CQFP器件板级温循可靠性的设计与仿真

温度循环是考核封装产品板级可靠性的重要试验之一。陶瓷四边引脚扁平封装(CQFP)适用于表面贴装,由于陶瓷材料与PCB热膨胀系数的差异,温循过程中引线互联部分产生周期性的应力应变,当陶瓷壳体面积较大时,焊点易出现疲劳失效现象。CQFP引线成形方式分顶部成形和底部成形两类。针对CQFP引线底部成形产品在板级温循中出现的焊接层开裂现象,采用有限元方法对焊接层的疲劳寿命进行了预测分析。采用二次成形方法对引线进行再次成形以缓解和释放热失配产生的应力。仿真和试验结果显示,引线二次成形有利于提高焊接层的温循疲劳寿命。与引线底部成形相比,当引线采用顶部成形时,焊接层的温循疲劳寿命显著提高。     

四边形激光陀螺的光束特性

为了对四边形激光陀螺进行更为深入的研究,了解其光束特性,运用传输矩阵,得到了四边形激光陀螺的稳定条件,并对四边形激光陀螺内部的高斯光束特性进行了数值计算,得到腔内实际上存在两条高斯光束,它们在两个球面镜处结合在一起。结果表明,球面镜的曲率半径越大,高斯光束的光斑半径越大,光束就越平直,越便于信号的读出。     

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.     

集成电路陶瓷外壳析出物失效模式分析

为了集成电路的可靠性保证,往往需要对集成电路外壳进行验收。验收项目中,有一个耐湿试验分组,用来加速评定外壳的抗腐蚀性能及相应的质量可靠性能。在该试验分组中发现,陶瓷外壳失效除了已有的常规模式外,还有一种很严重的析出物失效模式。发现焊框与陶瓷结合处有胶体状析出物,析出物以流质状态析出,然后凝固,严重的还会造成焊框漏气,从而引起外壳失效。     

Drop impact reliability analysis of CSP packages at board and product levels through modeling approaches

Chip scale package (CSP) and fine pitch ball grid array (BGA) packages have been increasingly used in portable electronic products such as mobile cell phones and PDA, etc. Drop impact which is inevitable during its usage could cause not only housing crack but also package to board interconnect failure, such as BGA solder breaks. Various drop tests have been used to ensure high reliability performance of packaging to withstand such impact and shock load. Due to extreme difficulty in directly measuring responses in solder joint during drop shock event, computer simulation based modeling approach has been increasingly played an important role in evaluating product reliability performance during product development. An advanced modeling technique with a comprehensive failure criterion including high strain rate effect needs to be developed to quantitatively evaluate package reliability performance especially in cross comparisons between different board and system level designs. In this paper, three drop tests have been modeled, namely, bare board drop, board with fixture drop or shock, and system level phone drop. Submodeling and explicit-implicit sequential modeling techniques are used to characterize the dynamic responses of CSP/BGA packages in different board designs. Failure criteria and effects of strain rate and edge support on BGA in multicomponent boards are also investigated. A validation test with data acquisition is used to correlate the test results with numerical results.     

Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact

Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability.     

Reliability studies of two flip-chip BGA packages using power cycling test

Power cycling tests of the second level reliability of two flip-chip BGA packages are discussed in this paper. The first one is for a flip-chip on laminate package (FCPBGA) and the other for a flip-chip on ceramic package (FCCBGA). For the FCPBGA, test strategies will be first discussed and then focus will be given to a unique failure mode associated with this type of packages assembled back to back onto printed circuit board. Instead of anticipated failures of the corner solder joints under the die shadow, as in the case of wire-bonded packages, we found that solder joints failed first in the central region of the package and then failures of solder joints spread out in the radial direction from the center of the package. Explanation will be given to the physical mechanisms that caused this type of failure. For the FCCBGA, the improved test strategies based on what has been learned from the test of FCPBGA will be presented and focus will be given to the effect of different parameters on the second level reliability of the package. Here, because of the increased rigidity of the ceramic substrate solder joints failed as expected first at the corner(s) of the ceramic substrate. Based on the test results and the modified Coffin–Manson equation, predictions or the solder joint fatigue life will be shown.     

金凸点键合工艺在国产陶瓷外壳中的应用

国产陶瓷外壳已经逐渐应用于高可靠要求的各类电子元器件的封装上。在IC封装过程中, 随着封装密度的提高,因其键合指状引线的质量难以满足键合工艺要求,为使其能达到工艺控制要求, 我们开发出一些相应的封装技术,提高了产品的可靠性。金凸点键合工艺用于提高国产陶瓷外壳键合指 上的键合引线强度有非常明显的效果,是一项较新的技术。     

Effects of Glue on the Bend Performance of Flip Chip Packages

To combat reliability margin loss in ball grid array (BGA) packages specifically in mechanical shock and vibration testing, companies are exploring the possibility of using glue and complete underfill to mitigate risk to second-level interconnects (SLI). Though glue has been demonstrated to have a positive influence on SLI reliability margin, it can have adverse affects on the rest of the package such as substrate or first-level interconnects (FLI). This paper explains details on how glue modulates the overall reliability of the package. Finite-element modeling (FEM) along with low strain rate bend tests was done to prove the effect of glue on solder joint reliability. Further, shock testing was done to demonstrate how the glue modulates the shock performance. The improvement in SLI reliability was highly dependent on the choice of glue.      

Semiconductor package qualification based on the swelling temperature

Currently, as semiconductor packages are becoming increasing smaller with improved performances, many are being constructed using stacked structures. However, these types of packages are not easy to qualify owing to the potential swelling of the stacked layers. In this paper, we propose a new method for reliability testing that directly measures the adhesion strength using the swelling temperature to assess the reliability of the package. The swelling temperature is the temperature at which a peel-off occurs between the layers. The advantage of the proposed method in comparison with the traditional reliability testing methods is that the proposed method enables a quick assessment of the product reliability. Through testing and actual case studies, we found that the product reliability qualification can be determined solely by measuring the swelling temperature.     

Vibration fatigue reliability of BGA-IC package with Pb-free solder and Pb–Sn solder

In this paper, a new method is proposed for evaluating the high-cycle fatigue strength of BGA (Ball Grid Array) packages with Pb-free solder and Pb–Sn solder due to vibration. An attached weight induced mixed mode stress in the solder ball of a package was used. To consider the effect of the mixed mode stress that occurred in a solder ball and the frequency to fatigue strength of the solder ball, a test was carried out with the three kinds of weights (σ_n/τ_n = 4, 5, and 6) at various frequencies (10–27 Hz). To clarify the effect of frequency, a nonlinear analysis with a viscoplastic model was carried out within the range of 0.001–3450 Hz. From the continuous observation of the cross-section of the package and finite element method (FEM) analysis results, it was revealed that the maximum principal stress is the driving force to package failure. Although an intermetallic compound in both packages and a Pb-rich region in a Pb–Sn solder based package were confirmed by EDX microprobe analysis, they do not contribute to the initiation of a crack in a solder ball. The fatigue strength of the Pb-free solder and Pb solder was evaluated on the basis of the maximum principal stress calculated by FEM and the experimental results.     

Board level reliability assessment of chip scale packages

A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.     

Effects of Different Kinds of Underfills and Temperature–Humidity Treatments on Drop Reliability of Board-Level Packages

The hygrothermal and mechanical reliability of board-level packages with various underfills under sequential temperature and humidity (TH) testing and drop testing were investigated. Board-level packages with underfill had greater resistance to drop shock than that without underfill, indicating that underfill protects the package from failure by absorption of the applied drop shock. The underfill, which was composed of polypropylene glycol epoxy resin and silane, exhibited good reliability for drop shock because of the improved adhesion of the underfill compared with that without the polypropylene glycol epoxy resin and silane. In addition, the drop reliability of board-level packages with underfill decreased with increasing TH test duration. Adhesion between the substrate and underfill or between the solder and underfill was decreased by moisture absorption. Components positioned at the board center were more susceptible to failure by drop shock than were corner components.     

Mechanical characterization of plastic ball grid array package flexure using moire interferometry

Most previous studies of PBGA packaging reliability focused on the effect of thermal cycling. However, as portable electronic products such as cellular phones and laptop computers are reduced in size and become more readily available, isothermal flexural fatigue also becomes an important reliability issue. Solder interconnects subjected to mechanically induced deformation may result in failure. In the current work, moire interferometry is used to investigate the influence of PCB flexure on interconnect strains. A versatile testing apparatus is developed to load PBGA packages in four point bending. Moire fringe patterns are recorded and analyzed at various bending loads to examine the variation in displacement and strain between the components. Solder balls across the entire array experience large shear strains, often resulting in plastic deformation, which reduces service life of the package.     

Thermomechanical Reliability Study of Flip Chip Solder Bumps: Using Laser Ultrasound Technique and Finite Element Method

Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and low throughput. As an alternative, a solder bump inspection system is being developed at Georgia Institute of Technology using laser ultrasound and interferometric techniques . This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the package surfaces using laser interferometric technique. The quality of solder bumps in electronic packages is evaluated by analyzing the transient responses. This paper presents a systematic study on thermomechanical reliability of flip chip solder bumps using laser ultrasound–interferometric inspection technique and finite element (FE) method. The correlation between the failure parameter extracted from FE simulation for evaluating solder bump reliability and quality degradation characterization of solder bumps through noncontact, nondestructive laser ultrasound testing has also been investigated.      

绝缘引线在陶瓷封装中的应用

随着半导体封装持续朝着多引脚、小节距及多列多层叠的方向发展,引线键合技术正面临越来越大的挑战。当陶瓷空封器件中的键合引线长度大于3.0 mm时,在加电冲击试验过程中键合引线容易出现瞬间的短路而导致器件失效。文章主要阐述了产生该问题的基本原因,提出了采用绝缘引线键合解决该问题的可行性,介绍了绝缘引线的基本特性,并用实际封装的电路进行了绝缘引线键合的可靠性研究,根据研究结果,提出了绝缘引线可有限应用于陶瓷封装的结论。     

Analysis of circularly polarized square ring and crossed-strip microstrip antennas

Segmentation technique coupled with cavity model have been used to analyze square ring and crossed-strip microstrip patch antennas for circular polarization. This technique is found to predict the characteristics of antennas correctly, as is evident from the close agreement between the calculated and measured results for resonant frequency, input impedance, radiation patterns, and bandwidth. Square ring antenna has been found to have larger impedance bandwidth and axial ratio bandwidth because of lowerQ. Crossed-strip antenna has larger size and thus fabrication tolerances can be relaxed.     

Materials characterization of the effect of mechanical bending on area array package interconnects

The mechanical integrity of solder joint interconnects in PWB assemblies with micro-BGA, chip scale, and land grid array packages is being questioned as the size and pitch decrease. Some consumer products manufacturers have mechanically reinforced fine pitch package interconnects with an adhesive underfill, and others are evaluating the need for underfill on a case-by-case basis. Three-point cyclic bend testing provides a useful tool for characterizing the expected mechanical cycling fatigue reliability of PWB assemblies. Cyclic bend testing is useful for characterizing bending issues in electronic assemblies such as repetitive keypad actuation in cell phone products. This paper presents the results of three-point bend testing of PWB assemblies with fine pitch packages. The solder joints on ceramic components performed better than a laminate interposer component in bend testing, because of the stiffening effect of the ceramic packaging materials. The methodology of materials analyses of the metallurgy of solder interconnects following mechanical bending and thermal cycle testing is described. The microstructure and fracture surfaces of solder joint failures in bend test samples differed significantly from thermal cycle test samples.     

高密度陶瓷倒装焊封装可靠性试验开路后的失效定位

陶瓷材料具有优良的综合特性,被广泛应用于高可靠微电子封装.陶瓷倒装焊封装的特殊结构使得对其进行失效分析相较其他传统封装形式更为困难.针对一款在可靠性试验中发生开路的高密度陶瓷倒装焊封装器件,制定了一套从非破坏性到破坏性的试验方案对其进行分析.通过时域反射计(TDR)测试排除了基板内部失效的可能性,通过X射线(X-ray)检测、超声扫描显微镜(SAM)和光学显微分析初步断定失效位置,并最终通过扫描电子显微镜和X射线能谱仪实现了对该器件的准确的失效定位,确定失效位置为基板端镀Ni层.该失效分析方法对其他陶瓷倒装焊封装的失效检测及分析有一定的借鉴意义.     

Evaluation of solder joint reliability in flip-chip packages during accelerated testing

The microstructural investigation and thermomechanical reliability evaluation of the Sn-3.0Ag-0.5Cu solder bumped flip-chip package were carried out during the thermal shock test of the package. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu₆Sn₅ intermetallic compound (IMC) layer, while the two phases which were (Cu,Ni)₆Sn₅ and (Ni,Cu)₃Sn₄ were formed between the solder and electroless Ni-P layer of the package side. The cracks occurred at the corner solder joints after the thermal shocks of 400 cycles. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally-activated solder fatigue failure. The premature brittle interfacial failure sometimes occurred in the package side, but nearly all of the failed packages showed the occurrence of the typical fatigue cracks. The finite-element analyses were conducted to interpret the failure mechanisms of the packages, and revealed that the cracks were induced by the accumulation of the plastic work and viscoplastic shear strains.