Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q_inv/L²––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V_GS and V_DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.     

CMOS放大器的温度补偿偏置

受载流子迁移率、阈值电压等参数的温度特性的影响，CMOS放大器往往具有较差的温度稳定性。本文介绍了一种基于恒跨导参考电流源偏置电路的温度补偿技术，理论分析和电路模拟结果显示，这种偏置方法对短沟道MOS管放大器也具有良好的温度补偿效果。     

Impact of gate induced drain leakage on overall leakage ofsubmicrometer CMOS VLSI circuits

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield     

A Robust and Scalable Constant-$g_m$ Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries

In this paper, we propose a robust and scalable constant- rail-to-rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p- and n-channel devices. Only standard CMOS transistors are used in the circuit without any special devices, such as floating-gate or depletion-mode transistors. Very small variations (less than ) have been achieved without sacrificing the large-signal behavior. The proposed circuit is proven effective for both long-channel and deep sub-micron CMOS technologies and is suitable for VLSI cell libraries, audio/video, embedded mixed-signal system-on-chip (SoC), and other applications. A prototype amplifier with rail-to-rail input common-mode range has been designed and fabricated in a standard 0.35-m CMOS technology. Experimental results confirm the effectiveness and robustness of proposed techniques.     

Subthreshold surface potential and drain current models for short-channel pocket-implanted MOSFETs

An analytical subthreshold surface potential model for short-channel pocket-implanted (double-halo) MOSFET is presented. The effect of the depletion layers around the source and drain junctions on channel depletion layer depth, which is very important for short-channel devices, is included. Using this surface potential, a drift-diffusion based analytical subthreshold drain current model for short-channel pocket-implanted MOSFETs is also proposed. A physically-based empirical modification of the channel conduction layer thickness that was originally proposed for relatively long-channel conventional device is made for such short-channel double-halo devices. Very good agreement for both the surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical device simulation using Dessis.     

Analysis of current conduction in short-channel accumulation-modeSOI PMOS devices

This paper reports a compact analytical current conduction model for short-channel accumulation-mode SOI PMOS devices. Based on the study, the current conduction mechanism in a short-channel accumulation-mode SOI PMOS device is different from that in a long-channel one. As verified by the experimental data, the compact analytical model considering channel length modulation and prepinchoff velocity saturation gives an accurate prediction of the drain current characteristics     

Analytical modeling of the subthreshold current in short-channel MOSFET's

In this paper an analytical model for subthreshold current for both long-channel and short-channel MOSFET's is presented. The analytical electrostatic potential derived from the explicit solution of a two-dimensional Poisson's equation in the depletion region under the gate for uniform doping is used. The case for nonuniform doping can easily be incorporated and will be published later. The results are compared to a numerical solution obtained by using MINIMOS, for similar device structures. An analytical expression for the channel current is obtained as a function of drain, gate, substrate voltages, and device parameters for devices in the subthreshold region. The short-channel current equation reduces to the classical long-channel equation as the channel length increases.     

Optically controlled current-voltage characteristics of ion-implanted MESFETs

Optically controlled MESFETs are useful as optical devices for optical communications, and as photodetectors. In this paper, a theoretical model for the I–V characteristics of these MESFETs is presented. The model considers the nonuniform Gaussian doping for ion-implanted channels. It takes both the photogenerated carriers as well as the doping generated residual carriers into account. It is noted that the density of photogenerated carriers in the channel due to diffusion is much less than that due to drift. Treatment both under gradual channel approximation and saturation velocity approximation has been presented. The gradual channel and the velocity saturation approximations are applied to study the I–V characteristics of long-channel and short-channel MESFETs, respectively. Results for both long-channel and short-channel MESFETs indicate that drain saturation current and transconductance can be improved by properly fixing the optical flux, and the absorption coefficient of the material.     

Subthreshold conduction in MOSFET's

The dependence of channel current in subthreshold operation upon drain, gate, and substrate voltages is formulated in terms of a simple model. The basic results are consistent with earlier approaches for long-channel devices. For short-channel devices, the variation of current with drain voltage up to the punch-through voltage is accurately described. The threshold voltage of a short-channel device as a function of applied voltages follows as a natural result of the derivation. Results are presented which confirm the theory over a wide range of drain and gate voltages. With the application of substrate bias it is concluded from the data and the theory that two-dimensional effects can cause dramatic increases in the drain conductance.     

CMOS工艺中抗闩锁技术的研究

伴随着CMOS工艺技术的发展,CMOS电路已经成为VLSI制造中的主流,而CMOS器件特征尺寸的快速缩小和CMOS电路的广泛应用,使得CMOS电路中的latch-up效应引起的可靠性问题也越来越受到大家的重视。阐述了CMOS工艺中闩锁的概念、原理及其给电路的可靠性带来的严重后果,深入分析了产生闩锁效应的条件、触发方式,并针对所分析的闩锁原因从版图设计、工艺改良、电路应用三个方面提出了一些防闩锁的优化措施,以满足和提高CMOS电路的可靠性要求。     

Determination of the spatial variation of interface trapped charge using short-channel MOSFET's

Previous measurements of interface trapped charge (ITC) by charge pumping used long-channel metal gate transistors. In this paper charge pumping is extended to short-channel Self-aligned polysilicon gate transistors and used to determine the spatial variation of ITC on wafers. Only the MOSFET gate area and a pulse frequency are required to calculate ITC density from the charge pumping current. In previous work, with long-channel devices, it appears that some investigators used the design dimension of metal gate devices and others used the metallurgical channel length of the transistors to calculate gate area. Two-dimensional simulation of the charge pumping measurement showed that, for a sufficient applied pulse height voltage, the correct area is obtained if the polysilicon gate length and width asmeasured are used. When the process-induced variation of the polysilicon gate length is included in the measurement analysis, no systematic variation of ITC is observed across 5 cm wafers. The charge pumping measurement technique on short-channel MOSFET's can be used to resolve the spatial variation of ITC if the area variations are correctly handled. The measurement of ITC is linear with frequency from 1 kHz to 1 MHz, indicating that the emission time constant of the fast states measured using this method is ≤10^-6s. A variation of ITC with channel lengths is also observed. This variation could not be detected using large area devices such as capacitors, but will have important consequences for short-channel MOSFET's.     

Latchup suppression in fine-dimension shallow p-well CMOS circuits

The high packing density required for VLSI CMOS circuits leads to enhanced performance of the inherent parasitic bipolar devices, and thus latchup becomes a major problem. One of the most attractive techniques for overcoming this is to fabricate the devices on n-on-n⁺epitaxial substrate material. This paper deals with latchup suppression by such a technique in fine-dimension CMOS circuits based on very shallow p-wells. Experimental results demonstrate that latchup may be eliminated in structures with p-well depths as shallow as 0.8 µm at supply voltages up to 10 V and temperatures up to 140°C. Furthermore, this may be achieved with no significant degradation of other aspects of device or circuit performance. A simple lumped model equivalent circuit has been used to predict latchup characteristics where appropriate, and in general this gives good agreement with experiment.     

On “effective channel length” in 0.1-μm MOSFETs

The conventional, 1-D definition of “effective channel length” (L_eff) is examined in light of the spatial dependence of channel sheet resistance in 0.1-μm MOSFETs calculated from a 2-D device model. For short-channel devices, the sheet resistance deviates significantly from the uniform, long-channel behavior that L _eff in general is different from the “metallurgical channel length”, L_met. While geometrical (charge-sharing) effects tend to make L_eff slightly shorter than L_met, lateral source-drain doping gradients, especially when coupled with retrograde channel doping, can make L_eff substantially longer than L_met. The latter might help explain the apparent “excess” short channel effect often observed in 0.1-μm CMOS devices     

基于小波分析的CMOS电路IDDT故障诊断新技术

对CMOS数字集成电路故障诊断技术的基本方法进行介绍,探讨了基于小波分析的CMOS电路瞬态电流IDDT故障诊断新技术的基本原理和作用。介绍了该故障诊断新技术的国内外研究动态,展望了其在超大规模集成电路的故障诊断、失效机理研究、可靠性提高等方面的作用、意义及其广阔的应用前景。     

A new I–V model for surrounding-gate MOSFET considering gate-voltage-dependent quantum effect

We present a new I–V model for a long-channel surrounding-gate (SG) metal–oxide–semiconductor field-effect transistor (MOSFET). SG MOSFET is a strong candidate for next generation nanoscale devices due to a high electrostatic channel control, which in turn substantially reduces the short-channel effect. The new model takes into account quantum mechanical (QM) effects in the SG MOSFET using a double triangular QM well model in the strong inversion regime. In contrast with the old model, we consider the V _g dependence of the QM effect. New model yields excellent agreement with 2-D numerical simulation results for various radii and gate oxide thicknesses of the SG MOSFET.     

Statistical modeling of MOS devices for parametric yield prediction

In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 μm CMOS technology, and measured data are included in support of the model calculations.     

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.     

High-speed, high-reliability circuit design for megabit DRAM

Circuit techniques for improving the speed and reliability of submicrometer geometry CMOS DRAMs are described. Double-bootstrap voltages are eliminated with an internal voltage supply and a unique word-line driver, reducing stress on short-channel devices. A row and column redundancy technique equivalent to physical disconnect of word lines and bit lines solves leakage problems. Speed enhancements are achieved through bit-line isolation for accelerated column access, a high-speed SRAM-style data path, and by tailoring sensing currents within the limitations of package inductance. The design of a fast 1-Mb DRAM employing these circuits is outlined     

Layout reconstruction of complex silicon chips

A semiautomated, fast-turnaround and high-reliability procedure for the layout reconstruction of complex VLSI circuits is presented together with details of the equipment and processes employed. The techniques have been verified using both simple CMOS gate array chips and complex VLSI microprocessor circuits and may be applied, in principle, to arbitrarily large or complex devices     

Novel circuit techniques for zero-power 25-ns CMOS erasable programmable logic devices (EPLDs)

A family of CMOS erasable programmable logic devices (EPLDs) is described with emphasis on the state-of-the-art chip architecture and circuit design techniques. The main features of this family of EPLDs include zero standby power, high-speed operation, flip-flop reconfigurability, small chip size, and high reliability. A novel input-transition-detection circuit allows the chip to consume no power during standby and yet wakes the chip up with minimum delay. Basic architectural differences between EPLDs and EPROM are discussed that require extra design considerations to achieve an optimal speed path through the array. A direct-drive technique is used in the transistor-transistor logic buffer and flip-flop circuits to improve speed, layout area, and chip organization.