Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model.In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.     

Robust tests for parity trees

Linear logic circuits are used extensively in digital computing and signal processing systems. They are constructed as regular arrays (for example as cascade or tree circuits), employing linear gates such as Exclusive OR (EOR) and Exclusive NOR (ENOR) gates. Earlier studies on fault diagnosis in linear logic circuits were based on the classical fault model of line stuck-at faults. Transistor stuck-open (SOP) and stuck-on (SON) faults in linear circuits were studied recently, but the effect of signal transients due to circuit delays and time skews in input changes were not considered in the derivation of test sequences. These latter factors are known to cause invalidation of two pattern tests for stuck-open faults. In this article we consider the problem of generating robust tests for linear logic circuits. These tests are not affected by circuit transients caused by delays. A major finding in this paper is that, if the test invalidation problem is redressed by introducing robust tests, the test length becomes a linear function of the depth of the circuit as opposed to the constant number of tests derived in previous studies, by neglecting circuit transients. A lower bound on minimum number of distinct test patterns needed for a tree of EOR gates of depthd is derived. This number depends on the specific implementation of the gate. Robust test-generation procedures are proposed for both single and multiple fault models and their optimalities are argued. Given that every gate in a parity tree is robustly testable, a test sequence that can test for all faults in the circuit, regardless of the nature of gate implementation, is calleduniversal robust test sequence for a parity tree. Finally we propose an optimal universal robust test sequence.     

Transistor-level to gate-level comprehensive fault synthesis for n-input primitive gates

In order to have a high level of confidence in system testing, more accurate fault models are needed. An accurate fault model cannot be attained unless all faults in the transistor-level (low level) are considered. However, these transistor-level faults must be mapped onto gate-level (higher level) so that the efficiency of fault simulation, fault emulation and test pattern generation at the gate-level is not sacrificed. This paper covers the static and dynamic single physical failures at transistor-level for static CMOS primitive gates and shows their effects in the output behavior in terms of gate-level faults. A specific fault pattern is proposed and a general formula to calculate the total number of static faults is concluded from these patterns for each type of gate regardless of its number of inputs. The dynamic nature of the physical faults included in the static fault list is evaluated and their cumulative effect on the timing at the circuit output is examined. A general formula for calculating propagation delay at the output due to resistive shorts and opens is derived and a delay fault pattern with variable defect resistance is provided.     

On the generation of test patterns for multiple faults

This article presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in FAN and SOCRATES algorithms to guide the search part of the algorithm, and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.     

FsmTest: Functional test generation for sequential circuits

This paper presents a new approach to test pattern generation for sequential circuits modeled as finite state machines. This approach is well suited for controller synthesis, because such devices are usually represented as explicit finite state machines. Based on a functional fault model, only a restricted set of transitions of the finite state machine (FSM) is considered for the purpose of testing. A new state discriminating sequence, referred to as EUIO is proposed. Overlapping is accomplished to reduce the test length. In most cases, test length and CPU time requirements are substantially lower compared with gate-level ATPGs. Techniques are also introduced to preserve a high fault coverage. Evaluation on MCNC benchmarks has shown the effectiveness of the test algorithm both at functional and gate levels, while achieving in most cases 100% coverage of single stuck-at faults.     

Experimental Results for Self-Dual Multi-Output Combinational Circuits

In this short note, the possibilities and the limitations for the application of self-dual circuits with alternating inputs are experimentally investigated. The original circuit is assumed to be given as a netlist of gates. The necessary area overhead, the fault coverage for single stuck-at faults in test mode and the error detection probability in on-line mode due to internal stuck-at faults and stuck-at faults at the input lines are determined for MCNC benchmark circuits.     

Delay fault propagation in synchronous sequential circuits

Compared with the propagation of logic errors produced by stuck-at faults, the propagation of gate delay fault effects in sequential circuits poses some particular problems. The authors first describe the propagation conditions of such faults then define the propagation rules of these faults which are used in a new delay fault simulation process for synchronous sequential circuits     

Testability of parity checkers

Checkers are used in digital circuits to detect both intermittent and stuck-at faults. The most common error detectors are parity checkers. Such circuits are themselves subject to failures. The use of parity trees is outlined, and techniques for testing them are surveyed. The effect of the checker's structure on its testability is discussed. Several fault models are considered: single stuck-at, multiple stuck-at, and bridging faults. The effectiveness of single stuck-at fault test sets in detecting multiple stuck-at and bridging faults is described. Upper bounds for the double fault coverage of the minimal single fault test are given for different tree structures. The testabilities of some selected checkers are examined to illustrate the concepts developed. A built-in self-test is proposed     

A neural network algorithm for testing stuck-open faults in CMOS combinational circuits

In this article, an automatic test pattern generation technique using neural network models for stuck-open faults in CMOS combinational circuits is presented. For a gate level fault model of stuck-open faults in CMOS circuits, SR(slow-rise) and SF(slow-fall) gate transition faults we develop a neural network representation. A neural network computation technique for generating robust test patterns for stuck-open faults is given. The main result is extending previous efforts in stuck-at test pattern generation to stuck-open test pattern generation using neural network models. A second result is an extension of the technique to robust test pattern generation.     

Functional fault models for non-scan sequential circuits

The paper presents two functional fault models that are applied for functional delay test generation for non-scan synchronous sequential circuits: the pin pair state (PPS) fault model and the pin pair full state (PPFS) fault model. The PPS fault model deals with the pairs of stuck-at faults on the primary inputs and the primary outputs, as well as, with the pairs of stuck-at faults on the previous state bits and the primary outputs. The PPFS fault model encompasses the PPS model, and additionally deals with the pairs of stuck-at faults on the primary inputs and the next state bits, as well as, with the pairs of stuck-at faults on the previous state bits and the next state bits. The main factor in assessing the quality of obtained test sequences was the transition fault coverage at the gate level of the selected according to the appropriate fault model test sequences from the generated randomly ones. The experimental results demonstrate that the implementation using presented functional fault models allow selecting the test sequences from the initial test set without the loss of transition fault coverage in many cases, and the number of the selected test sequences is much lesser than that of the initial test set. This result demonstrates that the functional delay test can be generated using the presented functional delay fault models before structural synthesis of the circuit.     

Self-checking CMOS circuits using pass-transistor logic

This article presents a new approach to implementing self-checking circuits in CMOS technology. Implementations are made self-checking with respect to a single line stuck-at 0/1 fault. It is assumed that stuck faults at a common gate of neighboring PMOS and NMOS are not independent and the contact between a PMOS (NMOS) source and a power (ground) line is fault free. Self-checking error checkers for parity, two-rail code, and m-out-of-n code are designed using pass-transistor logic and then verified by fault simulation.     

Symbolic fault modelling of MOS combinational circuits

This paper presents a new method for fault modelling of MOS combinational circuits at the transistor level. Every transistor is replaced with a conductance controlled by the gate logic value. The specific advantage of the method is use of a symbolic simulator for circuit function extraction. This function is referred as Transistor Logic Conductance Function (TLCF). Starting from a known TLCF, a simple set of rules is used for output state determination. The method is suitable for multiple fault model generation thanks to the fact that only one symbolic analysis of a circuit is sufficient for modelling different stuck-open, stuck-short and stuck-at faults of a logic gate. Moreover, the method can deal also with bridging and cut faults. Finally, the application of the TLCF for test pattern generation is considered.     

Test generation for technology-specific multi-faults based on detectable perturbations

In this paper, we introduce the concept of detectable perturbations as a method to generate tests that cover any technology-specific faults such as multiple bridging, open and stuck-at faults. Rather than devising a customized test pattern generation system for each class of technology-specific faults, we implemented a generic system to generate tests for single and multiple perturbations. We demonstrate the versatility of this approach by generating tests for a set of large benchmark circuits that have been mapped into single- and multi-output modules. These tests cover single stuck-at, multi-output bridging, stuck-at, as well as any mutation faults in the functionality of the technology-mapped cells. Experimental results provide useful insights about the quality of single stuck-at test patterns versus coverages for the additional classes of faults.     

RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences

Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. However, they suffer from low defect coverage since they are mostly derived in practice from existing design-verification test sequences. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a DFT method that uses the register-transfer level (RTL) output deviations metric to select observation points for an RTL design and a given functional test sequence. Simulation results for six ITC′99 circuits show that the proposed method outperforms two baseline methods for several gate-level coverage metrics, including stuck-at, transition, bridging, and gate-equivalent fault coverage. Moreover, by inserting a small subset of all possible observation points using the proposed method, significant fault coverage increase is obtained for all benchmark circuits.     

Logic Design Validation via Simulation and Automatic Test Pattern Generation

We investigate an automated design validation scheme for gate-level combinational and sequential circuits that borrows methods from simulation and test generation for physical faults, and verifies a circuit with respect to a modeled set of design errors. The error models used in prior research are examined and reduced to five types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), wrong input errors (WIEs), and latch count errors (LCEs). Conditions are derived for a gate to be testable for GSEs, which lead to small, complete test sets for GSEs; near-minimal test sets are also derived for GCEs. We analyze undetectability in design errors and relate it to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. These experiments demonstrate that high coverage of the modeled errors can be achieved with small test sets obtained with standard test generation and simulation tools for physical faults.     

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits

Reversible logic has gained interest of researchers worldwide for its ultra-low power and high speed computing abilities in the future quantum information processing. Testing of these circuits is important for ensuring high reliability of their operation. In this work, we propose an ATPG algorithm for reversible circuits using an exact approach to generate CTS (Complete Test Set) which can detect single stuck-at faults, multiple stuck-at faults, repeated gate fault, partial and complete missing gate faults which are very useful logical fault models for reversible logic to model any physical defect. Proposed algorithm can be used to test a reversible circuit designed with k-CNOT, Peres and Fredkin gates. Through extensive experiments, we have validated our proposed algorithm for several benchmark circuits and other circuits with family of reversible gates. This algorithm produces a minimal and complete test set while reducing test generation time as compared to existing state-of-the-art algorithms. A testing tool is developed satisfying the purpose of generating all possible CTS’s indicating the simulation time, number of levels and gates in the circuit. This paper also contributes to the detection and removal of redundant faults for optimal test set generation.