Effects of localized contamination with copper in MOSFETs

Using a relatively large size MOSFET (W/L= 15/15 /spl mu/m), we investigated the degradation of MOSFET characteristics due to localized copper contamination. In order to contaminate a part of the active region of MOSFET, silicon nitride (Si/sub 3/N/sub 4/) over the active region, which is known to be a protective film against copper, was etched by reactive ion etching (RIE). As the area of localized copper contamination is about 3-4 /spl mu/m or above, apart from the edge of the gate electrode, no degradation was observed after thermal treatment at 450/spl deg/C for 2 h in N/sub 2/ ambient, based on the result of the increase in interface trap density (/spl Delta/D/sub it/).     

Near room-temperature continuous-wave operation of all-monolithic InAlGaAs/InP 1.3 /spl mu/m VCSELs

InAlGaAs/InP-based all-monolithic 1.3 /spl mu/m VCSELs operating continuous wave up to 18/spl deg/C are demonstrated. The whole structure is grown by a single step of MOCVD. Selective wet etching of an InP layer is used to form an air-gap aperture for the current confinement. The threshold current of an 8 /spl mu/m device at 15/spl deg/C is /spl sim/2.8 mA.     

Particle adhesion and removal mechanisms in post-CMP cleaning processes

Chemical mechanical polishing (CMP) is considered as the paradigm shift that enabled optical photolithography to continue down to 0.12 /spl mu/m. Currently, the polishing physics is not well defined though it is known that the nature of the process makes particle removal after CMP difficult and necessary. It is important to understand the particle adhesion mechanisms resulting from the polishing process and the effect-of the adhering force on particle removal in post-CMP cleaning processes. In this paper, strong particle adhesion is shown to be caused by chemical reactions (after initial hydrogen bonding) that take place in the presence of moisture and long aging time. In particle removal using brush cleaning, contact between the particle and the brush is essential to the removal of submicron particles. In noncontact mode, 0.1-/spl mu/m particle can hardly be removed when the brush is more than 1 /spl mu/m away from the particle. While in full contact mode, removal is possible for a 0.1-/spl mu/m particle at the investigated brush rotational speeds. The experimental data shows that high removal efficiency (low number of defects) is possible with a high brush pressure and a short cleaning time.     

激光改性硅酸盐玻璃表面局域制备金属铜层

为了实现普通硅酸盐玻璃表面的金属化,利用波长为355nm的脉冲紫外激光刻蚀粗化活化,并结合化学镀,在其表面局域制备出了导电金属铜层。研究了激光加工参量对玻璃表面微观形貌、粗糙度、刻蚀深度的影响规律,并在玻璃表面成功引入了钯元素。结果表明,当第1次紫外激光扫描速率为200mm/s、脉冲频率为100kHz、能量密度为27J/cm2~37J/cm2和填充间距在10μm左右时,玻璃表面可以获得的刻蚀深度在25μm~35μm之间,刻蚀区域的粗糙度R_a在6μm~7μm之间,此时玻璃不会开裂;而第2次激光的能量密度在9J/cm2~11J/cm2之间时（其余参量不变）,钯元素的引入实现了化学镀铜,此时铜层和玻璃之间的平均结合强度可以达到10MPa以上,铜层的体积电阻率可以达到10-6Ω·cm数量级。这是一种具有局域选择性、无需掩模、低成本、高结合强度和良好导电性的玻璃表面金属化工艺。     

Low-cost 1.55-/spl mu/m InGaAsP-InP spot size converted (SSC) laser with conventional active layers

We report the realization of a low cost 1.55-/spl mu/m spot size converted (SSC) laser using conventional SCH-MQW active layers. The laser consists of a rectangular gain section, a linear taper and a passive waveguide. The lateral taper and the passive waveguide are fabricated on the same lower SCH layer, using conventional photolithography and RIE (reactive ion etching). The device exhibits low beam divergence of 6.6/spl deg//spl times/10.9/spl deg/ and -2.2-dB coupling loss with a cleaved single-mode fiber. The 1-dB alignment tolerance is /spl plusmn/2.15 /spl mu/m in vertical direction and /spl plusmn/2.3 /spl mu/m in lateral direction, respectively.     

A fault-tolerant 256K RAM fabricated with molybdenum-polysilicon technology

Describes a 256K molybdenum-polysilicon (Mo-poly) gate dynamic MOS RAM using a single transistor cell. Circuit technologies, including a capacitive-coupled sense-refresh amplifier and a redundant circuitry, enable the achievement of high performance in combination with Mo-poly technology. Electron-beam direct writing and dry etching technologies are fully utilized to make 1 /spl mu/m accurate patterns. The 256K word/spl times/1 bit device is fabricated on a 5.83 mm/spl times/5.90 mm chip. Cell size is 8.05 /spl mu/m/spl times/8.60 /spl mu/m. The additional 4K spare cells and the associated circuits, in which newly developed electrically programmable elements are used, occupy less than 10 percent of the whole chip area. The measured access time is 160 ns under V/SUB DD/=5 V condition.     

Spectral engineering of terahertz quantum cascade lasers using focused ion beam etched photonic lattices

Focused ion beam etching has been used to introduce one-dimensional photonic lattices, of periods 9.11, 9.24, 9.44 /spl mu/m, between the cleaved facets of three 4.44 THz Fabry-Perot quantum cascade lasers. Singlemode lasing has been achieved at precisely defined wavelengths of 67.59, 68.48, 70.00 /spl mu/m, respectively.     

Performance enhancement by using the n/sup +/-GaN cap layer and gate recess technology on the AlGaN-GaN HEMT fabrication

Due to the low mobility and wide bandgap characteristics of the undoped AlGaN layer used in the conventional AlGaN-GaN HEMT as a cap layer, the RF performance of this device will be limited by its high contact resistance and high knee voltage. In this letter, we propose using the n/sup +/-GaN cap layer and the selective gate recess etching technology on the AlGaN-GaN HEMTs fabrication. With this n/sup +/-GaN instead of the undoped AlGaN as a cap layer, the device contact resistance is reduced from 1.0 to 0.4 /spl Omega//spl middot/mm. The 0.3 /spl mu/m gate-length device demonstrates an I/sub ds,max/ of 1.1 A/mm, a g/sub m,max/ of 220 mS/mm, an f/sub T/ of 43 GHz, an f/sub max/ of 68 GHz, and an output power density of 4 W/mm at 2.4 GHz.     

应用于MEMS封装的TSV工艺研究

开展了应用于微机电系统(MEMS)封装的硅通孔(TSV)工艺研究,分析了典型TSV的工艺,使用Bosch工艺干法刻蚀形成通孔,气体SF6和气体C4F8的流量分别为450和190 cm3/min,一个刻蚀周期内的刻蚀和保护时长分别为8和3 s;热氧化形成绝缘层;溅射50 nm Ti黏附阻挡层和1μm Cu种子层;使用硫酸铜和甲基磺酸铜体系电镀液电镀填充通孔,比较了双面电镀和自下而上电镀工艺;最终获得了硅片厚度370μm、通孔直径60μm TSV加工工艺。测试结果证明:样品TSV无孔隙;其TSV电阻值小于0.01Ω;样品气密性良好。     

氧化铝陶瓷基板化学镀铜金属化及镀层结构

通过化学镀铜在氧化铝陶瓷基板表面实现了金属化,采用SEM研究了镀铜层表面微观形貌以及热处理的影响,检测分析了金属化镀层附着力。结果表明:通过控制镀液中铜离子浓度以及铜沉积速率,在基板表面可形成均匀致密的铜金属化层;热处理后进一步提高镀层致密化和导电性,其方阻由3.6 mΩ/□降为2.3 mΩ/□。划痕法测试表明镀铜层与氧化铝陶瓷基板结合紧密无起翘,可以满足敷铜基板的要求。     

A high-Q quasi-planar filtering solution for 60-GHz applications

A low insertion loss 2.2% bandwidth two-pole cavity filter was fabricated at 60 GHz by bonding metallized lids on each side of a 250-/spl mu/m silicon substrate. The lids are made by dry etching of a 500-/spl mu/m silicon substrate. The same process is used to etch via holes on the intermediate substrate. The position of these via holes fixes the external coupling and the coupling between the resonators. The measured unloaded quality factor is lied on the height of the cavity (1.05 mm) and is around 1100.     

Via etching through extremely thick organic dielectrics

A process for etching vias in extremely thick (85 to 152 /spl mu/m) HD MicroSystems polyimide PI2611 was developed using commercial reactive ion etching tools. Sloped via profiles were obtained using a combination of hard masks made of aluminum and silicon dioxide thin films, combined with reactive ion etch steps in pure O/sub 2/ and O/sub 2//CF/sub 4/. The deep via profiles provided good step coverage. These vias, coated with a 3-/spl mu/m-thick copper film, produced satisfactory electrical continuity between layers of package interconnects. The process is reproducible, reliable, and, hence, practically useful for fabricating a small number of parts in spite of extended etch periods.     

Low-loss InGaAsP/InP submicron optical waveguides fabricated by ICP etching

The fabrication and characterisation of low-loss InGaAsP/InP optical submicron waveguides made with ICP etching is reported. Their width ranges from 0.2 to 2 /spl mu/m. For the 0.5 /spl mu/m width, the propagation losses at /spl lambda/=1.55 /spl mu/m as low as 4.2 dB/mm have been measured.     

Improvement of InGaN-GaN light-emitting diodes with surface-textured indium-tin-oxide transparent ohmic contacts

Presents a surface-textured indium-tin-oxide (ITO) transparent ohmic contact layer on p-GaN to increase the optical output of nitride-based light-emitting diodes (LED) without destroying the p-GaN. The surface-textured ITO layer was prepared by lithography and dry etching, and dimensions of the regular pattern were approximately 3 /spl times/ 3 /spl mu/m. The operating voltage of the surface-textured LED was almost the same as that of the typical planar LED since the ITO layer was in ohmic contact with the p-GaN. The experimental results indicate that the surface-textured ITO layer is suitable for fabricating high-brightness GaN-based light emitting devices.     

Surface-emitting device with embedded circular grating coupler for possible application to optoelectronic integrated devices

A surface-emitting device with an embedded circular grating coupler is developed. A uniform grating coupler with 0.4-/spl mu/m pitch and 0.15-/spl mu/m depth is fabricated by electron beam lithography and reactive ion etching. The grating is well embedded by an overgrown layer. It is shown that the lasing oscillation is successfully achieved up to the measured temperature of 196 K where the absorption loss at the grating coupler is well suppressed, and a stable single-longitudinal-mode oscillation is obtained.     

Electrically-pumped vertical-cavity lasers with Al/sub x/O/sub y/-GaAs reflectors

We have fabricated the first electrically-pumped vertical-cavity surface-emitting lasers (VCSELs) which use oxide-based distributed Bragg reflectors (DBRs) on both sides of the gain region. They require a third the epitaxial growth time of VCSELs with semiconductor DBRs. We obtain threshold currents as low as 160 /spl mu/A in VCSELs with an active area of 8 /spl mu/m/spl times/8 /spl mu/m using a two quantum well InGaAs-GaAs active region. By etching away mirror pairs from the top reflector, quantum efficiencies as high as 61% are attained, while still maintaining a low threshold current of 290 /spl mu/A.     

Improvement of light extraction efficiency of flip-chip light-emitting diode by texturing the bottom side surface of sapphire substrate

A high light-extraction efficiency was demonstrated in the flip-chip light-emitting diode (FCLED) with a textured sapphire substrate. The bottom side of a sapphire substrate was patterned using a dry etching process to increase the light-extraction efficiency. Light output power measurements indicated that the scattering of photons emitted in the active layer was considerably enhanced at the textured sapphire substrate resulting in an increase in the probability of escaping from the FCLED. The light-output power of the FCLED was increased by 40.2% for a 0.4-/spl mu/m deep FCLED with a periodic distance of 13-/spl mu/m mesh-type texture on the bottom side of the sapphire substrate.     

Bumpless interconnect through ultrafine Cu electrodes by means of surface-activated bonding (SAB) method

In this paper, we demonstrate the feasibility of ultrahigh-density bumpless interconnect by realizing the ultrafine pitch bonding of Cu electrodes at room temperature. The bumpless interconnect is a novel concept of bonding technology that enables a narrow bonding pitch of less than 10 /spl mu/m by overcoming the thermal strain problem. In the bumpless structure, two thin layers including an insulator and metallic interconnections on the same surface are bonded at room temperature by the surface-activated bonding (SAB) method. In order to realize the bumpless interconnect, we invented a SAB flip-chip bonder that enabled the alignment accuracy of /spl plusmn/1 /spl mu/m in the high vacuum condition. Moreover, the fabrication process of ultrafine Cu electrodes was developed by using the damascene process and reactive ion beam etching (RIE) process, and the bumpless electrodes of 3 /spl mu/m in diameter, 10 /spl mu/m in pitch, and 60 nm in height were formed. As a result, we succeeded in the interconnection of 100 000 bumpless electrodes with the interfacial resistance of less than 1 m/spl Omega/. An increase of the resistance was considerably small after thermal aging at 150/spl deg/C for 1000 h.     

A 35 ns 2K /spl times/ 8 HMOS static RAM

This paper describes the circuit design and process techniques used to produce a 35-ns 2K /spl times/ 8 HMOS static RAM aimed at future high-end microprocessor applications. The circuit design uses predecoding of the row and column decoder/driver circuits to reduce active power, address-transition detection schemes to equalize internal nodes, and dynamic depletion-mode configurations for increased drive and speed. The technology is 2.5-3.0-/spl mu/m design rule HMOS employing an L/SUB eff/ of 1.7 /spl mu/m, t/SUB ox/=400 /spl Aring/, double-poly resistor loads, RIE and plasma etching, and wafer-stepper lithography. Using these techniques an access time of 35 ns, dc active power of 65 mA, standby power of 14 mA, and die size of 37.5K mil/SUP 2/ has been achieved. The cell size is 728 /spl mu/m/SUP 2/.     

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

The authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si/low-k 65-nm CMOS technology. Sets of 330 mm wafers with active devices such as 65-nm MOSFETs and 4-MB SRAMs were bonded face-to-face using copper pads with size ranging between 5 /spl mu/m/spl times/5 /spl mu/m and 6 /spl mu/m/spl times/40 /spl mu/m. The top wafers were thinned to different thicknesses in the range 5 to 28 /spl mu/m. Through-silicon-vias (TSVs) and backside metallization were used to enable electrical testing of both wafers in the Cu-stacked configuration. We tested individual transistors in the thinned silicon of bonded wafer pairs where the thinned silicon thickness ranged from 14 to 19 /spl mu/m. All results showed that both n- and p-channel transistors preserved their electrical characteristics after Cu bonding, thinning, and TSV integration. We also demonstrated the functionality of stacked 65-nm 4-MB SRAMs by independently testing the cells in both the thinned wafer and the bottom wafer. For the SRAM, we tested a wider thinned wafer thickness range from 5 to 28 /spl mu/m. On all tested samples, we did not find any impact to the electrical performance of the arrays resulting from the three-dimensional (3-D) integration process. The stacked SRAM is an experimental demonstration of the use of 3-D integration to effectively double transistor packing density for the same planar footprint. The results presented in this letter enable further exploratory work in high-performance 3-D logic, which takes advantage of the improved interconnect delays offered by this Cu-bonding stacking scheme integrated with modern CMOS processes.