An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributedtrack-and-hold preprocessing

An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm² in 0.5-μm standard digital CMOS technology     

A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip

A low-power three-dimensional (3-D) rendering engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel rendering logic are logically localized with a 3.2-GB/s runtime reconfigurable bus, reducing the area by 25% compared with conventional local frame-buffer architectures. The low power consumption is achieved by polygon-dependent access to the embedded DRAM macros with line-block mapping providing read-modify-write data transaction. The 3-D rendering engine with 2.22-Mpolygons/s drawing speed was fabricated using 0.18-/spl mu/m CMOS embedded memory logic technology. Its area is 24 mm/sup 2/ and its power consumption is 120 mW.     

A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosinetransform core processor with variable threshold-voltage (VT)scheme

A 4 mm², two-dimensional (2-D) 8×8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V _DD-V_th design space is also studied     

A 7.1-GB/s low-power rendering engine in 2-D array-embedded memorylogic CMOS for portable multimedia system

A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping, memory-coupled logic pipeline, low-power operation, 7.1-GB/s memory bandwidth, and 11.1-Mpolygon/s drawing speed. The 56-mm² prototype die integrating one edge processor, eight pixel processors, eight frame buffers, and a RISC core are fabricated using 0.35-μm CMOS embedded memory logic (EML) technology with four poly layers and three metal layers. The fabricated test chip, 590 mW at 100 MHz 3.3 V operation, is demonstrated with a host PC through a PCI bridge     

A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System

A 32-bit fixed-point logarithmic arithmetic unit is proposed for the possible application to mobile three-dimensional (3-D) graphics system. The proposed logarithmic arithmetic unit performs division, reciprocal, square-root, reciprocal-square-root and square operations in two clock cycles and powering operation in four clock cycles. It can program its number range for accurate computation flexibility of 3-D graphics pipeline and eight -region piecewise linear approximation model for logarithmic and antilogarithmic conversion to reduce the operation error under 0.2%. Its test chip is implemented by 1-poly 6-metal 0.18-mum CMOS technology with 9-k gates. It operates at the maximum frequency of 231 MHz and consumes 2.18 mW at 1.8-V supply     

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications

A 121-mm/sup 2/ graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine, a programmable power optimizer, and 29-Mb embedded DRAM. The chip is built in a 0.16-/spl mu/m pure DRAM technology to reduce the fabrication cost. Texture-mapped 3-D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of depth-first clock gating, address alignment logic, and embedded DRAM. Programmable clocking allows the LSI to operate in lower power modes for various applications. The chip consumes less than 210 mW, delivering 66 Mpixels/s and 264 Mtexel/s texture-mapped pixels with real-time special effects such as full-scene antialiasing and motion blur.     

A 1.2-million transistor, 33-MHz, 20-b dictionary search processor(DISP) ULSI with a 160-kb CAM

A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI has been developed using a 0.8-μm triple-layer-Al, CMOS fabrication technology. A 13.02×12.51-mm² chip contains a specially developed 160-kb content addressable memory (CAM) and cellular automation processor (CAP). A single DISP chip can store a maximum of 2048 words, and performs dictionary search in various search modes, including an approximate word search. The character input rate for the dictionary search operation is 33 million characters per second. The DISP typically consumes 800 mW at a supply voltage of 5 V. A high-speed, functional 50000 word dictionary search system can be built with 25 DISP chips arranged in parallel, to play an important role in natural language processing     

A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals

A low-power three-dimensional (3-D) rendering engine with two texture units and 29-Mb embedded DRAM is designed and integrated into an LSI for mobile third-generation (3G) multimedia terminals. Bilinear MIPMAP texture-mapped 3-D graphics can be realized with the help of low-power pipeline structure, optimization of datapath, extensive clock gating, texture address alignment, and the distributed activation of embedded DRAM. The scalable performance reaches up to 100 Mpixels/s and 400 Mtexels/s at 50 MHz. The chip is implemented with 0.16-/spl mu/m pure DRAM process to reduce the fabrication cost of the embedded-DRAM chip. The logic with DRAM takes 46 mm/sup 2/ and consumes 140 mW at 33-MHz operation, respectively. The 3-D graphics images are successfully demonstrated by using the fabricated chip on the prototype PDA board.     

A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-/spl mu/m CMOS

A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-/spl mu/m CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc.     

A 152-mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG

This paper presents a low power multimedia system-on-chip (SoC) with full integration with fully programmable 3-D graphics, MPEG4 codec, H.264 decoder, and JPEG codec for mobile devices. The mobile unified shader in 3-D graphics engine provides fully programmable 3-D graphics with 35% area and 28% power reduction. Low-power lighting engine which employs logarithmic number datapath and the specialized lighting instruction enable 9.1 Mvertices/s vertex fill rate, which is 2.5 times improvement compared with previous works including transformations and OpenGL lighting. The SoC consumes less than 152 mW for video applications and less than 195 mW for 3-D graphics applications. The mobile unified shader and merged JPEG/MPEG4 codec reduce the silicon area and the SoC consumes 6.4 mm $times,$ 6.4 mm in 0.13 $mu$ m complementary metal–oxide–semiconductor (CMOS) logic process.      

Signaling for multimedia conferencing in 4G: the case of integrated 3G/MANETs

Fourth-generation wireless systems are composed of coexisting and cooperating legacy and new networks. Mobile ad hoc networks are examples of new networks. They have several attractive characteristics and are gaining more and more momentum. Their integration with legacy third-generation networks is now being contemplated. Multimedia conferencing is the basis of a wealth of applications, including video conferences, multiparty games, and distance learning. Signaling is the central nerve of multimedia conferencing. It establishes, modifies, and tears down multimedia conferencing applications. This article is devoted to the signaling aspects of multimedia conferencing in 4G and focuses on the specific case of integrated 3G/MANETs. It reviews the standard 3G architecture and the emerging architectures for MANETs. This review shows that none of them is suitable for integrated 3G/MANETs. We propose a new architecture based on application-level clusters and conference gateways. We have implemented a prototype using the session initiation protocol (SIP) technology.     

An integrated resource negotiation, pricing, and QoS adaptationframework for multimedia applications

We study a dynamic, usage- and congestion-dependent pricing system in conjunction with price-sensitive user adaptation of network usage. We first present a resource negotiation and pricing (RNAP) protocol and architecture to enable users to select and dynamically renegotiate network services. We develop mechanisms within the RNAP architecture for the network to dynamically formulate prices and communicate pricing and charging information to the users. We then outline a general pricing strategy in this context. We discuss candidate algorithms by which applications (singly, or as part of a multi-application system) can adapt their rate and QoS requests, based on the user-perceived value of a given combination of transmission parameters. Finally, we present experimental results to show that usage- and congestion-dependent pricing can effectively reduce the blocking probability, and allow bandwidth to be shared fairly among applications, depending on the elasticity of their respective bandwidth requirements     

2-μm, 1.6-mW gated-gm sampler with 72-dB SFDR for fs=160 Ms/s and fin=320.25 MHz

The sampler is often the limitation in determining how early in the signal chain the conversion to discrete time can be done. We have fabricated a novel high-speed, wideband sampler core based upon a charge-domain gated-g_m cell that has a measured spurious free dynamic range (SFDR) of 72 db for a sample rate of 160 Ms/s and an input frequency of 320.25 MHz. The sampling bandwidth is ~880 MHz. This performance is achieved at ~1% of the power and ~1% of the core area of a state-of-the-art track-and-hold circuit implemented in a much more advanced IC technology. Simulations indicate that far higher performance is possible in a more advanced process and with minor circuit optimization     

A V-band front-end with 3-D integrated cavity filters/duplexers and antenna in LTCC technologies

This paper presents a compact system-on-package-based front-end solution for 60-GHz-band wireless communication/sensor applications that consists of fully integrated three-dimensional (3-D) cavity filters/duplexers and antenna. The presented concept is applied to the design, fabrication, and testing of V-band (receiver (Rx): 59-61.5 GHz, transmitter (Tx): 61.5-64 GHz) transceiver front-end module using multilayer low-temperature co-fired ceramic technology. Vertically stacked 3-D low-loss cavity bandpass filters are developed for Rx and Tx channels to realize a fully integrated compact duplexer. Each filter exhibits excellent performance (Rx: IL<2.37 dB, 3-dB bandwidth (BW) /spl sim/3.5%, Tx: IL<2.39 dB, 3-dB BW /spl sim/3.33%). The fabrication tolerances contributing to the resonant frequency experimental downshift were investigated and taken into account in the simulations of the rest devices. The developed cavity filters are utilized to realize the compact duplexers by using microstrip T-junctions. This integrated duplexer shows Rx/Tx BW of 4.20% and 2.66% and insertion loss of 2.22 and 2.48 dB, respectively. The different experimental results of the duplexer compared to the individual filters above are attributed to the fabrication tolerance, especially on microstrip T-junctions. The measured channel-to-channel isolation is better than 35.2 dB across the Rx band (56-58.4 GHz) and better than 38.4 dB across the Tx band (59.3-60.9 GHz). The reported fully integrated Rx and Tx filters and the dual-polarized cross-shaped patch antenna functions demonstrate a novel 3-D deployment of embedded components equipped with an air cavity on the top. The excellent overall performance of the full integrated module is verified through the 10-dB BW of 2.4 GHz (/spl sim/4.18%) at 57.45 and 2.3 GHz (/spl sim/3.84%) at 59.85 GHz and the measured isolation better than 49 dB across the Rx band and better than 51.9 dB across the Tx band.     

A 2.2-mW CMOS bandpass continuous-time multibit /spl Delta/-/spl Sigma/ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications

A delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter featuring 68-dB dynamic range and 64-dB signal-to-noise ratio in a 1-MHz bandwidth centered at an intermediate frequency of 2 MHz with a 48-MHz sample rate is reported. A second-order continuous-time modulator employing 4-bit quantization is used to achieve this performance with 2.2 mW of power consumption from a 1.8-V supply. The modulator including references occupies 0.36 mm/sup 2/ of die area and is implemented in a 0.18-/spl mu/m five-metal single-poly digital CMOS process.     

An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications

A high-speed three-dimensional (3-D) graphics SoC for consumer applications is presented. A 166-MHz 3-D graphics full pipeline engine with performance of 33 Mvertices/s and 1.3Gtexels/s, and 333-MHz ARM11 RISC processor, and video composition IPs are integrated together on a single chip. The geometry part of 3-D graphics IP provides full programmability in vertex and triangle level, and two-level multi-texturing with trilinear MIPMAP filtering are realized in the rasterization part. Per-pixel effects such as fog effects, alpha blending, and stencil test are also implemented in the proposed 3-D graphics IP. The rasterization architecture is designed for reducing external memory accesses to achieve the peak performance. The chip is fabricated using 0.13/spl mu/m CMOS technology and its area is 7.1/spl times/7.0mm/sup 2/.     

An IEEE 802.11 and 802.16 WLAN Wireless Transmitter Baseband Architecture with a 1.2-V, 600-MS/s, 2.4-mW DAC

In this paper, we propose a transmitter baseband architecture for the present and up-coming WLAN applications (IEEE 802.11a/g, 802.11n, 802.16), based on a 600-MS/s current-steering DAC with a passive output load, to perform the baseband signal processing, avoiding the use of any active analog reconstruction filter. The DAC, fabricated in a 0.13-μm CMOS technology, consumes 2.4 mW from a 1.2-V single supply voltage. The DAC exhibits 68 dB of SFDR at full-scale for a 12-MHz input signal frequency and 9.7 bits of full-scale dynamic range in the bandwith from dc to 10 MHz.     

An evaluation of exact and approximate 3-D reconstruction algorithms for a high-resolution, small-animal PET scanner

MicroPET is a low-cost, high-resolution positron emission tomography (PET) scanner designed for imaging small animals. MicroPET operates exclusively without septa, acquiring fully three-dimensional (3-D) data sets. The performance of the projection-reprojection (3DRP), variable axial rebinning (VARB), single slice rebinning (SSRB), and Fourier rebinning (FORE) methods for reconstruction of microPET data were evaluated. The algorithms were compared with respect to resolution, noise variance, and reconstruction time. Results suggested that the 3DRP algorithm gives the best combination of resolution and noise performance in 9 min of reconstruction time on a Sun UltraSparc I workstation. The FORE algorithm provided the most acceptable accelerated method of reconstruction, giving similar resolution performance with a 10%-20% degradation in noise variance in under 2 min. Significant degradation in the axial resolution was measured with the VARB and SSRB methods, offsetting the decrease in reconstruction time achieved with those methods. In-plane angular mashing of the 3-D data before reconstruction led to a 50% reduction in reconstruction time but also introduced unacceptable tangential blurring artifacts. This thorough evaluation of analytical 3-D reconstruction techniques allowed for optimal selection of a reconstruction method for the diverse range of microPET applications.