High-Voltage Self-Aligned p-Channel DMOS-IGBTs in 4H-SiC

SiC power MOSFETs designed for blocking voltages of 10 kV and higher face the problem of high drift layer resistance that gives rise to a high internal power dissipation in the ON -state. For this reason, the ON-state current density must be severely restricted to keep the power dissipation below the package limit. We have designed, optimized, and fabricated high-voltage SiC p-channel doubly-implanted metal-oxide-semiconductor insulated gate bipolar transistors (IGBTs) on 20-kV blocking layers for use as the next generation of power switches. These IGBTs exhibit significant conductivity modulation in the drift layer, which reduces the ON-state resistance. Assuming a 300 W/cm² power package limit, the maximum currents of the experimental IGBTs are 1.2x and 2.1x higher than the theoretical maximum current of a 20-kV MOSFET at room temperature and 177 degC, respectively.     

High-Voltage n-Channel IGBTs on Free-Standing 4H-SiC Epilayers

In this paper, we describe a process for fabricating high-voltage n-channel double-diffused metal–oxide–semiconductor insulated gate bipolar transistors (IGBTs) on free-standing 4H silicon carbide (SiC) epilayers. In this process, all critical layers are epitaxially grown in a continuous sequence. The substrate is then removed, and device fabrication takes place on the carbon face of a free-standing epilayer having a total thickness of about 180 $muhbox{m}$. For a drift layer with doping and thickness values capable of blocking 20 kV, the n-channel IGBT carries 27.3- $hbox{A/cm}^{2}$ current at a power dissipation of 300 $ hbox{W/cm}^{2}$, with a differential on-resistance of 177 $hbox{m}Omegacdot hbox{cm}^{2}$. To our knowledge, this is the first detailed report of device fabrication on free-standing SiC epilayers.      

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

A high-voltage lateral double-diffusion MOSFET (LDMOS) with a charge-balanced surface low on-resistance path (CBSLOP) layer is proposed and experimentally demonstrated using a modified CMOS process. The CBSLOP layer can not only provide a low on-resistance path in the on-state but also keep the charge balance between the N and P pillars of a surface low on-resistance path in the off-state, which results in improved breakdown voltage (BV). The experimental results show that the CBSLOP-LDMOS with a drift length of 35 $mu hbox{m}$ exhibits a BV of 500 V and specific on-resistance $(R_{{rm on}, {rm sp}}!)$ of 96 $hbox{m}Omega cdot hbox{cm}^{2}$, yielding to a power figure of merit $(BV^{2}!!/ !R_{{rm on}, {rm sp}})$ of 2.6 $hbox{MW}/hbox{cm}^{2}$ . The excellent device performances, coupled with a CMOS-compatible fabrication process, make the proposed CBSLOP-LDMOS a promising candidate for smart power integrated circuit.      

Optimization of on-State and Switching Performances for 15–20-kV 4H-SiC IGBTs

The 4H-SiC p-channel IGBTs designed to block 15 and 20 kV are optimized for minimum loss ( on-state plus switching power) by adjusting the parameters of the $hbox{p}$ JFET region, $ hbox{p}-$ drift layer, and $hbox{p}+$ buffer layer, using 2-D MEDICI simulations. Switching loss exhibits a strong dependence on buffer layer thickness, doping, and lifetime due to their influence on the current tail. In contrast, drift layer lifetime has little effect on the crossover frequency at which the MOSFET and IGBT have equal loss.      

Drift-free 10-kV, 20-A 4H-SiC PiN diodes

As impressive as the advancement in 4H-SiC material quality has been, 4H-SiC PiN diodes continue to suffer from irreversible, forward-voltage instabilities. In this work, we describe PiN diodes designed to block 10 kV and conduct 20 A at less than 4.5 V, which were fabricated on 4H-SiC PiN epitaxial layers that were grown with an innovative epitaxial process that has been developed specifically to suppress V_F drift. The diodes fabricated on epitaxial layers that implemented this new epitaxy process showed excellent V_F stability, with 86% of the diodes drifting less than 0.1 V during forward current stressing at 10 A (50 A/cm²) for 30 min. However, these improvements in V_F drift come with a cost in blocking yield, as the surface morphology and other crystal defects imparted by the epitaxial process resulted in only 1 of 50 diodes reaching the 10-kV blocking specification. Nevertheless, the remarkable progress in V_F drift yield brings us closer to commercialization of high-power 4H-SiC PiN diodes.     

Fabrication of 4H-SiC n-channel IGBTs with ultra high blocking voltage

Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices,n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications.In this paper,backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs.The thickness of a drift layer was 120 μm,which was designed for a blocking voltage of 13 kV.The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V,with a differential specific on-resistance of 140 mΩ·cm2.     

Demonstration of the first 10-kV 4H-SiC Schottky barrier diodes

This letter reports the demonstration of the first 4H-SiC Schottky barrier diode (SBD) blocking over 10 kV based on 115-/spl mu/m n-type epilayers doped to 5.6 /spl times/ 10/sup 14/ cm/sup -3/ through the use of a multistep junction termination extension. The blocking voltage substantially surpasses the former 4H-SiC SBD record of 4.9 kV. A current density of 48 A/cm/sup 2/ is achieved with a forward voltage drop of 6 V. The Schottky barrier height, ideality factor, and electron mobility for this very thick epilayer are reported. The SBD's specific-on resistance is also reported.     

Comparisons of Design and Yield for Large-Area 10-kV 4H-SiC DMOSFETs

Three large-area 10-kV 4H-SiC DMOSFET designs are compared with respect to their design, die area, breakdown yield, and ON-state yield. The largest of these DMOSFETs had 0.62 $hbox{cm}^{2}$ of active area on a 1- $hbox{cm}^{2}$ die, with a 10-kV device producing 40 A at a gate field of 3 MV/cm. Two designs used linear interdigitated fingers, whereas the third design used a square cell layout. The linear interdigitated finger design proved to be more robust, with higher yields than the square cell geometry. It was determined that the square cell design was yield limited due to the impact of wafer bow and total thickness variations on photolithographic accuracy, making the square cell geometry less attractive for large-area 4H-SiC DMOSFETs.      

Performance and Stability of Large-Area 4H-SiC 10-kV Junction Barrier Schottky Rectifiers

The forward and reverse bias dc characteristics, the long-term stability under forward and reverse bias, and the reverse recovery performance of 4H-SiC junction barrier Schottky (JBS) diodes that are capable of blocking in excess of 10 kV with forward conduction of up to 10 A at a forward voltage of less than 3.5 V (at 25 $^{circ}hbox{C}$) are described. The diodes show a positive temperature coefficient of resistance and a stable Schottky barrier height of up to 200 $^{circ}hbox{C}$. The diodes show stable operation under continuous forward current injection at 20 $hbox{A/cm}^{2}$ and under continuous reverse bias of 8 kV at 125 $^{circ}hbox{C}$. When switched from a 10-A forward current to a blocking voltage of 3 kV at a current rate-of-fall of 30 $hbox{A}/muhbox{s}$, the reverse recovery time and the reverse recovery charge are nearly constant at 300 ns and 425 nC, respectively, over the entire temperature range of 25 $^{circ}hbox{C}$–175 $^{circ}hbox{C}$.      

Fabrication and characterization of 11-kV normally off 4H-SiC trenched-and-implanted vertical junction FET

This letter reports the first demonstration of 101 kV trenched-and-implanted normally off 4H-SiC vertical junction field-effect transistor (TI-VJFET) with a 120 /spl mu/m /spl sim/4.9/spl times/10/sup 14/ cm/sup -3/-doped drift layer. Blocking voltages (V/sub B/) of 10 kV to 11 kV have been measured. The best specific on-resistance (R/sub SP/_/sub ON/) normalized to source active area has been determined to be 130 m/spl Omega//spl middot/cm/sup 2/. Three-dimensional computer modeling including current spreading effect shows that the TI-VJFET would have a specific resistance of 168 m/spl Omega//spl middot/cm/sup 2/ if it is scaled up substantially in size.     

Electrical Characteristics of 10-kV 4H-SiC MPS Rectifiers with High Schottky Barrier Height

This paper reports the study of the fabrication and characterization results of 10-kilo-volt (kV) 4H-SiC merged PiN/Schottky rectifiers. A metal contact process was developed to make the Schottky contact on n-type SiC and ohmic contact on p-type SiC at the same time. The diodes with different Schottky contact width were fabricated and characterized for comparison. With the improvement quality of the Schottky contact and the passivation layer, the devices show low leakage current up to 10 kV. The on-state characteristics from room temperature to elevated temperature (423 K) were demonstrated and compared between structures with different Schottky contact width.     

AlGaN/GaN Dual-Channel Lateral Field-Effect Rectifier With Punchthrough Breakdown Immunity and Low On-Resistance

We propose an AlGaN/GaN dual-channel lateral field-effect rectifier (DCL-FER) with improved balance between the reverse breakdown voltage (BV) and on-resistance. Instead of utilizing a long single enhancement-mode (E-mode) Schottky-controlled channel to enhance the punchthrough BV but inevitably sacrifice the on-resistance, the DCL-FER features a dual channel consisting of one E-mode section and one depletion-mode (D-mode) section in series. The D-mode channel provides higher carrier density that facilitates high on-current or low on-resistance while still preventing the E-mode channel from being punched through under high reverse voltage. For rectifiers with the same physical dimensions (a drift region length of 5 ?m and a Schottky-controlled channel length of 2 ?m), the DCL-FER is shown to deliver comparable BV while featuring 53% lower on-resistance.     

一种低功耗4H-SiC IGBT的仿真研究

针对传统沟槽栅4H-SiC IGBT关断时间长且关断能量损耗高的问题,文中利用Silvaco TCAD设计并仿真了一种新型沟槽栅4H-SiC IGBT结构。通过在传统沟槽栅4H-SiC IGBT结构基础上进行改进,在N ⁺缓冲层中引入两组高掺杂浓度P区和N区,提高了N ⁺缓冲层施主浓度,折中了器件正向压降与关断能量损耗。在器件关断过程中,N ⁺缓冲层中处于反向偏置状态的PN结对N ^-漂移区中电场分布起到优化作用,加速了N ^-漂移区中电子抽取,在缩短器件关断时间和降低关断能量损耗的同时提升了击穿电压。Silvaco TCAD仿真结果显示,新型沟槽栅4H-SiC IGBT击穿电压为16 kV,在15 kV的耐压设计指标下,关断能量损耗低至4.63 mJ,相比传统结构降低了40.41%。     

Bipolar Conduction Impact on Electrical Characteristics and Reliability of 1.2- and 3.5-kV 4H-SiC JBS Diodes

4H-SiC Junction Barrier Schottky (JBS) diodes (1.2 and 3.5 kV) have been processed using the same technology with two different layouts. From 4 A and for the whole temperature range, the 3.5-kV diodes exhibit a bipolar conduction independent of the layout. However, the behavior of the 1.2-kV diodes depends on the design. At 500 V–300 $^{circ}hbox{C}$, the leakage current is only 100 nA and 10 $muhbox{A}$ for the 3.5- and 1.2-kV diodes, respectively. The switch-off performances show a reverse peak current of only 50% of the nominal current at 300 $^{circ}hbox{C}$ for all JBS diodes. The JBS diodes have a surge current capability of around 80 A, two times higher than the Schottky diodes. DC electrical stresses are performed during 50 h, and all the 1.2-kV diodes exhibit no bipolar degradation. Nevertheless, some slight bipolar degradation is observed in 3.5-kV JBS diodes. Electroluminescence measurements exhibit the expansion of stacking faults in 3.5-kV diodes unlike in 1.2-kV diodes.      

Remarkable Reduction of On-Resistance by Ion Implantation in GaN/AlGaN/GaN HEMTs With Low Gate Leakage Current

We demonstrate Si ion-implanted GaN/AlGaN/GaN high-electron mobility transistors with extremely low gate leakage current and low source resistance without any recess etching process. The source/drain (S/D) regions were formed using Si ion implantation into undoped GaN/AlGaN/GaN on sapphire substrate. Using ion implantation into S/D regions with an energy of 80 keV, the performances were significantly improved. On-resistance decreased from 26.2 to 4.3 Omega^ldrmm. Saturation drain current and maximum transconductance increased from 284 to 723 mA/mm and from 48 to 147 mS/mm.     

Ultraviolet Single Photon Detection With Geiger-Mode 4H-SiC Avalanche Photodiodes

We report 4H-SiC avalanche photodiodes operated in Geiger mode for single photon detection at 265 nm. At room temperature, the single photon detection efficiency is 14% with a dark count probability of 1.7 x 10^-4. Since the external quantum efficiency is 21% at 265 nm, it follows that 65% of the absorbed photons are counted as avalanche events. The jitter of the photodiodes is also characterized.     

Implantation-Free 4H-SiC Bipolar Junction Transistors With Double Base Epilayers

This letter reports the first 4H-SiC power bipolar junction transistor (BJT) with double base epilayers which is completely free of ion implantation and hence of implantation-induced crystal damages and high-temperature activation annealing-induced surface roughness. Based on this novel design and implantation-free process, a 4H-SiC BJT was fabricated to reach an open base collector-to-emitter blocking voltage of over 1300 V, with a common-emitter current gain up to 31. Improvements on reliability have also been observed, including less forward voltage drift (< 2%) and no significant degradation on current gain in the active region.     

High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension

Implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about 80% of the theoretical value) were fabricated, measured, and analyzed by device simulation and optical imaging measurements at breakdown. The key step in achieving a high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to reach an optimum dopant dose of $sim!! hbox{1.2}times hbox{10}^{13} hbox{cm}^{-2}$ in the junction termination extension (JTE). Electroluminescence revealed a localized avalanche breakdown that is in good agreement with device simulation. A comparison of diodes with single- and double-zone etched JTEs shows a higher breakdown voltage and a less sensitivity to varying processing conditions for diodes with a two-zone JTE.      

4H-SiC PIN Recessed-Window Avalanche Photodiode With High Quantum Efficiency

We report a 4H-SiC PIN recessed-window avalanche photodiode with a peak responsitivity of 136 mA/W (external quantum efficiency $= 60$%) at $lambda = {262}$ nm, corresponding to more than a 50% increase in external quantum efficiency compared to nonrecessed structures. The dark current was 90 pA at a photocurrent gain of 1000. Avalanche gains of over $10 ^{6}$, $k sim 0.1$, and a spatially uniform response were achieved.      

Design, fabrication, and characterization of low forward drop, low leakage, 1-kV 4H-SiC JBS rectifiers

The 1-kV 4H-SiC planar junction barrier Schottky (JBS) rectifiers were designed, fabricated, and characterized. Different p+ implantation dosages and activation anneal methods were used to determine an optimum baseline process. Using the optimized process, the forward drop of our JBS rectifiers is <1.5 V while the reverse leakage current density is <1/spl times/10/sup -5/ A/cm/sup -2/. Blocking voltage>1 kV was achieved using a single-zone junction termination extension termination. It was shown experimentally that 4-/spl mu/m p-type implantation window spacing gives an optimum tradeoff between forward drop voltage and leakage current density for these rectifiers, yielding a specific on-resistance of 3 m/spl Omega//spl middot/cm/sup 2/.