10-Gb/s strained MQW DFB-LD transmitter module and superlattice APDreceiver module using GaAs MESFET IC's

This paper describes the design and performance of a 10-Gb/s laser diode (LD) transmitter and avalanche photodiode (APD) receiver, both of which are based on GaAs MESFET IC's. The LD transmitter consists of a strained MQW distributed-feedback LD and one chip LD driver IC. The module output power is +4.6 dBm at 10 Gb/s. The APD receiver consists of an InGaAsP/InAl/As superlattice-APD and an IC-preamplifier with the 10-Gb/s receiver sensitivity of -27.4 dBm. As for the LD transmitter, we discuss the optimum impedance-matching design from the viewpoint of high-speed interconnection between LD and driver IC's. As for the APD receiver, the key issue is input impedance design of preamplifier IC, considering noise and bandwidth characteristics. Total performance of the transmitter and receiver is verified by a 10-Gb/s transmission experiment and a penalty-free 10-Gb/s fiber-optic link over 80 km of conventional single-mode fiber is successfully achieved     

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS

This paper presents the first fully integrated SONET OC-192 transmitter and receiver fabricated in a standard 0.18-/spl mu/m CMOS process. The transmitter consists of an input data register, 16-b-wide first-in-first-out (FIFO) circuit, clock multiplier unit (CMU), and 16:1 multiplexer to give a 10-Gb/s serial output. The receiver integrates an input amplifier for 10-Gb/s data, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. An on-chip LC-type voltage-controlled oscillator (VCO) is employed by both the transmitter and receiver. The chipset operates at multiple data rates (9.95-10.71 Gb/s) with functionality compatible with the multisource agreement (MSA) for 10-Gb transponders. Both chips demonstrate SONET-compliant jitter characteristics. The transmitter 10.66-GHz output clock jitter is 0.065 UI/sub pp/ (unit interval, peak-to-peak) over a 50-kHz-80-MHz bandwidth. The receiver jitter tolerance is more than 0.4 UI/sub pp/ at high frequencies (4-80 MHz). A high level of integration and low-power consumption is achieved by using a standard CMOS process. The transmitter and receiver dissipate a total power of 1.32 W at 1.8 V and are packaged in a plastic ball grid array with a footprint of 11/spl times/11 mm/sup 2/.     

3.5-Gb/s×4-ch Si bipolar LSI's for optical interconnections

The 3.5-Gb/s, 4-ch transmitter and receiver LSI's described here include a 5-to-1 multiplexer, a 1-to-5 demultiplexer, and analog PLL circuits that can generate high-speed clock (3.5 GHz) and retimed data. The chips make it possible to connect twenty pairs of 700-Mb/s electrical ports (14-Gb/s throughput) without any external elements even for the PLL. Both the transmitter and receiver LSI are 4.5-mm-square and are fabricated by a 40-GHz 0.5-μm Si bipolar process. The transmitter LSI dissipates 2.5 W, and the receiver LSI dissipates 3.6 W. Both have -4.5- and -2-V supply voltages     

Applications of 40-Gb/s Chirp-Managed Laser in Access and Metro Networks

We investigate 40-Gb/s cost-efficient transmitter for access and metro networks. This 40-Gb/s transmitter comprises a standard directly modulated distributed-feedback (DFB) laser and a subsequent optical filter. Large dispersion tolerance of this transmitter is realized by chirp control through the phase correlation between adjacent bits for the destructive interference in order to erase the power of “0” bits while enhancing the extinction ratio. The chirp model of the DFB laser and the optimum parameters of the optical filter have been numerically analyzed. The chirp-managed 42.8-Gb/s transmission over 20-km standard single mode fiber (SSMF or SMF-28) without dispersion compensation and a centralized lightwave WDM-PON system are experimentally demonstrated. We have also realized the transmission over 100-m graded index plastic optical fiber (GI-POF). Moreover, the application in the metro network over 240-km SSMF or SMF-28 has also been investigated in this paper.      

A 12-Gb/s HDMI 2.1 quarter-rate transmitter in 28-nm bulk CMOS process

A four-lane 12-Gb/s per lane high-definition multimedia interface (HDMI) 2.1 transmitter is developed in 28-nm bulk CMOS process. To relieve the burden of the generation and distribution of clock, quarter-rate architecture is employed where the duty-cycle and phase spacing errors of multi-phase clock are automatically corrected by analog–digital converter based digital logic. The output driver terminated with 3.3-V supply is implemented only with 1.8- and 1.0-V transistors which are protected from over-voltage stress by double-cascoding with adaptive bias generation. The 4-lane HDMI 2.1 transmitter consumes 12.0-mW/lane at 12-Gb/s and occupies 0.12-mm² active area.     

A 20-Gb/s 0.13-/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

A 20-Gb/s transmitter is implemented in 0.13-/spl mu/m CMOS technology. An on-die 10-GHz LC oscillator phase-locked loop (PLL) creates two sinusoidal 10-GHz complementary clock phases as well as eight 2.5-GHz interleaved feedback divider clock phases. After a 2/sup 20/-1 pseudorandom bit sequence generator (PRBS) creates eight 2.5-Gb/s data streams, the eight 2.5-GHz interleaved clocks 4:1 multiplex the eight 2.5-Gb/s data streams to two 10-Gb/s data streams. 10-GHz analog sample-and-hold circuits retime the two 10-Gb/s data streams to be in phase with the 10-GHz complementary clocks. Two-tap equalization of the 10-Gb/s data streams compensate for bandwidth rolloff of the 10-Gb/s data outputs at the 10-GHz analog latches. A final 20-Gb/s 2:1 output multiplexer, clocked by the complementary 10-GHz clock phases, creates 20-Gb/s data from the two retimed 10-Gb/s data streams. The LC-VCO is integrated with the output multiplexer and analog latches, resonating the load and eliminating the need for clock buffers, reducing power supply induced jitter and static phase mismatch. Power, active die area, and jitter (rms/pk-pk) are 165 mW, 650 /spl mu/m/spl times/350 /spl mu/m, and 2.37 ps/15 ps, respectively.     

A CMOS burst-mode optical transmitter for 1.25-Gb/s ethernet PON applications

This brief presents a CMOS burst-mode optical transmitter suitable for use in 1.25-Gb/s Ethernet passive optical network applications. Based on feedback from the monitoring photodiode, in order to control consecutive burst data the proposed transmitter in this brief uses a reset mechanism, which allows fast responses from the beginning of a high-speed input burst. The chip is fabricated in mixed-mode 0.18-/spl mu/m CMOS technology and measurements are implemented in a chip-on-board configuration using a pig-tailed type Fabry-Perot laser. Under burst-mode operation of 1.25-Gb/s pseudorandom binary sequences, measurements show about 1-dBm averaged transmitted optical power with an over 12-dB extinction ratio over a wide temperature range.     

Performance Comparison of Duobinary Formats for 40-Gb/s and Mixed 10/40-Gb/s Long-Haul WDM Transmission on SSMF and LEAF Fibers

Duobinary formats are today considered as being one of the most promising cost-effective solutions for the deployment of 40-Gb/s technology on existing 10-Gb/s WDM long-haul transmission infrastructures. Various methods for generating duobinary formats have been developed in the past few years but to our knowledge their respective performances for 40-Gb/s WDM transmission have never been really compared. In this paper, we made an extensive numerical evaluation of the robustness of these different types of duobinary transmitter to accumulation of ASE noise, chromatic dispersion, PMD but also to single-channel and WDM 40-Gb/s transmission impairments on standard single-mode fiber. A numerical evaluation of the ability of duobinary format for mixed 10/40-Gb/s WDM long-haul transmission with 50-GHz channel spacing is also led, on both standard single-mode and LEAF fibers, and compared to DQPSK format. In order to clearly identify the limiting transmission effects on each of these two fiber types, the assessment of the performance of a 50-GHz spaced WDM 40-Gb/s long-haul transmission using either duobinary or DQPSK channels only is implemented at last.      

Compact and 10-Gb/s $times$ 12-Channel Optical Transmitter for Optical Interconnection With High Heat-Dissipation Capability Using Alumina Substrates

A compact 10-Gb/s $times$ 12-channel optical transmitter was developed for very short-reach optical interconnections. The 10-Gb/s/ch operations were achieved without employing the heat pipes or heat sinks typically required to keep vertical-cavity surface-emitting lasers at a low temperature under 85 $^{circ}$C. Alumina ceramic substrates with high heat dissipation capability are incorporated in order to maintain the low temperature operation. The optical transmitter is designed to be as compact as a standard mechanically transferable (MT) optical connector. To enhance usability, the transmitter can be directly connected with the MT-type optical connector with guide pins assembled in the alumina substrate. The compactness and usability of the optical module is effective in intrabox and interbox optical interconnections.      

Fully electrical 40-Gb/s TDM system prototype based on InP HEMTdigital IC technologies

This paper presents a fully electrical 40-Gb/s time-division-multiplexing (TDM) system prototype transmitter and receiver. The input and output interface of the prototype are four-channel 10-Gb/s signals. The prototype can be mounted on a 300-mm-height rack and offers stable 40-Gb/s operation with a single power supply voltage. InP high-electron mobility transistor (HEMT) digital IC's perform 40-Gb/s multiplexing/demultiplexing and regeneration. In the receiver prototype, unitraveling-carrier photodiode (UTC-PD) generates 1 V_pp output and directly drives the InP HEMT decision circuit (DEC) without any need for an electronic amplifier. A clock recovery circuit recovers a 40-GHz clock with jitter of 220 fs_pp from a 40-Gb/s nonreturn-to-zero (NRZ) optical input. The tolerable dispersion range of the prototype within a 1-dB penalty from the receiver sensitivity at zero-dispersion is as wide as 95 ps/nm, and the clock phase margin is wider than 70° over almost all the tolerable dispersion range. A 100-km-long transmission experiment was performed using the prototype. A high receiver sensitivity [-25.1 dBm for NRZ (2⁷-1) pseudorandom binary sequence (PRBS)] was obtained after the transmission. The 40-Gb/s regeneration of the InP DEC suppressed the deviation in sensitivity among output channels to only 0.3 dB. In addition, four-channel 40-Gb/s wavelength-division-multiplexing (WDM) transmission was successfully performed     

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial datacommunications

A 2.125-Gb/s transmitter meeting the specifications of the emerging ANSI Fiber Channel standard has been developed using BiCMOS technology. This transmitter features (1) a fully bipolar 10:1 multiplexer (MUX) and a 2.125-GHz retimer for high-accuracy transmission of data, (2) an emitter-coupled logic (ECL) CMOS analog phase-locked loop, (3) pure ECL-level output for direct connection to the currently available optical modules, and (4) BiCMOS process technology that includes 0.25-μm CMOS devices and 20-GHz bipolar devices. The LSI serializes 32-bit-wide, 53.125-Mb/s data into 2.125-Gb/s data through a CMOS 8B10B encoder. The chip area is 3×2 mm², and the power dissipation is 860 mW     

Characterization of an optical frequency-shift-keying transmitter based on carrier-suppressed phase modulation

We experimentally characterize an optical frequency-shift-keying transmitter based on optical carrier-suppressed phase modulation. Only one laser source is needed to generate an optical FSK signal. The demonstration of 10-Gb/s FSK signal generation and 50-km transmission verified the improved performance of the proposed transmitter, compared with the previous two-laser schemes. To further reduce the complexity of the transmitter, the phase modulator is omitted and a single MZM modulator is used for both optical carrier-suppression (OCS) and phase modulation. This simplified structure is verified by simulation, implying the feasibility that a FSK transmitter can be constructed with only one laser source and one modulator.     

Performance and scalability of a single-stage SOA switch for 10/spl times/10 gb/s wavelength striped packet routing

This letter reports successful routing of 10/spl times/10 Gb/s multiwavelength optical packets using single-stage semiconductor optical amplifier switches. Performance under switching is assessed with up to ten wavelengths with particular emphasis being placed on the limit of operation. A 15.2-dB power margin is demonstrated which allows at least eight port connections with a commercially available 0-dBm output 10-Gb/s transmitter and -21-dBm sensitivity receiver.     

An analog front-end chip set employing an electro-optical mixeddesign on SPICE for 5-Gb/s/ch parallel optical interconnection

A chip set composed of a laser-diode driver (LDD) and an optical receiver (RCV), which incorporates a full 2D (reshape, regenerate) function, has been developed by using silicon bipolar technology for a four-channel 5-Gb/s parallel optical transceiver. An electro-optical mixed design on SPICE of the LDD and the LD is accomplished by describing the rate equations of the LD as an electrical circuit. This design accommodates easy connectivity of the LDD chip to the LD in the optical transmitter module without the need for adjustment of the optical waveform. A pseudobalanced transimpedance amplifier (TIA) and feedforward automatic decision threshold control (ATC) in the RCV minimize the number of off-chip bypass capacitors, eliminate the need for any off-chip coupling capacitors, and keep crosstalk less than -50 dB and low cutoff frequency less than 80 kHz. A prototype parallel optical transmitter module and a prototype receiver module, based on the chip set, demonstrated asynchronous four-channel 5-Gb/s operation. The chip set has a throughput of 20 Gb/s with a power dissipation of 1.3 W at a 3.3-V supply     

Extended Transmission Reach Using Optical Filtering of Frequency-Modulated Widely Tunable SSG-DBR Laser

We propose a novel transmitter consisting of a frequency-modulated widely tunable super-structure-grating distributed Bragg reflector (SSG-DBR) laser and an optical filter. The SSG-DBR laser acts as a frequency modulating light source with a constant output power by modulating the reverse bias voltage in the phase control (PC) region. By optically filtering the output light from the frequency-modulated laser, we have demonstrated 60- and 180-km transmissions for 20- and 10-Gb/s nonreturn-to-zero (NRZ) signals, respectively. The power penalty was 2.2 dB after the 180-km transmission of a 10-Gb/s NRZ signal as determined by bit-error-rate measurements. Furthermore, an extended transmission reach was achieved with a wide tuning range without controlling the bias and modulating voltages in the PC region.     

Performance analysis of single-MZM APRZ transmitters

In this paper, an efficient single Mach-Zender modulator (MZM) implementation of alternate-phase return to zero (APRZ), which combines carrier-suppressed return to zero (CSRZ)'s ease of implementation with APRZ's nonlinear tolerance, is analyzed. In particular, the first numerical study of 67%-duty-cycle single-MZM APRZ over a 40-Gb/s 5 /spl times/ 100-km link, in terms of nonlinear, dispersion, and filtering tolerance, comparing it with 33% RZ, 33% APRZ, and standard 67% CSRZ, is presented. The results show that APRZ with phase shift close to /spl pi//2 is the optimum choice, independent of specific transmitter implementation. A new mechanism is also discovered, based on the interference of ghost pulses with the original pulse train, which improves the nonlinear tolerance of CSRZ in a 40-Gb/s transmission.     

Parallel-optical interconnects >100 gb/s

A parallel-optical interconnect with 12 channels operating at 8.5 Gb/s giving an aggregate data rate of 102 Gb/s is demonstrated, to the authors' knowledge, for the first time. The paper describes and demonstrates 13 /spl times/ 16-mm cross-section 12-channel parallel-optic transmitter and receiver modules with each channel operating at a data rate of 8.5-10 Gb/s. This was achieved using bottom-emitting 990-nm vertical-cavity surface-emitting lasers and bottom-illuminated InGaAs-InP photodetectors flip-chip bonded directly to 12-channel transmitter and receiver integrated circuits, respectively. In addition, 102-Gb/s link results are demonstrated over 100 m of 50-/spl mu/m-core standard multimode ribbon fiber. A bit-error ratio of <10/sup -13/ was measured on a single channel after transmission through 100 m of multimode fiber at a data rate of 8.5 Gb/s with all 12 channels operating simultaneously.     

60-GHz Photonic Millimeter-Wave Link for Short- to Medium-Range Wireless Transmission Up to 12.5 Gb/s

In this paper, a 60-GHz photonic millimeter-wave link system for short- to medium-range broadband wireless data transmission is investigated. The system employs advanced mm-wave photonic components and radio-over-fiber (RoF) techniques for the generation of a DSB-SC optical mm-wave carrier and its subsequent on-off-keying modulation and transmission. For short-range applications, we have constructed a compact wireless RoF transmitter consisting of a high-frequency photodiode and a mm-wave antenna only. This system achieved error-free ($hbox {BER}=10^{-9}$, $2^{31}-1$ PRBS, NRZ) in-door transmission of 12.5-Gb/s signals over wireless distances up to 3.1 m with a receiver sensitivity as low as $-$ 45.4 dBm . For fixed wireless access (FWA) requiring a bit error rate of $10^{-4}$, the maximum transmission distance for 12.5 Gb/s is increased up to 5.8 m. For medium-range broadband wireless transmission an electrical radio-frequency (RF) amplifier was employed in the RoF transmitter. Here we achieved 7.5-Gb/s error-free transmission in out-door line-of-sight experiments over wireless distances of up to 36 m. Based upon the experimental results, we expect that the maximum wireless distance the system could accommodate for 12.5 Gb/s is in the kilometer range when using high-gain antennas and an RF transmitter amplifier with a sufficient bandwidth.      

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS,MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-μm CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160×114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-μm CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-Ω strip lines, high-speed signal lines, and 33 power supply layers formed using 50-μm thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80×120×20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection