声表面波器件金属膜自动化剥离技术

介绍了声表面波器件金属膜剥离工艺及自动化设备,包括设备用途、功能和结构组成,能完成厚度在0.20～1.00 mm具有基准边的100～150 mm标准圆片金属膜剥离、冲洗和甩干工艺。与传统的槽式批处理剥离清洗技术相比,可以提高产品成品率,避免交叉污染,确保器件规格(线条尺寸)、性能、可靠性等指标不会因剥离工艺(Lift off process)影响而劣化。     

芯片背金属剥离分析

封装制程中发生金属层剥离对产品可靠性产生致命伤害。背金属制程污染是产生剥离的主要原因,封装制程使用的材料和工艺对金属剥离的程度有影响。EDX电子显微镜分析有助于确认金属剥离界面的物质元素,通过比对背面金属设计可以确定剥离是在金属镀膜过程还是封装过程中产生。蒸金过程提高清洗质量和防止化剂交叉污染,封装过程降低胶带粘性、使用胶木/集束顶针、降低热烘温度和时间、降低顶出高度和速度等可减少背面金属膜剥离。     

一种新的基于水蒸气和水混合流体去胶方法

随着半导体器件尺寸越来越小,光刻胶的剥离,尤其是对硬烘后和离子注入后的光刻胶剥离,被认为是现代半导体器件制造过程中最具挑战的工艺之一。本文提出了一种新的湿法去胶技术从而可以替代现有的湿法剥离工艺和等离子灰化工艺。并针对固化后的光刻胶以及金膜和铬膜,进行了相关实验。然后给出了光刻胶的剥离图片,并分析和讨论了该过程的机理。结果表明,利用水蒸气和水的混合流体射流清洗技术可以很容易去除固化后的光刻胶和金属膜。     

功率器件封装中铝引线焊点剥离失效机制研究

比较回流焊前后两组器件样品的电学测量结果,并结合样品的失效分析,发现引线框架氧化也是导致焊点剥离失效的一个重要因素,而且回流焊工艺下的热机械效应,会加速原先潜在的焊点剥离失效的发生.样品的连接性测试发现,在低峰值交流测试电压下显示开路,而高峰值测试电压下显示正常,可以将其归结为典型的焊点剥离失效的测试现象.发现引线键合前的等离子清洗可以减少焊点剥离失效,并可使焊点的剪切强度提高25%.     

准平面型InSb光伏列阵红外探测器

在台式光敏面基础上,采用SiO_2介质掩蔽,金属膜延伸电极和衬底区超声引焊电极引线,研制成InSb光伏型列阵的准平面型器件。由本工艺制备的器件具有无串音、结阻抗高、反向耐压高、稳定性好等良好性能。     

金属剥离与衬底腐蚀等平面自对准OHR技术研究

开发了一套OHR(OverhangResist)技术。在原来剥离工艺的基础上,增加苯处理和高温烘烤工艺,使光刻胶掩膜既保持有利于剥离的形状,腐蚀时又不发生钻蚀,完成自对准腐蚀与等平面的金属剥离。这一技术可以广泛地应用于MEMS和集成电路加工工艺中,使器件工艺简化,降低成本,提高质量。     

利用键合方法转移薄膜材料

阐述了利用键合方法转移薄膜材料的技术及其应用。最人竞争力的转移固体薄膜技术主要有键合加选择性腐蚀工艺和注氢智能剥离工艺，这种技术解决了外延生长难以解决的晶格失配问题，为改善器件结构及性能提供了巨大的潜力。     

等离子清洗工艺对PBGA组装可靠性的影响

文章主要论述了PBGA组装的等离子清洗评定,包括抗界面剥离。研讨了通过射频和微波能量施加功率的两种不同的等离子体系。通过测量表面接触角获得最佳的等离子清洗工艺参数通过扫描电子显微镜、抗拉及剪切力试验来鉴定等离子清洗结果,试验样品为27 mm×27mm的292个焊球的PBGA。陈述了密封剥离试验、芯片和密封剂拉力试验、焊线拉力试验和C-模式SAM(C-SAM)检查的结果,证明了最佳的等离子清洗工艺会增强PBGA封装的定性等级,并提高工艺效率和生产率。     

衬底剥离的量子阱红外探测器研究

对用MBE生长的GaAs/A lGaAs量子阱材料进行了衬底剥离,在此基础上制备了单元器件并测量了器件的黑体响应率以及光电流响应.实验解决了衬底剥离及器件制备中的工艺问题,研究了衬底剥离对材料及器件性能的影响以及用这种方法制备器件的可行性.结果表明选择腐蚀法是一种有效的衬底剥离方法,用这种方法得到的多量子阱薄膜材料仍具有较好的红外探测性能,为进一步实验提供了依据.     

带胶剥离工艺粘附性实验研究

带胶剥离是微电子工艺的常见工艺步骤.文章通过对带胶剥离的样品进行退火实验,研究了电极蒸发金属和不同基底的粘附特性.实验表明,带胶剥离工艺制备的电极,其金属与衬底的粘附性差,退火过程产生气泡,严重影响了器件的特性.蒸发温度、蒸发室真空度,以及基片表面的清洁度与气泡产生有密切的关系.从这几点入手,提出了相应的改进方法.     

20纳米nMOS器件中应力金属栅结构设计与薄膜工艺优化

对于如今的CMOS集成工艺,应变金属栅是关键的工艺引入应变技术（PIS,process-induced-strain）之一。在本文中,为了在20nm高K金属栅后栅工艺的nMOS器件中得到较高栅应力,我们对金属栅结构和薄膜工艺的优化进行了大量的研究。通过TCAD工具对工艺和器件的仿真,我们研究了先进应变金属栅技术对器件性能的影响。带有不同栅应力（0GPa~-6GPa）的金属栅电极被应用在器件的仿真中,与此同时,其他PIS技术,如e-SiC 和氮化物应力层也被应用于器件中。随着器件尺寸的减小,应变金属栅对器件中沟道载流子输运有巨大的提高作用。此外,一种新型的角栅电极结构被提出,角度与沟道应力的关系被研究。同时,一种新的全应变金属填充栅以及用平板型氧化铪层代替U型氧化铪层,都能够提高应变金属栅的效果。为了在金属栅中得到更大应力的薄膜,我们优化了物理汽相淀积氮化钛的工艺条件。在氮气流量大约6sccm,较高溅射功率和较薄膜厚的情况下我们得到了最大的压应力-6.5GPa。     

微电子工艺技术可靠性

对工艺过程进行评估的目的在于找出存在可靠性缺陷的地方，它是针对技术磨损的机理，通过对专门设计的测试结构进行封装级或圆片级可靠性测试，获取可靠性模型参数和可靠性信息，超大规模集成电路主要的三个的失效机理分别是热载流子注入效应，金属化电迁移效应和氧化层的TDDB击穿，本文对这三种失效机理分别进行了介绍，对各自对应的可靠性模型进行了说明，列举了热载流子汪入效应的寿命评价实例，说明了可靠性评价的重要性，给出了可靠性主人在工艺中的应用流程图。     

Mechanical strength of 300 mm diameter silicon wafers at high temperatures: modeling and simulation

Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.     

A planar gate double beryllium implanted GaAs power MESFET for lowvoltage digital wireless communication application

An ion-implanted planar gate power MESFET for low voltage digital wireless communication system including DCS1800 (digital cellular system at 1800 MHz) and CDMA (code division multiple access) handset applications has been developed. The process for the device developed contains double Be implantation to reduce the surface and substrate defect trapping effects. The MESFET process developed has very little gate recess (less then 200 Å), which greatly improves the uniformity and the yield of the wafer. The 1 μm×20 mm MESFET manufactured using this planar gate technology exhibits an output power of 32.98 dBm and power added efficiency over 53% with gain of 11.2 dB when tested at 1.9 GHz under 3.6 V drain bias voltage and 80 mA quiescent drain current. The pinch off voltage of the 20 mm devices within a wafer is -2.81 V with a standard deviation of 120 mV. The device was also tested at 3.6 V and 1.9 GHz for CDMA application. Under the IS-95 CDMA modulation at 28 dBm output power, the device gain is 10.7 dB and the device has an adjacent channel power rejection (ACPR) of -29.5 dBc at 1.25 MHz offset frequency and -44.9 dBc at 2.25 MHz offset. The test data shows that the double Be implanted devices developed using the planar gate technology have very good linearity and efficiency and can be used for the low voltage DCS1800 and CDMA handset applications     

一种短波电台无人值守值班机系统的设计

本文介绍了一种以MCS－51系列单片机为核心的短波电台无人值守智能值班机系统，用来代替值班人员自动接收电台报文并通过公用电话网及时传达报文信息，文中给出了系统总体设计框图并详细介绍了系统主要功能及工作过程，最后针对设计中用到的关键技术进行了总结。     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

红外加热吸附反应外延系统的温度均匀性研究

为指导全新的吸附反应外延技术ARE(Absorption Reaction Epitaxy, ARE)设备红外热源的设计,分析在真空腔室中红外管阵列的热流分布。通过对灯管阵列灯管数量、灯管间距、灯阵与硅片之间距离等设计参数。采用COMSOL Multiphysics软件进行仿真模拟,研究了以红外为热源的设备腔室及硅片温度场分布情况,实测硅片表面温度及均匀性与仿真基本吻合。结果表明在保证源在硅片表面良好扩散效果的同时,当灯管阵列灯管长度为200 mm,数量为11根,间距10 mm,距离硅片15 mm时硅片表面温度不均匀度达到0.683%,满足红外加热吸附反应外延工艺需求,可为ARE红外热源及腔室设计提供参考。     

采用高压NMP实现全自动去胶技术

LED加工工序中,需要对晶圆表面进行去胶处理。针对LED去胶工序研究了一种去胶方法,并开发出了一种享有专利的晶圆表面金属剥离及光刻胶去除工艺及自动去胶设备,该工艺方法可去除LED表面金属层及光刻胶,并且将人工去胶的三道工艺程序整合到一起。采用该方法的全自动去胶设备,通过实验比对,能够达到良好的LED晶圆去胶良率。结尾列出了利用该方法与目前常见的人工去胶相比的多种优点。     

Ultra large scale static rams

Using a patented defect avoidance technique, high yield production of high density SRAM devices (ULSI SRAMs) can be achieved one process generation ahead of the rest of the industry. Production wafer yields as high as 100% and long-term average yields above 80% are reported on Inova's monolithic, 1.2μ, 320 square mm, one megabit SRAM demonstrating a practical method of achieving wafer scale integration. A yield model is presented and used to determine the optimized architecture and redundancy scheme for Inova's four megabit SRAM and to predict yield as a function of defect density. Achievement of a working 8M-bit experimental device using a 1.2μ process is also reported.     

涂胶显影机的产能设计

涂胶显影机的产能设计是一个重要部分,通过对机台的工艺时间参数、工艺处理周期时间参数、工艺传递周期时间参数等核心参数的设计,有效地配置工艺处理模块的数量及位置、工艺传递晶圆的速度及路线,搭建出目标机台内的工艺模块组成架构,确定出目标机台内的各个机器人技术参数,满足与光刻机联线生产的量产涂胶显影机对产能的技术需求。