A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I _ON/I _OFF ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I _ON/I _OFF (～10⁹). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.     

Quantum ballistic transport in the junctionless nanowire pinch-off field effect transistor

In this work we investigate quantum ballistic transport in ultrasmall junctionless and inversion mode semiconducting nanowire transistors within the framework of the self-consistent Schrödinger-Poisson problem. The quantum transmitting boundary method is used to generate open boundary conditions between the active region and the electron reservoirs. We adopt a subband decomposition approach to make the problem numerically tractable and make a comparison of four different numerical approaches to solve the self-consistent Schrödinger-Poisson problem. Finally we discuss the IV-characteristics for small (r≤5 nm) GaAs nanowire transistors. The novel junctionless pinch-off FET or junctionless nanowire transistor is extensively compared with the gate-all-around (GAA) nanowire MOSFET.     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

The ongoing trend of device dimension miniaturization is attributed to a large extent by the development of several non-conventional device structures among which tunneling field effect transistors (TFETs) have attracted significant research attention due to its inherent characteristics of carrier conduction by built-in tunneling mechanism which in turn mitigates various short channel effects (SCEs). In this work, we have, incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a double gate tunneling field effect transistor (DG TFET), thereby presenting a new device structure, a work function engineered double gate tunneling field effect transistor (WFEDG TFET). We have presented an explicit analytical surface potential modeling of the proposed WFEDG TFET by the solving the 2-D Poisson’s equation. From the surface potential expression, the electric field has been derived which has been utilized to formulate the expression of drain current by performing rigorous integration on the band-to-band tunneling generation rate over the tunneling region. Based on this analytical modeling, an overall performance comparison of our proposed WFEDG TFET with its normal DG TFET counterpart has been presented in this work to establish the superiority of our proposed structure in terms of surface potential and drain current characteristics. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.     

Double gate graphene nanoribbon field effect transistor with electrically induced junctions for source and drain regions

In this paper a novel graphene nanoribbon transistor with electrically induced junction for source and drain regions is proposed. An auxiliary junction is used to form electrically induced source and drain regions beside the main regions. Two parts of same metal are implemented at both sides of the main gate region. These metals which act as side gates are connected to each other to form auxiliary junction. A fixed voltage is applied on this junction during voltage variation on other junctions. Side metals have smaller workfunction than the middle one. Tight-binding Hamiltonian and nonequilibrium Green’s function formalism are used to perform atomic scale electronic transport simulation. Due to the difference in metals workfunction, additional gates create two steps in potential profile. These steps increase horizontal distance between conduction and valance bands at gate to drain/source junction and consequently lower band to band tunneling probability. Current ratio and subthreshold swing improved at different channel lengths. Furthermore, device reliability is improved where electric field at drain side of the channel is reduced. This means improvement in leakage current, hot electron effect behavior and breakdown voltage. Application to multi-input logic gates shows higher speed and smaller power delay product in comparison with conventional platform.     

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I _D ), ON-state to OFF-state current ratio (I _ON /I _OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G _m R _O ), output conductance (G _D ), transconductance/drain current ratio (G _m /I _D ) and unity gain cut-off frequency (f _T ). The effects of varying the spacer dielectric constant (k _sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W _sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.     

Modeling of metal-ferroelectric-semiconductor field effect transistor subthreshold current

Abstract

A subthreshold current model for metal-ferroelectric-semiconductor field effect transistor (MFSFET) is derived from a new analytical ferroelectric hysteresis model,^1.2 the semiconductor surface model,³ the classical diffusion current model,⁴ as well as the Maxwell equations. The model predicates the shift of MFSFET subthreshold current between forward sweep and backward sweep of gate bias. The simulation results show the effects of coercive voltage, the remanent polarization, the saturation polarization, and the free interface charge between ferroelectric and semiconductor. The external field effect on the saturation polarization (better known as ferroelectric space charge effect) is also modeled. The conventional method to evaluate the interface trapped charge for metal-oxide-semiconductor system is also proposed for MFS system based on the ideal subthreshold current model and its experimental data.     

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson’s equation using “variable separation technique”. The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.     

场效应管器件筛选装置设计

随着场效应管器件在电子设备的应用越来越广泛,而相关的测试和筛选需求也在相应增加,针对目前本实验室在场效应管器件筛选过程中不具备的栅偏、反偏及功率老化等试验能力,在现在实验室具备的筛选试验设备平台上,设计并建立一套场效应管器件的栅偏、反偏及功率老化试验装置,提高实验室的检测能力.对整个设计、试验及结果验证过程做了详细介绍...     

Performance enhancement of recessed silicon channel double gate junctionless field-effect-transistor using TCAD tool

In this paper, we propose an n-type double gate junctionless field-effect-transistor using recessed silicon channel. The recessed silicon channel reduces the channel thickness between the underlap regions, results in lowering the number of charge carriers in the silicon channel, and therefore, diminishing the OFF-current in the device. The proposed device shows similar electrical characteristics with improved transconductance, as compared to the conventional double gate junctionless field-effect-transistor. The effect of channel length scaling on the performance have been investigated, and it has been found that the recessed junctionless device shows higher ON-to-OFF current ratio, lower subthreshold swing and better immunity against the short channel effects, namely threshold voltage roll-off and drain-induced-barrier-lowering. For a channel length of 20 nm the OFF-current of the order of 1.20?×?10^–14 A/µm, ON-to-OFF current ratio of the order of 6.01?×?10¹⁰, subthreshold swing of the value of 67 mV/dec, and DIBL of 37.8 mV V^?1 has been achieved with the proposed junctionless device, in comparison of conventional double gate junctionless FET. The performance of proposed device with respect to the variations in depth and length of recessed silicon area, has also been presented as a roadmap for further tuning of its electrical behaviour. Comparatively, steeper DC transfer characteristics and improved rail-to-rail swing in transient behaviour has been reported with the designed complementary metal–oxide–semiconductor inverter, based on recessed double gate junctionless FET. The proposed recessed silicon channel double gate junctionless field-effect-transistor has been simulated using TCAD tool.

     

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.     

Recent advances in insulated gate bipolar transistor technology

Device design of the insulated gate bipolar transistor (IGBT) has been optimized to reduce the distributed transmission-line effect. In addition, cell geometry is chosen to yield high latchup current capability and low forward-voltage drop simultaneously. The vertical structure is optimized to enhance both the turn-off speed and the safe operating area of the IGBTs. The turn-off time of the n-IGBT has been shortened to be as low as 40 ns. The p-channel IGBT latchup current has been improved four to six times over the previously reported results through innovative design and processes. An open-base bipolar transistor model has been implemented to investigate transient IGBT characteristics