A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I _ON/I _OFF ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I _ON/I _OFF (～10⁹). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.     

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I _D ), ON-state to OFF-state current ratio (I _ON /I _OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G _m R _O ), output conductance (G _D ), transconductance/drain current ratio (G _m /I _D ) and unity gain cut-off frequency (f _T ). The effects of varying the spacer dielectric constant (k _sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W _sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.     

3D analytical modeling of surface potential,threshold voltage,and subthreshold swing in dual-material-gate (DMG) SOI FinFETs

Here, we develop a 3D analytical model for potential in a lightly doped dual-material-gate FinFET in the subthreshold region. The model is based on the perimeter-weighted sum of a dual-material double-gate (DMDG) asymmetric MOSFET and a DMDG symmetric MOSFET. The potential model is used to determine the minimum surface potential needed to obtain the threshold voltage \((V_{\mathrm{T}})\) and subthreshold swing (SS) by considering the source barrier changes in the leakiest channel path. The proposed model is capable of reducing the drain-induced barrier lowering (DIBL) as well as the hot carrier effects offered by this device. The impact of control gate ratio and work function difference between the two metal gates on \(V_{\mathrm{T}}\) and SS are also correctly established by the model. All model derivations are validated by comparing the results with technology computer-aided design (TCAD) simulation data.     

A simulation study of short channel effects with a QET model based on Fermi–Dirac statistics and nonparabolicity for high-mobility MOSFETs

In this paper, the quantum confinement and short channel effects of Si, Ge, and \(\hbox {In}_{0.53}\hbox {Ga}_{0.47}\)As n-MOSFETs are evaluated. Both bulk and double-gate structures are simulated using a quantum energy transport model based on Fermi–Dirac statistics. Nonparabolic band effects are further considered. The QET model allows us to simulate carrier transport including quantum confinement and hot carrier effects. The charge control by the gate is reduced in the Ge and \(\hbox {In}_{0.53}\hbox {Ga}_{0.47}\)As bulk n-MOSFETs due to the low effective mass and high permittivity. This charge control reduction induces the degradation of short channel effects. In double-gate structures, different improvements of drain induced barrier lowering (DIBL) and subthreshold slope (SS) are seen. The double-gate structure is effective in the suppression of DIBL for all channel materials. The SS degradation depends on channel materials even in double-gate structure.     

Transport study of gate and channel engineering on the surrounding-gate CNTFETs based on NEGF quantum theory

In this paper, we comprehensively study the effects of gate and channel engineering on the performances of surrounding-gate CNTFETs using a quantum kinetic model, which is based on two-dimensional non-equilibrium Green functions (NEGF) solved self-consistently with Poisson’s equations. The iterative approach between Poisson equation and NEGF has been discussed. For the first time, the influences of double-material-gate and linear doping structures on the CNTFETs have been investigated. The calculated results show that double-material-gate CNTFETs with conventional doping (DMG-CNTFETs) can effectively suppress the drain-induced barrier lowering (DIBL), short-channel effects (SCEs), and achieve better sub-threshold property as compared with single-material-gate CNTFETs with conventional doping (SMG-CNTFETs). Compared with conventional doping, linear doping presents lower leakage current, higher I _on /I _off ratio, and lower sub-threshold swing, which means a better ability of gate controlling. In addition, we present a detailed discussion of the performances of scaling down, and conclude that DMG structure can meet the ITRS’10 requirements better than SMG, especially that the I _on /I _off ratio is two orders of magnitude higher than that of ITRS’10 requirements.     

The effect of ITO and Mo electrodes on the properties and stability of In-Ga-Zn-O thin film transistors

The effect of ITO and Mo electrodes on the electrical properties and stability of In-Ga-Zn-O (IGZO) thin film transistors (TFTs) are investigated. While the field effect mobility values of the devices employing ITO and Mo electrodes are similar, the former exhibit smaller threshold voltage (V_th) and subthreshold swing (SS). It is suggested that the relatively large workfunction of Mo (4.7 eV) compared to that of ITO (4.4?~?4.5 eV) induces a large Schottky barrier at the Mo/IGZO junction, which prohibits the effective injection of electrons from the metal into the IGZO semiconductor. The workfunction of IGZO is usually reported to be approximately 4.5 eV. The device stability of the two types of TFTs under negative bias stress (NBS) and positive bias stress (PBS) is similar, which implies that the degradation of the devices under bias stress is mainly affected by the trapping of carriers at the IGZO/gate insulator interface. In the presence of illumination, the devices using optically transparent ITO electrodes allow the penetration of a more abundant concentration of photons into the IGZO active layer, and thus undergo larger V_th shifts under negative bias illumination stress (NBIS). However, under positive bias illumination stress (PBIS), the TFTs using ITO exhibit smaller positive V_th shifts. The latter phenomenon is suggested to result from the excess photo-induced electrons in the bulk that counter the effect of electron trapping near the IGZO/gate insulator boundary.     

Fabrication of a superconducting flux flow transistor with a serial-channel structure by an AFM lithography method

Atomic force microscopy (AFM) has become an attractive technique to fabricate nano devices since the observing mechanism is different from fabricating one. We have fabricated the superconducting flux flow transistor (SFFT) with a serial-channel structure using the AFM lithography analyzed the modified surface by the AFM image. We investigated the induced voltage in a serial-channel terminals dependence on the gate current by the I–V measurement system. We performed the numerical simulation to get the theoretical characteristics of the SFFT controlled by the gate current via the modified channel. The transresistance was 0.006 Ω for I_d=51 mA at I_g=5 mA. It is very low transresistance in comparison with SFFTs fabricated by the other processes, however our results show that the SFFT with a serial-channel structure is effectively fabricated by an AFM lithography method.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

New nanoscale band-to-band tunneling junctionless GNRFETs: potential high-performance devices for the ultrascaled regime

High-performance sub-10-nm field-effect transistors (FETs) are considered to be a prerequisite for the development of nanoelectronics and modern integrated circuits. Herein, new band-to-band tunneling (BTBT) junctionless (JL) graphene nanoribbon field-effect transistors (GNRFETs) endowed with sub-10-nm gate length are proposed using a quantum transport simulation. The nonequilibrium Green’s function (NEGF) formalism is used in quantum simulations considering the self-consistent electrostatics and the ballistic transport limit. The computational assessment includes the I_DS–V_GS transfer characteristics, the potential and electron density distributions, the current spectrum, the ambipolar behavior, the leakage current, the subthreshold swing, the current ratio, and the scaling capability. It is found that BTBT JL-GNRFETs can provide subthermionic subthreshold swings and moderate current ratios for sub-10-nm gate lengths. Moreover, a new doping profile, based on the use of lateral lightly n-type-doped pockets, is adopted to boost their performance. The numerical results reveal that BTBT JL-GNRFETs with the proposed doping profile can exhibit improved performance in comparison with uniformly doped BTBT JL-GNRFETs. In addition, the role of the length and n-type doping concentration of the pockets in boosting the device performance is also studied and analyzed while considering the scaling capability of such devices, revealing that low doping concentrations and long pocket lengths are useful for performance improvement. The merits of the BTBT JL-GNRFETs based on the proposed nonuniform doping profile, namely sub-10-nm scale, steep subthermionic subthreshold swing, low leakage current, and improved current ratio and ambipolar behavior, make them promising nanodevices for use in modern nanoelectronics and high-performance integrated circuits.

     

Parabolic behavior of solution processed ZnSnO device performances depending on Zn/Sn ratios

Thin film transistors (TFTs) with amorphous zinc tin oxide (ZTO) channel layer were fabricated by a simple and low-cost solution process, prepared by dissolving 0.2 M of zinc acetate dihydrate and tin chloride dihydrate in 20 mL of 2-methoxyethanol. All ZTO thin films showed amorphous phases and no impurities (no carbon and chlorine content) even at process temperature of 350 °C. As the Sn ratio in ZTO films increased, the values of saturated mobility (u_sat) and subthreshold gate swing (SS) exhibited a parabolic behavior in ZTO TFTs, depicting that the μ_sat and SS values were a maximum (3.4 cm²/V.s) and minimum (0.38 V/decade) at Zn/Sn?=?1 ratio. Interestingly, the x-ray absorption and X-ray photoemission spectroscopy revealed the origin of parabolic behavior, indicating not only to improve a charge transport in conduction bands but also to increase the Sn⁴⁺/Sn²⁺ ratio at the peak values (Sn/(Zn?+?Sn)?=?1).     

A new F(ast)-CMS NEGF algorithm for efficient 3D simulations of switching characteristics enhancement in constricted tunnel barrier silicon nanowire MuGFETs

In this paper, we present 3D quantum simulations based on Non-Equilibrium Green’s Function (NEGF) formalism using the Comsol Multiphysics^? software and on the implementation of a new Fast Coupled Mode-Space (FCMS) approach. The FCMS algorithm allows one to simulate transport in nanostructures presenting discontinuities, as the normal Coupled Mode-Space (CMS) algorithm does, but with the speed of a Fast Uncoupled-Mode Space (FUMS) algorithm (a faster algorithm that cannot handle discontinuities). We then use this new algorithm to explore the effect of local constrictions on the performance of nanowire MultiGate Field-Effect Transistors (MuGFETs). We show that cross-section variations in a nanowire result in the formation of energy barriers that can be used to improve the on/off current ratio and switching characteristics of transistors: (1) A small constriction resulting in a barrier of the order of a 0.1 eV can be used as an effective means to improve the subthreshold slope and minimize the on/off current ratio degradation resulting from SD tunneling in ultra scaled transistor, and (2) We also report a new variable barrier transistor (VBT) device concept that is able to achieve sub-kT/q subthreshold slope without using impact ionization or band-to-band tunneling. Intra-band tunneling through constriction barriers is used instead. The device is, therefore, fully symmetrical and can operate at very low supply voltages. A subthreshold slope as low as 56.5 mV/decade is reported at T=300 K. The VBT reported here breaks the 60 mV/dec barrier over more than five decades of subthreshold current, which is the widest current range reported so far.     

On the Electrostatics of Double-Gate and Cylindrical Nanowire MOSFETs

In this work we investigate and compare the electrostatics of fully-depleted double-gate (dg) and cylindrical nanowire (cnw) mosfets accounting for quantum effects and, in doing so, we propose a new approach for the self-consistent solution of the Schrödinger-Poisson equations based on a rigorous time-independent perturbation method. This study leads to the conclusion that the cylindrical geometry is superior to the equivalent double-gate structure both in terms of the current ratio I_on/I_off and the available voltage gain g_m/g_o, indicating that both the subthreshold slope and the drain-induced barrier lowering (dibl) are better controlled by the cnw-mosfet.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

An analytical study of undoped symmetric double gate MOSFET (SDG)

In the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the V_ds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.     

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.     

Analog and RF performance of doping-less tunnel FETs with $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$ source

This paper reports studies of a doping-less tunnel field-effect transistor (TFET) with a \(\hbox {Si}_{0.55} \hbox {Ge}_{0.45}\) source structure aimed at improving the performance of charge-plasma-based doping-less TFETs. The proposed device achieves an improved ON-state current (\(I_{{\mathrm{ON}}} \sim {4.88} \times {10}^{-5}\,{\mathrm{A}}/\upmu {\mathrm{m}}\)), an \(I_\mathrm{ON}/I_\mathrm{OFF}\) ratio of \({6.91} \times {10}^{12}\), an average subthreshold slope (\(\hbox {AV-SS}\)) of \(\sim \) \({64.79}\,{\mathrm{mV/dec}}\), and a point subthreshold slope (SS) of 14.95 mV/dec. This paper compares the analog and radio of frequency (RF) parameters of this device with those of a conventional doping-less TFET (DLTFET), including the transconductance (\(g_{{\mathrm{m}}}\)), transconductance-to-drain-current ratio \((g_\mathrm{m}/I_\mathrm{D})\), output conductance \((g_\mathrm{d})\), intrinsic gain (\(A_{{\mathrm{V}}}\)), early voltage (\(V_{{\mathrm{EA}}}\)), total gate capacitance (\( C_{{\mathrm{gg}}}\)), and unity-gain frequency (\(f_{{\mathrm{T}}}\)). Based on the simulated results, the \(\hbox {Si}_{0.55}\hbox {Ge}_{0.45}\)-source DLTFET is found to offer superior analog as well as RF performance.