Simulation Study of High Performance III-V MOSFETs for Digital Applications

We have studied the performance potential of an 80 nm physical gate length MOSFET with GaAs channel and high-k gate insulator using ensemble Monte Carlo simulations. The results show that a such device could deliver a 100–125% increase in the drive current compared to conventional MOSFETs with analogous channel lengths and device structure. This improvement is much higher than the 20–30% drive current increase in similar devices with strained Si channels on virtual SiGe substrates.     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.     

A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I _ON/I _OFF ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I _ON/I _OFF (～10⁹). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.     

Modelling the Deposition of High-k Dielectric Films by First Principles

Considerable interest is focussed on high-k dielectrics as replacements for the gate oxide in future MOSFETs. Atomic Layer Deposition (ALD) is the method of choice to produce conformal thin films for the gate dielectric, but a deeper understanding of this method is needed for process optimisation. For ALD of alumina, we use first principles density functional (DFT) calculations to describe the surface intermediates and pathways of precursor adsorption/decomposition at the atomic scale, yielding quantitative reaction energetics. This reveals the intrinsic limits on ALD growth rate as a function of OH coverage.     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

An analytical model was developed to calculate the potential distribution for a gate-underlap double-gate tunnel FET. The electrostatic potential of the device was derived using the two-dimensional Poisson’s equation, incorporating the fringing electric field in the gate-underlap surface and employing a conformal mapping method. In addition to analytical potential modeling, the electric field and drain current were evaluated to investigate the device performance. Excellent agreement with technology computer-aided design (TCAD) simulation results was observed. The dependence of the ambipolar current on the spacer oxide dielectric constant, spacer length, channel length, and gate material thickness was examined using the proposed model. The effects of the variation of all of these parameters were well predicted, and the model reveals that use of a low-\(\kappa \) spacer dielectric combined with a high-\(\kappa \) gate dielectric results in the minimal ambipolar current for the device.     

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I _D ), ON-state to OFF-state current ratio (I _ON /I _OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G _m R _O ), output conductance (G _D ), transconductance/drain current ratio (G _m /I _D ) and unity gain cut-off frequency (f _T ). The effects of varying the spacer dielectric constant (k _sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W _sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.     

Analysis of tunneling currents in multilayer black phosphorous and $$\hbox {MoS}_{2}$$ non-volatile flash memory cells

This paper presents a theoretical study of tunneling current density and the leakage current through multi-layer (stacked) trapping layer in the gate dielectric in MOS non-volatile memory devices. Two different 2D materials (\(\hbox {MoS}_{2}\) and black phosphorous) with a combination of high-k dielectric (\(\hbox {HfO}_{2}\)) have been used for the study with differently ordered stacks i.e., as trapping layer and substrate. The material properties of 2D materials like density of states, effective mass and band structure has been evaluated using density functional theory simulations. Using the Maxwell–Garnett effective medium theory we have calculated the effective barrier height, effective bandgap, effective dielectric constant and effective mass of the gate dielectric stacks. By applying WKB approximation in the multi-layer trapping layer we have studied the effect of the direct and Fowler–Nordheim tunneling currents. The leakage current in all the different stack combinations used has also been evaluated. The results obtained have shown to match the required dynamics of a memory device.     

Transport study of gate and channel engineering on the surrounding-gate CNTFETs based on NEGF quantum theory

In this paper, we comprehensively study the effects of gate and channel engineering on the performances of surrounding-gate CNTFETs using a quantum kinetic model, which is based on two-dimensional non-equilibrium Green functions (NEGF) solved self-consistently with Poisson’s equations. The iterative approach between Poisson equation and NEGF has been discussed. For the first time, the influences of double-material-gate and linear doping structures on the CNTFETs have been investigated. The calculated results show that double-material-gate CNTFETs with conventional doping (DMG-CNTFETs) can effectively suppress the drain-induced barrier lowering (DIBL), short-channel effects (SCEs), and achieve better sub-threshold property as compared with single-material-gate CNTFETs with conventional doping (SMG-CNTFETs). Compared with conventional doping, linear doping presents lower leakage current, higher I _on /I _off ratio, and lower sub-threshold swing, which means a better ability of gate controlling. In addition, we present a detailed discussion of the performances of scaling down, and conclude that DMG structure can meet the ITRS’10 requirements better than SMG, especially that the I _on /I _off ratio is two orders of magnitude higher than that of ITRS’10 requirements.     

Modeling gate-all-around Si/SiGe MOSFETs and circuits for digital applications

Apart from excellent electrostatic capability and immunity to short-channel effects, the performance of gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) can be further enhanced by incorporating strain. Owing to the technological importance of strained GAA (S-GAA) NW MOSFETs in modern electronics, we have proposed an analytical model of the threshold voltage and drain current for S-GAA NW MOSFETs taking into account the appreciable contributions of source (S) and drain (D) series resistances in the nanometer regime, along with quantum mechanical effect. We have focused on the elliptical cross section of the device as is necessary to consider the fabrication imperfections which give rise to such cross section, rather than an ideal circular structure. Incorporating S/D series resistance in the model of drain current demands for algorithms based on multi-iterative technique, which has been proposed in this paper for analyzing the impact of strain, NW width, aspect ratio and so on, on the performance of S-GAA NW devices with emphasis on CMOS digital circuits. Based on our proposed methodology, we have also investigated the scope of using high-k dielectric materials and metal gate in S-GAA NW structures.     

On the numerical aspects of deterministic multisubband device simulations for strained double gate PMOSFETs

In this paper numerical aspects of deterministic multisubband device simulations are presented for strained double gate PMOSFETs including magnetotransport. The simulations are based on a self-consistent solution of the multisubband Boltzmann transport equation (BTE), 6×6 k?p Schrödinger equation (SE) and Poisson equation (PE). For accurate and efficient calculation of the subband structure, an efficient discretization of the 2D k-space combined with a monotonic cubic spline interpolation is employed. The multisubband BTE is solved with a deterministic method based on a Fourier expansion of the distribution function. The Fourier series is found to converge rapidly for nanoscale double gate PMOSFETs. A convergence enhancement method for the Gummel type SE-PE-BTE loop by solving the BTE-PE simultaneously is proposed.     

Multiscale simulation of MOS systems based on high-κ oxides

We report on a multiscale simulation approach that includes both macroscopic drift-diffusion current model and quantum tunneling model. The models are solved together in a self-consistent way inside a single simulation package. As an example, we study the subthreshold transfer characteristics of MOS transistors based on high-κ oxides. We compare the high-κ gates based on HfO₂ and ZrO₂ with a SiO₂ gate of the same equivalent thickness and show the effect of the tunneling current on transistor performance.     

Bias and geometry optimization of FinFET for RF stability performance

This paper presents RF stability of FinFET at particular bias and geometry conditions. The article provides guideline for optimizing the FinFET at RF range. The FinFET geometrical parameters such as gate spacer length, height of silicon fin, and thickness of silicon fin along with gate material work function and bias conditions are adjusted to optimize the device for better stability performance at RF range. The critical frequency (f _k ) is obtained for different bias and geometry conditions using numerical simulation. The result shows that the optimized FinFET exhibits good RF stability performance.     

Comparison of Double-Gate MOSFETs and FinFETs with Monte Carlo Simulation

A full-band Monte Carlo simulator has been used to analyze and compare the performance of n-channel double-gate MOSFETs and FinFETs. Size quantization effects were accounted for by using a quantum correction based on Schrödinger equation. FinFETs are a variation of typical double-gate devices with the gate surrounding the channel on three sides. From our simulations, we observed that the quantization effects in double-gate devices are less significant as compared to bulk MOSFETs. The total sheet charge density drops only slightly as the depletion of charge at the interface is counterbalanced by the increased volume inversion effect. We also observed an appreciable drop in average velocity distribution when quantum corrections were applied. For FinFETs, the fin extension lengths on either side of the gate affect the device performance significantly. These underlap regions have low carrier concentration and behave as large resistors. The current drops non-linearly with increasing fin extension lengths.     

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green’s function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-\(\kappa \) materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.     

Investigation of trigate JLT with dual-<Emphasis Type="Italic">k</Emphasis> sidewall spacers for enhanced analog/RF FOMs

This paper shows the potential benefits of using the trigate junctionless transistor (JLT) with dual-k sidewall spacers to enhance analog/radio-frequency (RF) performance at 20-nm gate length. Simulation study shows that the source-side-only dual-k spacer (dual-kS) JLT can improve all analog/RF figures of merit (FOMs) compared with the conventional JLT structure. The dual-kS JLT shows improvement in intrinsic voltage gain (\(A_{V0}\)) by \(\sim \)44.58 %, unity-gain cutoff frequency (\(f_\mathrm{T}\)) by \(\sim \)7.67 %, and maximum oscillation frequency (\(f_\mathrm{MAX}\)) by \(\sim \)6.4 % at drain current \((I_\mathrm{ds}) = 10\,\upmu \hbox {A}/\upmu \hbox {m}\) compared with the conventional JLT structure. To justify the improvement in all analog/RF FOMs, it is also found that the dual-kS structure shows high electron velocity near the source region because of the presence of an additional electric field peak near the source region, resulting in increased electron transport efficiency and hence improved transconductance (\(g_\mathrm{m}\)). Furthermore, the dual-kS JLT shows a reduction in the electric field value near the drain end, thereby improving short-channel effects.     

3D Electrostatics of Carbon Nanotube Field-Effect Transistors

The three dimensional (3D) electrostatics of carbon nanotube field-effect transistors (CNTFETs) is studied by solving the Poisson equation self consistently with equilibrium carrier statistics of CNTFETs. The 3D Poisson equation is solved using the method of moments. We examine how the 3D environment affects the electrostatics of a 30 nm intrinsic CNT under equilibrium conditions. We show that for a CNTFET with a planar gate, the scaling length (the distance by which the source and drain fields penetrate into the channel) is mostly determined by the gate oxide thickness. The contact geometry can also play an important role on the scaling length. A smaller contact results in shorter scaling length and better gate control. We finally show that the top gated geometry offers obvious advantage over the bottom gated geometry in terms of gate electrostatic control.     

Dual material gate junctionless tunnel field effect transistor

This paper proposes a junctionless tunnel field effect transistor (JLTFET) with dual material gate (DMG) structure and the performance was studied on the basis of energy band profile modulation. The two-dimensional simulation was carried out to show the effect of conduction band minima on the abruptness of transition between the ON and OFF states, which results in low subthreshold slope (SS). Appropriate selection of work function for source and drain side gate metal of a double metal gate JLTFET can also significantly reduce the subthreshold slope (SS), OFF state leakage and hence gives improved I _ON/I _OFF.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.