8-GHz CMOS quadrature VCO using transformer-based LC tank

A fully integrated quadrature VCO at 8 GHz is presented. The VCO is implemented using a transformer-based LC tank in 0.18 /spl mu/m CMOS technology, in which two VCOs are coupled to generate I-Q signals. The VCO is realized employing the drain-gate transformer feedback configuration proposed here. This makes use of the quality factor enhancement in the resonator using a transformer and the deep switching-off technique by controlling gate bias. By turning off switching transistors of the differential VCO core deeply, the phase noise performance is improved more than 10 dB. The measured phase noise values are -110 and -117 dBc/HZ at the offset frequencies of 600 kHz and 1 MHz respectively. The tuning range of 250 MHz is achieved with the control voltage from 0 to 1 V. The VCO draws 8 mA in two differential core circuits from 3 V supply. When the bias voltage goes down to 2.5 V, the phase noise decrease only 2 dB compared to that of 3 V bias. The VCO performances are compared with previously reported quadrature Si VCOs in 5/spl sim/12 GHz frequency range.     

A 1.5 V 3.1 GHz–8 GHz CMOS Synthesizer for 9-Band MB-OFDM UWB Transceivers

This paper presents the design of a CMOS synthesizer for dual-conversion zero-IF2 Multi-Band OFDM (MB-OFDM) transceivers covering the first 9 frequency bands from 3.1GHz to 8.0GHz, each with a bandwidth of 528 MHz. A wideband single-sideband mixer with wideband inductive network loading is proposed. Moreover, a modified transformer-coupled quadrature VCO and interconnection-loading-insensitive layout technique are employed. Fabricated in TSMC 0.18-mum CMOS process and operated at 1.5V, the synthesizer measures phase noise of -127.4dBc/Hz at 10MHz offset, integrated phase noise of 4.43deg, sideband suppression of better than -22 dBc, and a switching time of less than 1ns while consuming 59 mA     

全集成低噪声CMOS宽带分数分频频率综合器

设计了一款应用于CMMB数字电视广播接收的全集成低噪声宽带频率综合器。采用三阶ΣΔ调制器小数分频器完成高精度的频率输出,使用仅一个低相位噪声的宽带VCO输出频率范围覆盖900~1 600 MHz,产生的本振信号覆盖UHF的数字电视频段(470~790 MHz)。设计中的频率综合器能在所有的频道下保证环路的稳定以及最小的环路性能偏差。测试结果表明,整个频率综合器的带内相位噪声小于-85 dBc/Hz,并且带外相位噪声在1MHz时均小于-121 dBc/Hz,总的频率综合器锁定时间小于300μs。设计在UMC 0.18μm RFCMOS工艺下实现,芯片面积小于0.6 mm2,在1.8 V电源电压的测试条件下,总功耗小于22 mW。     

一种9.8-mW 1.2-GHz CMOS 低噪声正交输出频率综合器

实现了一种基于标准0.18µm CMOS工艺的应用于北斗导航射频接收机的1.2GHz频率综合器。在频率综合器中采用了一种基于分布式偏置技术实现的低噪声高线性LC压控振荡器和一种基于源极耦合逻辑的高速低开关噪声正交输出二分频器,集成了基于与非触发器结构的高速8/9双模预分频器、无死区效应的延迟可编程的鉴频鉴相器和电流可编程的电荷泵。该频率综合器的输出频率范围从1.05到1.30GHz。当输出频率为1.21GHz 时,在100-kHz和1-MHz的频偏处相位噪声分别为-98.53dBc/Hz和-121.92dBc/Hz。工作电压为1.8V时,不包括输出Buffer的核心电路功耗为9.8mW。北斗射频接收机整体芯片面积为2.41.6 mm2。     

一种用于双波段GPS接收机的低功耗宽带CMOS频率合成器

提出了一种用于双波段GPS接收机的宽带CMOS频率合成器.该GPS接收机芯片已经在标准O.18μm射频CMOS工艺线上流片成功,并通过整体功能测试.其中压控振荡器可调振荡频率的覆盖范围设计为2～3.6GHz,覆盖了L1,L2波段的两倍频的频率点.并留有足够的裕量以确保在工艺角和温度变化较大时能覆盖所需频率.芯片测试结果显示,该频率综合器在L1波段正常工作时的功耗仅为5.6mW,此时的带内相位噪声小于-82dBc/Hz,带外相位噪声在距离3.142G载波1M频偏处约为-112dBc/Hz,这些指标很好地满足了GPS接收芯片的性能要求.     

深空测控系统1 Hz低相噪频率合成技术

针对深空测控系统高精度测量对于信道附加相噪的要求,采用直接数字频率合成（DDS）正交调制方法设计频率综合器。通过巧妙的试验和外推方法,择优选取电压型鉴相器,在锁相环相噪模型的基础上,全面分析各部分相噪的贡献,综合设计环路带宽,有效控制附加相噪,实现低相噪频综器最理想的目标,即环路带内的相噪完全由参考决定,带外的相噪由压控振荡器（VCO）决定,并采用两源互比的方法完成1 Hz极低相位噪声的测试,测试结果为-73 dBc/Hz,与设计结果完全一致。该方法对于测控站极低相噪的设计具有一定参考价值。     

A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SCtuning loop

A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-μm CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (K_VCO) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply     

A 1-V 9.7-mW CMOS Frequency Synthesizer for IEEE 802.11a Transceivers

A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm².     

Noise property of a quadrature balanced VCO

A quadrature balanced voltage controlled oscillator (B-VCO) with current source switching is proposed and analyzed. This letter shows analytically that the switching improves the phase noise. A switched transistor is also used as a coupling transistor to generate quadrature signals without degrading the phase noise. To investigate the effect of quadrature coupling on the phase noise, a single B-VCO and a quadrature B-VCO are implemented with identical components in an 0.18-/spl mu/m CMOS process. Both VCO cores draw about 8.8mA under a low bias voltage of 1.8V. The oscillation frequencies are 10.21GHz and 10.81GHz. The measured phase noises of the single at an offset frequency of 1MHz VCO is -114.83 dBc/Hz while that of the quadrature VCO is -116.67 dBc/Hz. The quadrature B-VCO is superior to the single B-VCO with respect to phase noise and oscillation frequency in the X-band.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

使用三位三阶Δ∑调制器的集成1GHz小数频率合成器

本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μm CMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.     

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.     

基于0.35μm SiGe BiCMOS的2.5GHz低相位噪声LC压控振荡器的设计

介绍了一个基于0.35μm SiGe BiCMOS工艺的2.5GHz低相位噪声LC压控振荡器.文章重新定义了压控振荡器工作区域.分析表明谐振回路的电感值和偏置电流对振荡器的相噪优化有重要的影响.本文同时分析了CMOS和BJT压控振荡器设计思路的不同.本设计中,采用键合线来实现谐振回路中的电感来进一步提高相噪性能.该VCO和其他模块集成在一起实现了一个环路带宽为30kHz的频率综合器.测试结果表明,当中心频率为2.5GHz时,在100kHz和1MHz的频偏处相噪分别为-95dBc/Hz和-116dBc/Hz.工作电压为3V时,VCO核心电路的电流消耗为8mA.据我们所知,这是国内第一个采用SiGe BiCMOS工艺的差分压控振荡器.     

A 6-9 GHz 5-band CMOS synthesizer for MB-OFDM UWB

An ultra-wideband frequency synthesizer is designed to generate carrier frequencies for 5 bands distributed from 6 to 9 GHz with less than 3 ns switching time.It incorporates two phase-locked loops and one single-sideband (SSB) mixer.A 2-to-1 multiplexer with high linearity is proposed.A modified wideband SSB mixer,quadrature VCO, and layout techniques are also employed.The synthesizer is fabricated in a 0.18μm CMOS process and operates at 1.5-1.8 V while consuming 40 mA current.The measured phase noise ...     

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature(I/Q) local oscillating signal.A high-speed 8/9 dual-modulus prescaler(DMP),a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply.The total area of the receiver is 2.4×1.6 mm~2.     

Single-VCO multi-band DTV frequency synthesizer with a divide-by-3 frequency divider for quadrature signal generation

A multi-band frequency synthesizer for In-phase and Quadrature (I/Q) LO signal generation in Digital TV tuners is presented. Using divisor numbers other than powers of 2 (2 ⁿ ) for quadrature generation, reduces the required frequency range of the VCO, hence the number of VCO circuits, in multi-band frequency synthesizers. In the proposed synthesizer, VHF, UHF and L-band frequencies are covered with only one VCO. This is achieved by using a novel divide-by-3 circuit which produces precise I/Q LO signals. The VCO tuning range in this design is 2,400–3,632 MHz which is covered by a 6-bit switched-capacitor bank. A fast adaptive frequency calibration block selects the closest VCO frequency to the target frequency by setting the coarse-tuning code prior to the start of phase lock. A programmable charge pump is used to reduce variations in PLL characteristics over the frequency range. The synthesizer has been fabricated in a 0.18 μm CMOS technology and the die area is 1.7 × 1.6 mm². It consumes 27 mA from a 1.8 V power supply. Measurement results show operation of the proposed divide-by-3 circuit over the entire VCO frequency range. The synthesizer quadrature output phase noise for UHF and VHF bands is <−131dBc/Hz at 1.45 MHz offset.     

U波段小数分频锁相环型频率综合器

使用0.18μm1.8VCMOS工艺实现了U波段小数分频锁相环型频率综合器,除压控振荡器(VCO)的调谐电感和锁相环路的无源滤波器外,其他模块都集成在片内。锁相环采用了带有开关电容阵列(SCA)的LC-VCO实现了宽频范围,使用3阶MASHΔ-Σ调制技术进行噪声整形降低了带内噪声。测试结果表明,频率综合器频率范围达到650～920MHz;波段内偏离中心频率100kHz处的相位噪声为-82dBc/Hz,1MHz处的相位噪声为-121dBc/Hz;最小频率分辨率为15Hz;在1.8V工作电压下,功耗为22mW。     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

An Integrated 5–2.5-GHz Direct-Injection Locked Quadrature LC VCO

This letter presents an integrated direct-injection locked quadrature voltage controlled oscillator (VCO), consisted of a 5-GHz VCO integrated with injection locked LC frequency dividers for low-power quadrature generation. The circuit is implemented using a standard 0.18-mum CMOS process. The differential VCO is a full PMOS Colpitts oscillator, and the frequency divider is performed by adding an injection nMOS between the differential outputs of complementary cross-coupled np-core LC VCO. The measurement results show that at the supply voltage of 1.8-V, the master 5-GHz VCO is tunable from 4.73 to 5.74GHz, and the slave 2.5-GHz VCO is tunable from 2.36 to 2.87GHz. The measured phase noise of master VCO is -118.2dBc/Hz while the locked quadrature output phase noise is -124.4dBc/Hz at 1-MHz offset frequency, which is 6.2dB lower than the master VCO. The core power consumptions are 7.8 and 8.7mW at master and slave VCOs, respectively     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.