A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

A 1-V 9.7-mW CMOS Frequency Synthesizer for IEEE 802.11a Transceivers

A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm².     

采用balun低噪声放大器的5GHz 7.2-dB NF低功耗直接转换接收机前端电路

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm². It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted,and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor.To obtain low l/f noise and high linearity,a current mode passive mixer is preferred and realized.A current mode switching scheme can switch between high and low gain modes,and meanwhile it can not only perform good linearity but save power consumption at low gain mode.The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm~2.It achieves 35 dB conversion gain across 4.9-5.1 GHz,a noise figure of 7.2 dB and an IIP3 of -16.8 dBm,while consuming 28.4 mA from a 1.2 V power supply at high gain mode.Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

A fully integrated 0.18-/spl mu/m CMOS direct conversion receiver front-end with on-chip LO for UMTS

This paper presents a 0.18-/spl mu/m CMOS direct-conversion IC realized for the Universal Mobile Telecommunication System (UMTS). The chip comprises a variable gain low-noise amplifier, quadrature mixers, variable gain amplifiers, and local oscillator generation circuits. The solution is based on very high dynamic range front-end blocks, a low-power superharmonic injection-locking technique for quadrature generation and continuous-time dc offset removal. Measured performances are an overall gain variable between 21 and 47 dB, 5.6 dB noise figure, -2 dBm out-of-band IIP3, -10 dBm in-band IIP3, 44.8-dBm minimum IIP2, and -155-dBc/Hz phase noise at 135 MHz from carrier frequency, while drawing 21 mA from a 1.8-V supply.     

1/f noise characteristics of AlGaAs/GaAs heterojunction bipolartransistor with a noise corner frequency below 1 kHz

To reduce the low-frequency noise, HBTs with a large emitter size of 120×120 μm² are fabricated on abrupt emitter-base junction materials without undoped spacer. The HBTs exhibit an internal noise corner frequency of 100 Hz, which is much lower than about 100 kHz of conventional AlGaAs/GaAs HBTs. From the very low noise HBTs, the existence of resistance fluctuation 1/f noise is clearly verified by the simple comparison of collector current noise spectra with different base terminations. It is found that, at a high emitter-base forward bias, the resistance fluctuation 1/f noise becomes dominant for shorted base-emitter termination, but the internal 1/f noise dominant for open base. Device design rules for low noise small-feature size HBT, including resistance fluctuation, are discussed     

A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquistinput

This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-μm double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm² ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V     

A 250-kHz 94-dB double-sampling /spl Sigma//spl Delta/ modulation A/D converter with a modified noise transfer function

This paper presents a high-order double-sampling single-loop /spl Sigma//spl Delta/ modulation analog-to-digital (A/D) converter. The important problem of noise folding in double-sampling circuits is solved here at the architectural level by placing one of the zeros in the modulator's noise transfer function at half the sampling frequency instead of in the baseband. The resulting modulator is of fifth order but has the baseband performance of a fourth-order modulator. Through the use of an efficient switched-capacitor implementation, the overall circuit uses only four operational amplifiers and hence, its complexity is similar to that of a fourth-order modulator. An experimental 1-bit modulator was designed for an oversampling ratio of 96 and a bandwidth of 250 kHz at a 3.3-V supply in a conservative 0.8-/spl mu/m standard CMOS process. Due to the double-sampling, the sampling frequency is 48 MHz, although the circuits operate at a clock frequency of only 24 MHz. The circuit achieves a dynamic range of 94 dB. The peak signal-to-noise ratio and signal-to-noise-plus-distortion ratio were measured to be 90 and 86 dB, respectively. The power consumption of the complete circuit including clock drivers and output pad drivers was 43 mW. The analog blocks (opamps, comparators, etc.) consume 30 mW of this total.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS

A third-order continuous-time multibit (4 bit) /spl Delta//spl Sigma/ ADC for wireless applications is implemented in a 0.13-/spl mu/m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm/sup 2/.     

A 0.22-mm/sup 2/ 7.25-mW per-channel audio stereo-DAC with 97-dB DR and 39-dB SNR/sub out/

In the stereo audio DAC here presented, the tradeoff between area-power consumption-SNR/sub out/-dynamic range is optimized for the case of a 96-dB audio system. Using a single-opamp switched-capacitor structure for the reconstruction filter, a hybrid FIR/IIR transfer function allows to reject out-of-band noise. This circuit solution strongly reduces area and power consumption. In a 0.13-/spl mu/m CMOS technology, the stereo DAC achieves a 97-dB dynamic range and a 39-dB SNR/sub out/ with a 0.22-mm/sup 2/ area and 7.25-mW power consumption per channel.     

A packaged 1.1-GHz CMOS VCO with phase noise of -126 dBc/Hz at a600-kHz offset

A packaged 1.1-GHz CMOS voltage-controlled oscillator (VCO) with measured phase noise of -92, -112, and -126 dBc/Hz at 10-, 100-, and 600-kHz offsets is demonstrated. According to J. Craninekx et al. (1997), these satisfy the GSM requirements. The extrapolated phase noise at a 3 MHz offset is -140 dBc/Hz. The power consumption is 6.8 and 12.7 mW at V_DD=1.5 and 2.7 V, respectively. The VCO is implemented in a low-cost 0.8-μm foundry CMOS process, which uses p+ substrates with a p-epitaxial layer. Buried channel PMOS transistors are exclusively used for lower 1/f noise. The inductors for the LC tanks are implemented using a series combination of an on-chip spiral inductor, four bond wires, and two package leads to increase Q. This technique requires no extra board space beyond that needed for the additional package leads     

A calibrated direct conversion front-end transmitter with resonant matching techniques for mobile WiMAX/WiBro applications

A direct conversion front-end transmitter with the properties of high linearity and high single sideband rejection ratio is described in this paper. The transmitter employs two resonant matching techniques to improve its operating bandwidth. The first resonant circuit design is applied at the inter-stage of the LO input buffer in order to achieve a wideband frequency response which ranges from dc to 6 GHz. The second resonant circuit is applied at the power amplifier (PA) driver output stage to increase the matching bandwidth and meet both the Worldwide Interoperability for Microwave Access (WiMAX) and Wireless Broadband (WiBro) applications simultaneously. In addition, the sideband signal and carrier leakage of this transmitter are further minimized by a proposed calibration circuit design to achieve the error vector magnitude (EVM) specifications. The measured single sideband performance with calibration mechanism demonstrates approximately 15 dB improvement on sideband and carrier suppression. The rejected sideband and carrier signals can be up to 55.19 and 56.31 dBc, respectively. The measured dynamic gain range of the transmitter is 53 dB in 1-dB step with a maximum relative gain error lower than 0.4 dB. The transmitter delivers +0.766 dBm output power with EVM of −34.687 dB for the orthogonal frequency division multiple access (OFDMA) 64QAM-3/4 modulated signals. The measured constellation is minimized to be <1.5% with output power from −2.3 to −36.2 dBm.     

A 1.8-mW CMOS ΣΔ modulator with integrated mixer forA/D conversion of IF signals

In this paper, the design of a continuous-time baseband sigma-delta (ΣΔ) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF ΣΔ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF ΣΔ modulator is 0.2 mm² in 0.35-μm CMOS     

A 0.13 /spl mu/m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier

This paper presents a fully integrated CMOS receiver front-end based on a direct conversion architecture for UMTS/802.11b-g and a low-IF architecture at 100 kHz for DCS1800. The two key building blocks are a multiband low-noise amplifier (LNA) that uses positive feedback to improve its gain and a highly linear mixer. The front-end, integrated in a 0.13 /spl mu/m CMOS process, exhibits a minimum noise figure of 5.2 dB, a programmable gain that can be varied from 13.5 to 28.5 dB, an IIP3 of more than -7.5 dBm and an IIP2 better than 50 dBm. The total current consumption is 20mA from a 1.2V supply.     

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recyclinginput/output buffers

This paper presents a high-speed and low-power SRAM for portable equipment, which is operated by a single battery cell of around 1 V. Its memory cells are made up of high-threshold-voltage (high-V_th) MOSFETs in order to suppress the power dissipation due to large subthreshold leakage currents. For designing peripheral circuitry, we use SRAM's special feature that input signals of each logic gate during the standby time can be predicted. Low-V_th MOSFETs are assigned for the critical paths of memory-cell access. The leakage current in each logic gate is reduced by high-V_th MOSFETs, which are cut off during standby. The high-V_th, MOSFET in one logic gate can be shared with another logic gate in order to enlarge effective channel width. To shorten the readout time, a step-down boosted-wordline scheme suitable for current-sense readout and a new half-swing bidirectional double-rail bus are used. The data-writing time is halved by means of a pulse-reset wordline architecture. To reduce the power dissipation, a 32-divided memory array structure is employed with a new redundant address-decoding scheme. Also, data transition detectors and a charge-recycling technique are employed for reducing the power dissipation of data-I/O buffers. A 64-K-words×16-bits SRAM test chip, which was fabricated with a 0.5-μm multithreshold voltage CMOS (MTCMOS) process, has demonstrated a 75-ns address access time at a 1-V power supply. The power dissipation during standby is 1.2 μW, and that at a 10-MHz read operation with the modified checkerboard test pattern is 3.9 mW for 30-pF loads     

A 3.3-mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18-/spl mu/m CMOS with 70-dB dynamic range in 2-MHz bandwidth

A quadrature fourth-order, continuous-time, /spl Sigma//spl Delta/ modulator with 1.5-b quantizer and feedback digital-to-analog converter (DAC) for a universal mobile telecommunication system (UMTS) receiver chain is presented. It achieves a dynamic range of 70 dB in a 2-MHz bandwidth and the total harmonic distortion is -74 dB at full-scale input. When used in an integrated receiver for UMTS, the dynamic range of the modulator substantially reduces the need for analog automatic gain control and its tolerance of large out-of-band interference also permits the use of only first-order prefiltering. An IC including an I and Q /spl Sigma//spl Delta/ modulator, phase-locked loop, oscillator, and bandgap dissipates 11.5 mW at 1.8 V. The active area is 0.41 mm/sup 2/ in a 0.18-/spl mu/m 1-poly 5-metal CMOS technology.     

A 0.6-V 1.6-mW transformer-based 2.5-GHz downconversion mixer with +5.4-dB gain and -2.8-dBm IIP3 in 0.13-/spl mu/m CMOS

On-chip transformers are best suited to lower the supply voltage in RF integrated circuits. A design method to achieve a high current gain with an on-chip transformer operating in resonance is presented. The proposed method will be proven analytically and has been applied to a downconversion mixer. Thereby part of the overall gain of the mixer has been shifted from the RF input stage to the transformer. Thus, the power consumption has been reduced and, in spite of the low supply voltage, moderate linearity has been achieved. Although the transformer has a bandpass behavior, a 3-dB bandwidth of 900 MHz at a center frequency of 2.5 GHz has been achieved. The downconversion mixer has been realized in 0.13-mum CMOS. It consumes 1.6 mW from a 0.6-V supply. A gain of +5.4 dB, a third-order intercept point of -2.8 dBm, an input 1-dB compression point of -9.2 dBm, and a single-sideband noise figure of 14.8 dB have been achieved     

A time-variant analysis of the 1/f/sup 2/ phase noise in CMOS parallel LC-tank quadrature oscillators

This paper presents a study of 1/f/sup 2/ phase noise in quadrature oscillators built by connecting two differential LC-tank oscillators in a parallel fashion. The analysis clearly demonstrates the necessity of adopting a time-variant theory of phase noise, where a more simplistic, time-invariant approach fails to explain numerical simulation results even at the qualitative level. Two topologies of 5-GHz parallel quadrature oscillators are considered, and compact but nevertheless highly general, closed-form formulas are derived for the phase noise caused by the losses in the LC-tanks and by the noisy currents in the MOS transistors. A large number of spectreRF simulations, covering a wide range of working conditions for the oscillators, is used to validate the theoretical analysis.