Wide temperature (-20°C-95°C) operation of an uncooled2.5-Gb/s 1300-nm DFB laser

This letter describes a 2.5-Gb/s 1300-nm distributed feedback laser that can operate in a wide temperature range of -20°C to 95°C. We present RF and DC characteristics of the device and the statistical distribution of threshold current and slope efficiency at high temperature. Finally, we demonstrate the device performance in a 2.5-Gb/s small-form-factor module up to 85°C     

CMOS/SIMOX devices having a radiation hardness of 2 Mrad(Si)

Radiation-hardened CMOS/SIMOX devices have been produced by combining SIMOX with a newly developed lateral isolation structure. Even after exposure of these devices up to 2 Mrad(Si) of gamma-ray irradiation, they exhibit sufficient operational characteristics.     

短沟道CMOS／SIMOX器件与电路的制造

本文简要介绍短沟道ＣＭＯＳ／ＳＩＭＯＸ器件与电路的研制。在自制的ＳＩＭＯＸ材料上成功地制出了沟道长度为１．０μｍ的高性能全耗尽ＳＩＭＯＸ器件和１９级ＣＭＯＳ环形振荡器。Ｎ管和Ｐ管的泄漏电流均小于１×１０－１２Ａ／μｍ，在电源电压为５Ｖ时环振电路的门延迟时间为２８０ｐｓ。     

CMOS／SIMOX和CMOS／BESOI的γ射线辐照特性比较

用薄膜ＳＩＭＯＸ（ＳｅｐａｒａｔｉｏｎｂｙＩＭｐｌａｎｔａｔｉｏｎｏｆＯＸｙｇｅｎ）、厚膜ＢＥＳＯＩ（ｆｆｅｎｄｉｎｇａｎｄＥｔｃｈ－ｂａｃｋＳｉｌｉｃｏｎＯｎＩｎｓｕｌａｔｏｒ）和体硅材料制备了ＣＭＯＳ倒相器电路，并用６０Ｃｏγ射线进行了总剂量辐照试验。在不同偏置条件下，经不同剂量辐照后，分别测量了ＰＭＯＳ、ＮＭＯＳ的亚阈特性曲线，分析了引起ＭＯＳＦＥＴ阈值电压漂移的两种因素（辐照诱生氧化层电荷和新生界面态电荷）。对ＮＭＯＳ／ＳＩＭＯＸ，由于寄生背沟ＭＯＳ结构的影响，经辐照后背沟漏电很快增大，经３００Ｇｙ（Ｓｉ）辐照后器件已失效。而厚膜ＢＥＳＯＩ器件由于顶层硅膜较厚，基本上没有背沟效应，其辐照特性优于体硅器件。最后讨论了提高薄膜ＳＩＭＯＸ器件抗辐照性能的几种措施。     

CMOS／SIMOX器件总剂量辐照的研究

在新材料ＳＩＭＯＸ上制作ＣＭＯＳ器件,并采用静态Ｉ－Ｖ技术,研究了ＣＭＯＳ／ＳＩＭＯＸ在（６０）Ｃｏ－γ电离辐照场中辐照感生界面态、氧化物正电荷、阈值电压、静态漏电流等参数的变化。结果表明,在辐照过程中,氧化物正电荷增加较多,界面态增加较少,且ＮＭＯＳ和ＰＭＯＳ＂导通＂辐照偏置是最恶劣偏置。     

Suppression of parasitic bipolar action in ultra-thin-filmfully-depleted CMOS/SIMOX devices by Ar-ion implantation intosource/drain regions

This paper proposes a new technique that can effectively suppress the parasitic bipolar action (PBA) in ultrathin-film fully-depleted (FD)nMOSFET's/SIMOX with a floating body. In this technique, recombination centers are created in the source and drain (S/D) regions by deep Ar-ion implantation. They act to reduce the number of holes that accumulate in the body region by increasing the hole current flowing from the body region into the source region. Consequently, the rise of the body potential is lowered, and the parasitic bipolar action can be suppressed. A 0.25-μm gate nMOSFET/SIMOX fabricated with an Ar dose of 2×10¹⁴ cm^-2 exhibited excellent improvements in electrical characteristics: a reduction in the off-leakage current of over two orders of magnitude and an increase in the drain-to-source breakdown voltage beyond 0.6 V     

短沟道CMOS／SIMOX器件及电路的辐照特性研究

利用薄膜全耗尽ＣＭＯＳ／ＳＯＩ工艺成功地研制了沟道长度为１．０μｍ的薄膜抗辐照ＳＩＭＯＸＭＯＳＦＥＴ、ＣＭＯＳ／ＳＩＭＯＸ反相器和环振电路，Ｎ和ＰＭＯＳＦＥＴ在辐照剂量分别为３ｘ１０５ｒａｄ（Ｓｉ）和７ｘ１０５ｒａｄ（Ｓｉ）时的阈值电压漂移均小于１Ｖ，１９级ＣＭＯＳ／ＳＩＭＯＸ环振经过５ｘ１０５ｒａｄ（Ｓｉ）剂量的电离辐照后仍能正常工作，其门延迟时间由辐照前的２３７ｐｓ变为３２８ｐｓ。     

High-temperature electrical characteristics of GaAs MESFETs(25-400°C)

The effects of elevated ambient and substrate temperatures (25°C up to 400°C) on the electrical characteristics of integrated GaAs MESFETs in a state-of-the-art commercial technology are reported. The focus is on the large- and small-signal parameters of the transistors. The existence of zero-temperature-coefficient drain currents is demonstrated analytically and experimentally for enhancement- and for depletion-mode GaAs MESFETs. The data show that, while GaAs MESFETs generally display degradation mechanisms similar to those of silicon MOSFETs with increasing temperature, they incur several additional effects, prominent among which are increased gate leakage currents, lowered Schottky-barrier height, decreased large- and small-signal (gate) input resistances, decreased sensitivity to sidegating and backgating up to approximately 200°C, and increased small-signal drain resistance     

Design of SOI CMOS operational amplifiers for applications up to300°C

Design guidelines using two analog parameters (Early voltage and transconductance to drain current ratio) are proposed for correct operation of silicon-on-insulator (SOI) CMOS operational amplifiers (opamp) at elevated temperature up to 300°C. The dependence of these parameters on temperature is first described. A new single-stage CMOS opamp model using only these two parameters is presented and compared to measurements of several implementations operating up to 300°C for applications such as micropower (below 4 μW at 1.2 V supply voltage), high gain (65 dB) or high frequency up to 100 MHz. Trade-offs among such factors as gain, bandwidth, phase margin, signal swing, noise, matching, slew rate and power consumption are described. The extension to other architectures is suggested and the design methodology is valid for bulk as well as SOI CMOS opamps     

The effect of emitter current crowding on CMOS latchup characteristics

Both static latchup and intrinsic p-n-p bipolar characteristics are compared and analyzed for various p-n-p-n test structures using a modern p^-epi on p⁺CMOS technology. By varying the epi-layer thickness and the lateral spacing between the p⁺injector and the n-well boundary, it is shown that high-level injection and current crowding dominate the carrier transport inside the well under latchup conditions, especially when a shallow epi layer is used. As a result, a guideline for latchup-related design rules, applicable for large devices, which combines good latchup protection and a negligible penalty in area of performance, is proposed and discussed.     

Scalable 10 Gbit/s 4×20.25 μm CMOS/SIMOX ATM switch LSIcircuit based on distributed contention control

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput, 0.2 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption     

The characteristics of lectin binding to the surface of differentiated neuroblastoma C 1300 cells

Peculiarities of the binding of lectins of castor bean, cochlea, soya bean, lime bean and wheat germs to the surface of differential neuroblastoma C 1300 N 18 cells have been studied using the method electron cytochemistry. It is found that the quantity of the bound lectin conjugates with colloidal gold on the surface of differentiated cells varied considerably from that on the surface of nondifferentiated cells.     

Evaluation of 850°C wet oxide as the gate dielectric in a0.8-μm CMOS process

The authors describe a detailed comparison of a 850°C wet oxide and a 900°C dry oxide as the MOS gate dielectric in a 0.8-μm CMOS process. The device fabrication involves a GE 0.8-μm CMOS process. Emphasis is given to poly-Si gate linewidth measurements which are crucial to the interpretation of the results. The comparison of thin oxide integrity, device characteristics, hot-electron reliability, and total-dose radiation hardness between the two oxides is discussed. Specifically, it is pointed out why the PMOS punchthrough voltage requirements mandate the use of a 850°C wet oxide for the gate dielectric     

Electrical characteristics of scaled CMOSFET's with source/drainregions fabricated by 7° and 0° tilt-angle implantations

The differences of electrical characteristics in trench-isolated n-well CMOSFET's with LDD- and EPS-regions fabricated by 7° and 0° tilt-angle phosphorous implantations are measured and qualitatively explained. The CMOSFET's have channel lengths ranging from 5 to 0.4 μm and a channel width of 10 μm. The differences in impurity profiles due to the channeling ions by 0°-implantation cause the clear changes in the punchthrough-current characteristics and the substrate bias-voltage dependences of threshold voltages for both n- and p-MOSFET's. Meanwhile n- and p-MOSFET's fabricated by 7° and 0° implantations show nearly the same characteristics of threshold voltages and subthreshold swings which are almost determined by the impurity profiles in each channel region because the impurity profiles are scarcely affected by the channeling ions     

The effect of post-oxygen-implant annealing temperature on the channel mobilities of CMOS devices in oxygen-implanted silicon-on-insulator structures

The effects of post-oxygen-implant annealing temperature on the characteristics of MOSFET's in oxygen-implanted silicon-on-insulator (SOI) substrates are studied. The results show significant improvements in the electron and hole mobilities near the silicon/buried-oxide interface and in the electron mobility of the front-gate n-channel transistors in SOI substrates with higher post-oxygen-implant annealing temperature. The improvements in the transistor characteristics hence are attributed to the annihilation of oxygen precipitates and the reduction of defect density in the residual silicon film. By comparing the ring oscillators fabricated in SOI substrates annealed at 1150°C and 1250°C after oxygen implantation, a speed improvement of 15 percent is observed in substrates annealed at higher temperature.     

Generation-recombination noise in the near fully depleted SIMOX SOI n-MOSFET - physical characteristics and modeling

Noise measurement in the linear regime of the device characteristics shows the evolution of an important Lorentzian-like component in the thin-film SIMOX silicon-on-insulator (SOI) n-MOSFET, during the transition from fully depleted to near fully (or partially) depleted operation. The same noise component co-exists with another Lorentzian-like component commonly observed in the kink region, thus distinguishing it from the latter, which is associated with a shot-noise mechanism. Evidence unambiguously shows that local potential fluctuations, caused by random generation-recombination (G-R) processes at bulk defects in the depleted SOI film, are primarily responsible. Extracted trap energy of /spl sim/0.4-0.45 eV below the silicon conduction band edge confirms the involvement of deep-level electron traps, which are probably linked to the residual oxygen and SiO/sub 2/ precipitates in the SOI film. A new analytical G-R noise model yields bulk traps with an average density of /spl sim/10/sup 16/ cm/sup -3/, situated at /spl sim/22-32 nm from the front interface. With an area density comparable to that of the front interface states, the proximity of these bulk traps to the conducting channel in thin-film SIMOX SOI devices accounts for the dominance of bulk-trap induced G-R noise over conventional 1/f noise due to near-interface oxide traps.     

A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATMswitch based on scalable distributed arbitration

This paper presents the design and implementation of a scalable asynchronous transfer mode switch. We fabricated a 10-Gb/s 4×2 switch large-scale integration (LSI) that uses a new distributed contention control technique that allows the switch LSI to be expanded. The developed contention control is executed in a distributed manner at each switch LSI, and the contention control time does not depend on the number of connected switch LSI's. To increase the LSI throughput and reduce the power consumption, we used 0.25-μm CMOS/SIMOX (separation by implanted oxygen) technology, which enables us to make 221 pseudo-emitter-coupled-logic I/O pins with 1.25-Gb/s throughput. In addition, power consumption of 7 W is achieved by operating the CMOS/SIMOX gates at -2.0 V. This consumption is 36% less than that of bulk CMOS gates (11 W) at the same speed at -2.5 V. Using these switch LSI's, an 8×8 switching multichip module with 80-Gb/s throughput was fabricated with a compact size     

Size dependence of the characteristics of Si single-electrontransistors on SIMOX substrates

A Si single-electron transistor (SET) was fabricated by converting a one-dimensional (1-D) Si wire on a SIMOX substrate into a small Si island with a tunneling barrier at each end by means of pattern-dependent oxidation. Since the size of the Si island became as small as around 10 nm owing to this novel technique, the total capacitance of the SET was reduced to a value of the order of 1 aF, which guaranteed the conductance oscillation of the SET even at room temperature. Furthermore, a linear relation between the designed wire length and the gate capacitance of SET's was obtained, which clearly indicates that the single island was actually formed in the middle of the one dimensional Si wire. These results were achieved owing to the highly reproducible fabrication process based on pattern dependent oxidation of SIMOX-Si layers     

High-speed performance of 0.35 μm CMOS gates fabricated onlow-dose SIMOX substrates with/without an N-well underneath the buriedoxide layer

We present experimental results concerning the propagation delay time of the 0.35 μm CMOS gate chains (inverter, 3NAND, and 3NOR) fabricated on low-dose SIMOX substrates with and without the N-well formed underneath the buried oxide layer in the PMOS region. Using such experimental data as the capacitance voltage characteristics of the buried oxide layer, and the enhanced PMOS transistor drivability due to the negative back bias effect, we clarify the most essential factor of the high-speed performance of the CMOS/SIMOX circuits fabricated on a low-dose SIMOX substrate     

The effect of thin interfacial oxides on the electrical characteristics of silicon bipolar devices

The effect of thin interfacial oxides on the impurity diffusion from polysilicon to the silicon substrate has been studied in detail. Polysilicon films were deposited on the silicon substrate in two different process conditions to control the thickness of interfacial oxides. Results show that the presence of about 1-nm-thick oxides retarded the impurity diffusion by about 10 nm and an increase of the sheet resistance of about 10 percent has been observed. Bipolar devices, which are sensitive to the impurity profiles, were fabricated with identical processing apart from the polysilicon deposition conditions. A detailed analysis of their electrical characteristics shows the difference of collector current components and hence the increase of current gain by about two times. These results indicate that the effect of interfacial oxides on the impurity profile is expressed by the segregation coefficientm, which is the ratio of Csi/CpolySiat the interface. The sensitivity ofmfor the device characteristics was calculated by a process-device simulator, and it is demonstrated that the current gain is a strong function ofmfor shallow emitters.