The characteristics of CMOS devices in oxygen-implantedsilicon-on-insulator structures

The characteristics of CMOS devices fabricated in oxygen-implanted silicon-on-insulator (SOI) substrates with different oxygen doses are studied. The results show that transistor junction leakage currents are improved by orders of magnitude when the oxygen dose is decreased from 2.25×10¹⁸ cm^-2 to 1.4×10¹⁸ cm^-2 . The floating-body effect, i.e. transistor turn-on at lower gate voltage with dramatic improvement in subthreshold slope when the drain voltage is increased, is enhanced by the reduction in leakage current and hence the oxygen dose. In SOI substrates implanted with 1.4×10¹⁷ cm^-2 oxygen dose and annealed at 1150°C, back-channel mobilities are decreased by several orders of magnitude compared to the mobilities in the precipitate-free silicon film. These device characteristics are correlated with the microstructure at the silicon-buried-oxide interface, which is controlled by oxygen implantation and post-oxygen-implantation anneal     

A CV technique for measuring thin SOI film thickness

A technique is developed to measure silicon-on-insulator (SOI) silicon device film thickness using a MOSFET. The method is based on CV measurements between gate and source/drain at two different back-gate voltages. The SOI devices used in this study were n⁺ polysilicon gate n-channel MOSFETs fabricated with modified submicrometer CMOS technology on SIMOX (separation by implanted oxygen) wafers. The SIMOX wafers were implanted with a high dose of oxygen ions (10¹⁸ cm^-2) at 200 keV and subsequently annealed at 1230°C. The NMOS threshold boron implant dose is 2×10¹² cm^-2. This method is simple, nondestructive, and no special test structure is needed. Using this technique, SOI film thickness mapping was made on a finished wafer and a thickness variation of ±150 Å was found     

Reduction of oxide charge and interface-trap density in MOScapacitors with ITO gates

The electrical properties of MOS capacitors with an indium tin oxide (ITO) gate are studied in terms of the number density of the fixed oxide charge and of the interface traps N_f and N _it, respectively. Both depend on the deposition conditions of ITO and the subsequent annealing procedures. The fixed oxide charge and the interface-trap density are minimized by depositing at a substrate temperature of 240°C at low power conditions and in an oxygen-rich ambient. Under these conditions, as-deposited ITO films are electrically conductive. The most effective annealing procedure consists of a two-step anneal: a 45-s rapid thermal anneal at 950°C in N₂, followed by a 30 min anneal in N₂/20% H₂ at 450°C. Typical values obtained for N_it and N_f are 4.2×10¹⁰ cm^-2 and 2.8×10¹⁰ cm^-2, respectively. These values are further reduced to 1.9×10¹⁰ cm^-2 and ≲5×10⁹ cm^-2, respectively, by depositing approximately 25 nm polycrystalline silicon on the gate insulation prior to the deposition of ITO     

Ultrathin gate oxide grown on nitrogen-implanted silicon for deepsubmicron CMOS transistors

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0×10¹⁴/cm² and 2.0×10¹⁴ /cm². Initial O₂ injection method was applied for gate oxidation. The method is composed of an O₂ injection/N₂ anneal/main oxidation, and the control process is composed of a N₂ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 μm have been fabricated by use of the method. Compared to the control process, the initial O₂ injection process increases the amount of nitrogen piled up at the Si/SiO₂ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved     

Deep-level dominated current-voltage characteristics of buriedimplanted oxide silicon-on-insulator

Current-voltage characteristics of Au contacts formed on buried implanted oxide silicon-on-insulator (SOI) structures are discussed, which indicate that the dominant transport mechanism is space-charge-limited current (SCLC) conduction in the presence of deep-level states. The deep-level parameters, determined using a simple analysis, appear to be sensitive to anneal conditions used and subsequent processing. Silicon implanted with 1.7×10¹⁸ cm^-2 oxygen ions at 150 keV following a 1200°C anneal for 3 h shows deep level 0.37 eV below the conduction band edge with a concentration of unoccupied traps of ~ 2×10¹⁵ cm^-3 . In contrast, arsenic ion implantation, in the 1200°C annealed material with a dose of 1.5×10¹² cm^-2 at 60 keV and activated by rapid thermal annealing (RTA), introduces a deep level 0.25 eV below the conduction band edge with an unoccupied trap concentration of ~6×10¹⁷ cm^-2     

A single-poly EEPROM cell in SIMOX technology for high-temperatureapplications up to 250°C

A thin-film SIMOX technology has been used for fabrication of a single-polysilicon EEPROM cell suitable for high-temperature applications. The two transistor cell is composed of a select transistor and a floating gate transistor with 10 nm tunnel oxide. The EEPROM process extension requires only a few steps suitable for embedded memory applications with low cost and turn around time. Endurance and data retention characteristics of the SIMOX EEPROM cell are presented for a temperature of 250°C. The problem of temperature induced leakage currents in the select transistor at elevated temperatures is investigated     

Integrated amorphous and polycrystalline silicon thin-filmtransistors in a single silicon layer

Using a masked hydrogen plasma treatment to spatially control the crystallization of amorphous silicon to polycrystalline silicon in desired areas, amorphous and polycrystalline silicon thin-film transistors (TFTs) with good performance have been integrated in a single film of silicon without laser processing. Both transistors are top gate and shared all process steps. The polycrystalline silicon transistors have an electron mobility in the linear regime of ~15 cm²/Vs, the amorphous silicon transistors have a linear mobility of ~0.7 cm²/Vs and both have an ON/OFF current ratios of >10⁵. Rehydrogenation of amorphous silicon after the 600°C crystallization anneal using another hydrogen plasma is the critical process step for the amorphous silicon transistor performance. The rehydrogenation power, time, and reactor history are the crucial details that are discussed in this paper     

Investigation of inductively coupled plasma gate oxide on lowtemperature polycrystalline-silicon TFTs

By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350°C to achieve excellent gate oxide integrity of low leakage current<5×10^-8 A/cm² (at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5×10¹¹ /eV cm². The superior performance poly-Si TFTs using such a thin ICP oxide were attained to achieve a high ON current of 110 μA/μm at V_D=1 V and V_G=5 V and the high electron field effect mobility of 231 cm²/V·S     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

Plasma damage immunity of thin gate oxide grown on very lightly N+ implanted silicon

Plasma damage immunity of gate oxide grown on very low dose (2×10¹³/cm²) N⁺ implanted silicon is found to be improved compared to a regular gate oxide of similar thickness. Both hole trapping and electron trapping are suppressed by the incorporation of nitrogen into the gate oxide. Hole trapping behavior was determined from the relationship between initial electron trapping slope (IETS) and threshold voltage shifts due to current stress. This method is believed to be far more reliable than the typical method of initial gate voltage lowering during current stress     

Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂      

Gate oxide integrity of thermal oxide grown on high temperatureformed Si0.3Ge0.7

We have investigated the gate oxide integrity of thermal oxides direct grown on high temperature formed Si_0.3Ge_0.7. Good oxide integrity is evidenced by the low interface-trap density of 5.9×10¹⁰ eV^-1 cm^-2, low oxide charge density of -5.6×10¹⁰ cm^-2, and the small stress-induced leakage current after -3.3 V stress for 10 000 s. The good gate oxide integrity is due to the high temperature formed and strain-relaxed Si_0.3Ge_0.7 that has a original smooth surface and stable after subsequent high temperature process     

Argon ion-implantation on polysilicon or amorphous-silicon forboron penetration suppression in p+ pMOSFET

In this paper, a technique to use Ar ion-implantation on the p⁺α-Si or poly-Si gate to suppress the boron penetration in p⁺ pMOSFET is proposed and demonstrated. An Ar-implantation of a dose over 5×10¹⁵ cm^-2 is shown to be able to sustain 900°C annealing for 30 min for the gate without having the underlying gate oxide quality degraded. It is believed to be due to gettering of fluorine, then consequently boron, by the bubble-like defects created by the Ar implantation in the p⁺ gate region to reduce the B penetration. Excellent electrical characteristics like dielectric breakdown (E_bd), interface state density (D_it), and charge-to-breakdown (Q_bd) on the gate oxide are obtained. The technique is compatible to the present CMOS process. The submicron pMOSFET fabricated by applying this technique exhibit better subthreshold characteristics and hot carrier immunity     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance     

Practical reduction of dislocation density in SIMOX wafers

The dislocation density in the superficial silicon layers of SIMOX wafers formed under different oxygen implantation conditions has been investigated using a Secco etching technique. An extremely low dislocation density in the order of 10/sup 2/ cm/sup -2/ has been obtained for waters implanted at 180 keV with a dose of 0.4*10/sup 18/ and doses ranging from 0.9 to 1.2*10/sup 18/O/sup +//cm/sup 2/ at a wafer temperature of 550 degrees C followed by post-implant anneal at temperatures higher than 1300 degrees C. The buried oxide layers of the SIMOX wafers have breakdown voltages higher than 40 V.<>     

Effects of post-deposition anneal on the electrical properties ofSi3N4 gate dielectric

The effects of postdeposition anneal of chemical vapor deposited silicon nitride are studied. The Si₃N₄ films were in situ annealed in either H₂(2%)/O₂ at 950°C or N₂O at 950°C in a rapid thermal oxidation system. It is found that an interfacial oxide was grown at the Si₃N₄/Si interface by both postdeposition anneal conditions. This was confirmed by thickness measurement and X-ray photoelectronic spectroscopy (XPS) analysis. The devices with H₂ (2%)/O₂ anneal exhibit a lower gate leakage current and improved reliability compared to that of N₂O anneal. This improvement is attributed to a greater efficiency of generating atomic oxygen in the presence of a small amount of hydrogen, leading to the elimination of structural defects in the as-deposited Si₃N ₄ film by the atomic oxygen. Good drivability is also demonstrated on a 0.12 μm n-MOSFET device     

The low-temperature anodization of silicon in a gaseous plasma

A comprehensive investigation of the low-temperature anodization of silicon in RF and microwave oxygen plasmas is discussed. A comparison of the growth results and ion signals observed, using quadropole mass spectrometry, indicates a strong correlation between the growth rate and the presence of O^- ions in the plasma. Characterization of parameters such as pressure, electrode spacing, and current density has allowed wafers up to 4-in. diameter to be anodized with good growth rates (0.3 μm/h) and excellent oxide uniformity, using low temperatures (⩽600°C), low input power densities (~59 W-cm^-2), and low current densities (~7 mA-cm^-2). Oxide properties such as etch rate and refractive index were found to be indistinguishable from thermally grown oxides. Optimization of anneals and the use of a halogen gas enables plasma oxides with high breakdown fields (10-11 MV/cm), an interface trap density of ~5×10¹⁰ cm^-2-eV^-1 at midgap, and a fixed oxide charge of 6×10¹⁰ cm^-2 to be fabricated without resorting to high-temperature (⩾600°C) processing     

Positive flatband voltage shift in MOS capacitors on n-type GaN

GaN MOS capacitors were fabricated using silicon dioxide deposited by low-pressure chemical vapor deposition oxide at 900°C. The MOS capacitor flatband voltage shift versus temperature was used to determine a pyroelectric charge coefficient of 3.7 × 10⁹ q/cm²-K, corresponding to a pyroelectric voltage coefficient of 7.0 × 10⁴ V/m-K     

0.2-μm p+-n junction characteristics dependent onimplantation and annealing processes

Junction depth, sheet resistance, dopant activation, and diode leakage current characteristics were measured to find out the optimal processing conditions for the formation of 0.2-μm p⁺-n junctions. Among the 2×10¹⁵ cm^-2 BF₂ implanted crystalline, As or Ge preamorphized silicon, the crystalline and Ge preamorphized samples exhibit excellent characteristics. The thermal cycle of furnace anneal (FA) followed by rapid thermal anneal (RTA) shows better characteristics than furnace anneal, rapid thermal anneal, or rapid thermal anneal prior to furnace anneal