纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

金属纳米晶存储器件数据保持能力建模与验证

金属纳米晶存储器件具有低功耗、高速读写特性及较高的可靠性,因此近年来在非易失存储器研究领域备受关注.对比分析讨论了量子限制效应与库仑阻塞效应对金属纳米晶费密能级的影响后,发现库仑阻塞效应会严重削弱器件数据保持能力.在综合考虑金属纳米晶量子限制效应和库仑阻塞效应的基础上,提出了金属纳米晶存储器件数据保持能力分析模型,并通过与相关研究文献的实验数据对比分析,证实了本模型的合理性.     

利用同步晶化法制备的镍纳米晶的电荷存储特性

快速退火纳米晶化法是目前常用的金属纳米晶制备方法,但其后续600~900℃高温退火会降低器件的电学特性和可靠性。本文提出了热预算低的金属纳米晶制备的新方法—沉积过程中的同步金属薄膜原位纳米晶化法,可以省掉后续单独的退火处理工艺,使金属薄膜同步产生纳米晶化,降低工艺热功耗及简化工艺,从而有效地改善上述薄膜沉积后退火纳米晶化法的不足。在不同衬底温度（250~325 ?C）下,利用同步纳米晶化法制备镍纳米晶存储器。随着生长温度的增加,其存储窗口先增加到最大值再降低。衬底温度为300 ?C时,其存储窗口（2.78 V）最大。与快速热退火法镍纳米晶存储器相比较,同步纳米晶化法制备镍纳米晶存储器具有更强的电荷存储能力。另外,研究了不同操作电压和脉冲时间下器件的平带电压偏移量,当操作电压增加到±10 V时出现了较大的平带电压偏移量,这表明器件发生了大量的载流子（电子和空穴）注入现象。最后,模拟了金属纳米晶存储器的载流子（电子和空穴）注入和释放过程。     

纳米晶非挥发性存储器研究进展

介绍了纳米晶非挥发性存储器的发展状况和基本工作原理,比较了纳米晶非挥发性存储器所涉及到的各种不同的电荷输运机制,系统介绍了纳米晶非挥发性存储器在纳米晶材料设计、纳米晶晶体生长控制方法、隧穿/控制介质层工程和新型存储器器件结构等方面的一些最新研究进展,对纳米晶非挥发性存储器的研究趋势进行了展望。     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

基于硅纳米晶的非挥发存储器制备与存储特性

硅纳米晶非挥发存储器由于其卓越的性能以及与传统工艺的高度兼容性,近来引起高度关注。采用两步低压化学气相淀积(LPCVD)生长方式制备硅纳米晶(Si-NC),该方法所制备的硅纳米晶具有密度高、可控性好的特点,且完全兼容于传统CMOS工艺。在此基础上制作四端硅纳米晶非挥发存储器,该器件展示出良好的存储特性,包括10 V操作电压下快速地擦写,数据保持特性的显著提高,以及在105次擦写周期以后阈值电压(Vt)飘移低于10%的良好耐受性。该器件在未来高性能非挥发存储器应用上极具潜质。     

使用化学方法常温合成金纳米晶并通过旋涂工艺将其组装的存储特性可调型非易失性存储器

3C行业的不断发展,催生了对高密度、持久保存、快速擦写、鲁棒可靠性的非易失性存储器(如flash)的持续需求,促使我们在科研上不断地深入研究新材料、新工艺。在本文中,我们首次采用了区别于传统CMOS工艺的两步工艺方法来制作金属纳米晶非易失性存储器。这种方法,由于将金纳米晶的化学合成和后续组装分离开来,所以能够独立地调节纳米晶的尺寸和组装密度,而且可以很好地避免一直困扰的金属扩散问题。最终的形貌表征和电学测量结果,证实存在一个最优化的纳米晶密度--在这个最优化条件下,我们的存储器件,既有持久的保存时间,又有较大的存储窗口。而组装密度的可调,同时可以满足我们对于大的存储窗口/较长保存时间某一方面的偏好。这些实验结果,都很好地证明了我们两步工艺方法的可行性。     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

纳米硅单电子存储器研究进展

纳米硅单电子存储器与现有微电子存储器相比,由于具有更低的功耗、更快的开关速度、更高的存储密度以及更高的集成度,被认为是在非挥发性存储器的研究中最有可能成为未来快闪存储器的候选者之一.文章论述了纳米硅单电子存储器的工作原理、研究现状及发展趋势.     

Asymmetric electric field enhancement in nanocrystal memories

The electrostatic model for nanocrystal memories is used to illustrate the fundamental difference of the metal nanocrystal memory in low-voltage program/erase (P/E) operations in comparison with semiconductor nanocrystal and trap-based memories. Due to repulsion of potential contours inside conductors, the metal nanocrystals will significantly enhance the electric field between the nanocrystal and the sensing channel set up by the control gate bias and, hence, can achieve much higher efficiency in low-voltage P/E. On the other hand, the electric field originated from the stored charge will only be slightly different for metal and semiconductor nanocrystal cases. We presented the electrostatic models by both approximate analytical formulation and three-dimensional numerical simulation in a nanocrystal array. Operations of P/E and read disturbance were analyzed for the cases of homogeneous charge distribution, silicon, and metal nanocrystals. In the P/E condition of +5/-5 V, the metal nanocrystal memory offers around 1.6 times higher peak fields than Si counterparts and almost three times higher than that from the one-dimensional model for homogeneous charge distribution. The field enhancement factor suggests the design criteria of oxide thickness, nanocrystal size, and spacing. The advantage of asymmetric field enhancement of metal nanocrystals will be even more prominent when high-K gate dielectrics are employed.     

Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications

The self-assembly of metal nanocrystals including Au, Ag, and Pt on ultrathin oxide for nonvolatile memory applications are investigated. The self-assembly of nanocrystals consists of metal evaporation and selective rapid-thermal annealing (RTA). By controlling process parameters, such as the thickness of the deposited film, the post-deposition annealing temperatures, and the substrate doping concentration, metal nanocrystals with density of 2–4 × 10¹¹ cm⁻², diameter less than 8.1 nm, and diameter deviation less than 1.7 nm can be obtained. Observation by scanning-transmission electron microscopy (STEM) and convergent-beam electron diffraction (CBED) shows that nanocrystals embedded in the oxide are nearly spherical and crystalline. Metal contamination of the Si/SiO₂ interface is negligible, as monitored by STEM, energy dispersive x-ray spectroscopy (EDX), and capacitance-voltage (C-V) measurements. The electrical characteristics of metal, nanocrystal nonvolatile memories also show advantages over semiconductor counterparts. Large memory windows shown by metal nanocrystal devices in C-V measurements demonstrate that the work functions of metal nanocrystals are related to the charge-storage capacity and retention time because of the deeper potential well in comparison with Si nanocrystals.     

Statistical Metrology of Metal Nanocrystal Memories With 3-D Finite-Element Analysis

We study the parametrical yield of memory windows for the metal nanocrystal (NC) Flash memories with consideration of the 3-D electrostatics and channel percolation effects. Monte Carlo parametrical variation that accounts for the number and size fluctuations in NCs as well as channel length is used to determine the threshold voltage distribution and bit error rate for gate length scaling to 20 nm. Devices with nanowire-based channels are compared with planar devices having the same gate stack structure. Scalability prediction by 1-D analysis is found to be very different from 3-D modeling due to underestimation of effective NC coverage and failure to consider the 3-D nature of the channel percolation effect.      

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.     

Fabrication of Ni Nanocrystal Flash Memories Using a Polymeric Self-Assembly Approach

Fabrication of nickel nanocrystal flash memories using a polymeric approach is presented. Heat treatment of the poly (styrene-b-methyl methacrylate) block copolymer with a molecular weight of 67 000 g/mol followed by PMMA removal in an organic solvent created a porous PS film with 20-nm-diameter pores and a total pore density of ~6 times 10¹⁰ cm^-2. A trilayer pattern-transfer approach was employed in order to solve the metal lift-off issue intertwined with the low aspect ratio block copolymer patterns. As a result, a highly uniform self- assembled array of nickel nanocrystals was attained and utilized for flash memory fabrication. The memory devices demonstrated an unchanged memory window for up to 2 times 10⁵ stressing cycles.     

Metal nanocrystal memories. I. Device design and fabrication

This paper describes the design principles and fabrication process of metal nanocrystal memories. The advantages of metal nanocrystals over their semiconductor counterparts include higher density of states, stronger coupling with the channel, better size scalability, and the design freedom of engineering the work functions to optimize device characteristics. One-dimensional (1-D) analyses are provided to illustrate the concept of work function engineering, both in direct-tunneling and F-N-tunneling regimes. A self-assembled nanocrystal formation process by rapid thermal annealing of ultrathin metal film deposited on top of gate oxide is developed and integrated with NMOSFET to fabricate such devices