Suppression of corner effects in wide-channel triple-gate bulk FinFETs

This paper presents a method of eliminating corner effects in triple-gate bulk FinFETs. The parasitic device in FinFET’s corners can be turned off by increasing body doping in corner regions by corner implantation. Corner implantation described in this work does not require additional masks, rotation or tilt. This method is investigated in idealized (with rectangular cross-section of the fin) and realistic (with rounded top corners of the fin) triple-gate bulk FinFETs and has shown considerable improvements: kink effect in transfer characteristics is completely eliminated, threshold voltage increased by up to 0.43 V, subthreshold swing and drain-induced barrier-lowering decreased to values under 95 mV/dec and 16 mV/V, respectively. Optimization is performed on the realistic rounded-corner FinFET structure to find the proper body doping and corner implantation peak values for acceptable threshold voltage and on-state current.     

Double-gate 1T-DRAM cell using nonvolatile memory function for improved performance

We propose a double-gate (DG) 1T-DRAM cell combining SONOS type storage node on the back-gate (control-gate) for nonvolatile memory function. The cell sensing margin and retention time characteristics were systematically examined in terms of control-gate voltage (V_cg) and nonvolatile memory (NVM) function. The additional NVM function is achieved by Fowler-Nordheim (FN) tunneling electron injection into the nitride storage node. The injected electrons induce a permanent hole accumulation layer in silicon body which improves the sensing margin and retention time characteristics. To demonstrate the effect of stored electrons in the nitride layer, experimental data are provided using 0.6 μm devices fabricated on SOI wafers.     

Reduction of gate-to-channel tunneling current in FinFET structures

In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO₂ than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6 nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25 nm. The possible reasons for the observed effect are discussed.     

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.     

DC self-heating effects modelling in SOI and bulk FinFETs

DC thermal effects modelling for nanometric silicon-on-insulator (SOI) and bulk fin-shaped field-effect transistors (FinFETs) is presented. Among other features, the model incorporates self-heating effects (SHEs), velocity saturation and short-channel effects. SHEs are analysed in depth by means of thermal resistances, which are determined through an equivalent thermal circuit, accounting for the degraded thermal conductivity of the ultrathin films within the device. Once the thermal resistance for single-fin devices has been validated for different gate lengths and biases, comparing the modelled output characteristics and device temperatures with numerical simulations obtained using Sentaurus Device, the thermal model is extended by circuital analysis to multi-fin devices with multiple fingers.     

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

In this paper a computationally efficient surface-potential-based compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates is presented. A fully-depleted SOI MOSFET with a back-gate is essentially an independent double-gate device. To the best of our knowledge, existing surface-potential-based models for independent double-gate devices require numerical iteration to compute the surface potentials. This increases the model computational time and may cause convergence difficulties. In this work, a new approximation scheme is developed to compute the surface potentials and charge densities using explicit analytical equations. The approximation is shown to be computationally efficient and preserves important properties of fully-depleted SOI MOSFETs such as volume inversion. Drain current and charge expressions are derived without using the charge sheet approximation and agree well with TCAD simulations. Non-ideal effects are added to describe the I-V and C-V of a real device. Source-drain symmetry is preserved for both the current and the charge models. The full model is implemented in Verilog-A and its convergence is demonstrated through transient simulation of a coupled ring oscillator circuit with 2020 transistors.     

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity,short channel effects (SCEs),leakage currents,device variability and reliability etc.Nowadays,multigate structure has become the promising candidate to overcome these problems.SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs),because of its more effective gate-controlling capabilities.In this paper,our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length.Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility,electric field,electric potential,sub-threshold slope (SS),ON current (Ion),OFF current (Ioff) and Ion/Ioff ratio.The potential benefits of SOI FinFET at drain-to-source voltage,VDS =0.05 V and VDS =0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (Av),output conductance (gd),trans-conductance (gm),gate capacitance (Cgg),and cut-off frequency (fT =gm/2πCgg) with spacer region variations.     

Mobility in ultrathin SOI MOSFET and pseudo-MOSFET: Impact of the potential at both interfaces

The mobility-thickness dependence in SOI films is clarified. Measurements in fully depleted SOI MOSFETs show that the low-field mobility at the front channel decreases by thinning the Si film or by sweeping the back gate from depletion into accumulation. We demonstrate that this mobility degradation is only apparent, being related to the potential value at the surface facing the channel. This opposite-surface potential induces an intrinsic vertical field which adds to the usual gate-related field. The mobility drop simply indicates a deviation from the low-field condition which cannot be achieved. We propose an updated model for proper extraction and interpretation of the low-field mobility. Pseudo-MOSFET results reveal the existence of a similar additional vertical field in bare SOI wafers, induced by charges present on the unpassivated surface. This intrinsic field increases in thinner films and affects pseudo-MOSFET conduction. The mobility decrease measured in SOI wafers with thinner films reflects the increasing impact of the intrinsic field and does not imply any degradation in quality of film-BOX interface.     

抑制 SOIp- MOSFET中短沟道效应的 GeSi源 /漏结构

提出在 SOI p- MOSFET中采用 Ge Si源 /漏结构 ,以抑制短沟道效应 .研究了在源、漏或源与漏同时采用 Ge Si材料对阈值电压漂移、漏致势垒降低 (DIBL)效应的影响 ,并讨论了 Ge含量及硅膜厚度变化对短沟道效应及相关器件性能的影响 .研究表明 Ge含量应在提高器件驱动电流及改善短沟道效应之间进行折中选择 .对得到的结果文中给出了相应的物理解释 .随着器件尺寸的不断缩小 ,Ge Si源 /漏结构不失为 p沟 MOS器件的一种良好选择     

SOI MOSFET自加热效应测试方法

为研究自加热效应对绝缘体上硅(SOI)MOSFET漏电流的影响,开发了一种可同时探测20 ns时瞬态漏源电流-漏源电压(Ids-Vds)特性和80μs时直流静态Ids-Vds特性的超快脉冲I-V测试方法。将被测器件栅漏短接、源体短接后串联接入超快脉冲测试系统,根据示波器在源端采集的电压脉冲的幅值计算漏电流受自加热影响的动态变化过程。选取体硅NMOSFET和SOI NMOSFET进行验证测试,并对被测器件的温度分布进行仿真,证实该方法用于自加热效应的测试是准确有效的,能为建立准确的器件模型提供数据支撑。采用该方法对2μm SOI工艺不同宽长比的NMOSFET进行测试,结果表明栅宽相同的器件,栅长越短,自加热现象越明显。     

深亚微米SOI MOSFET低压热载流子效应研究

当器件尺寸进入深亚微米后，SOI MOS集成电路中的N沟和P沟器件的热载流子效应引起的器件退化已不能忽视。通过分别测量这两种器件的跨导、阈值电压等参数的退化与应力条件的关系，分析了这两种器件的退化规律，对这两种器件的热载流子退化机制提出了合理的解释。并模拟了在最坏应力条件下，最大线性区跨导Gmmax退化与漏偏压应力Vd的关系，说明不同沟长的器件在它们的最大漏偏压以下时，能使Gmmax的退化小于10％。     

SOIMOSFET因辐照引起的部分耗尽与全耗尽过渡区的漂移

首次报道了辐照所引起的 SOI/ MOS器件 PD (部分耗尽 )与 FD (全耗尽 )过渡区的漂移 .基于含总剂量辐照效应的 SOI MOSFET统一模型 ,模拟了 FD与 PD过渡区随辐照剂量的漂移 .讨论了辐照引起 FD与 PD器件转化的原因 ,进一步分析了 FD与 PD器件的辐照效应     

深亚微米PD和FD SOI MOS器件热载流子损伤的研究

研究了深亚微米PD和FD SOI MOS器件遭受热截流子效应(HCE)后引起的器件参数退化的主要差异及其特点，提出了相应的物理机制，以解释这种特性。测量了在不同应力条件下最大线性区跨导退化和闽值电压漂移，研究了应力Vg对HCE退化的影响，并分别预测了这两种器件的寿命，提出了10年寿命的0．3μm沟长的PD和FD SOI MOS器件所能承受的最大漏偏压。     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

A New SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

To improve the characteristics of breakdown voltage and specific on‐resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon‐on‐insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on‐resistance. The breakdown voltage and the specific on‐resistance of the fabricated device is 352 V and 18.8 m·cm² with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on‐state is over 200 V and the saturation current at V_gs=5 V and V_ds=20 V is 16 mA with a gate width of 150 µm.     

一种新型高性能FinFET的设计与特性分析

针对CMOS器件随着技术节点的不断减小而产生的短沟道效应和漏电流较大等问题,设计了一种新型直肠形鳍式场效应晶体管(FinFET),并将该新型器件与传统的矩形结构和梯形结构的FinFET通过Sentaurus TCAD仿真软件进行对比。结果表明,当栅极长度控制在10 nm时,新型器件相比于另外两种传统的FinFET具有更小的鳍片尺寸,且鳍片高度不低于抑制短沟道效应的临界值。仿真结果显示,这种新型的FinFET具有更好的开关特性和亚阈值特性。同时,该器件在射频方面的特性参数也显示出该器件具有较高性能,并有一定的实际应用价值。     

Analytical threshold voltage and subthreshold swing model for TMG FinFET

An analytical modelling of the subthreshold surface potential, threshold voltage (V_T) and subthreshold swing (SS) for a triple material gate (TMG) FinFET is presented. The basis of the 3D solution is two separate 2D solutions. The FinFET is separated into two 2D structures: asymmetric triple material double gate (TMDG) and symmetric TMDG MOSFETs. Their potential distributions are obtained by solving the corresponding 2D Poisson’s equations. The potential distribution in TMG FinFET is obtained by a parameter-weighted sum of the two 2D solutions. Utilising the concept of minimum source barrier as the leakiest channel path, the minimum value of the surface potential is developed from the potential model. This leads to the derivations for the threshold voltage and SS. Furthermore, the effects of variation in gate work function and gate length are investigated for analytically developed SS and V_T models. Our models are validated against TCAD Sentaurus-simulated results and found to be quite accurate.     

FORWARD GATED—DIODE METHOD FOR DIRECTLY MEASURING STRESS—INDUCED INTERFACE TRAPS IN NMOSFET／SOI

Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter.This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device‘s hot carrier characteristics.For the tested device, an expected power law relationship of Δnit-t^0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.     

Three-interface pseudo-MOSFET models for the characterization of SOI wafers with ultrathin film and BOX

The electrical characterization of unprocessed fully depleted silicon-on-insulator (SOI) layers relies on the pseudo-MOSFET (Ψ-MOSFET) technique. We propose three-interface models which are more appropriate for addressing the case of SOI wafers with ultrathin body and BOX (UTB²). The novel models for threshold voltage and subthreshold swing account for the channel-to-surface and channel-to-substrate coupling which are important effects, respectively, in ultrathin films and thin BOX. The influence of the density of traps at each of the three interfaces (free surface, channel/BOX and BOX/substrate) is discussed. The models are validated with experimental results from a range of SOI film thicknesses.     

Experimental characterisation of PD SOI MOSFET devices fabricated with diamond-shaped body contact

The design of diamond-shaped body-contacted (DSBC) devices using standard layers in a 0.35?µm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process is described in this article. The technology is based on a manufacturable partially depleted SOI process targeted for radio frequency applications. The experimental measurements of drain induced barrier lowering for the fabricated DSBC structure showed suppression of floating body effects (FBE) at the promising rate of 24?mV/V. The measurement results confirmed current drive (I _DS) improvement by 25% at V _DS?=?1.5?V and V _GS?=?1.5?V compared to conventional body-tied-source (BTS) device. A constant and steady output conductance (g _DS) in the saturation region was observed for the DSBC structure. The gate trans-conductance (g _m) is improved by 34% at V _DS?=?1.5?V and V _GS?=?1.5?V compared to conventional BTS device. Three-dimensional device simulation provides insight on FBE suppression and channel current improvement. Experimental results confirmed the area efficiency of the DSBC structure and its excellent current drive performance.