Low-power-consumption and high-gain CMOS distributed amplifiers using cascade of inductively coupled common-source gain cells for UWB systems

A distributed amplifier with new cascade inductively coupled common-source gain-cell configuration is presented. Compared with other existing gain-cell configurations, the proposed cascade common-source gain cell can provide much higher transconductance and, hence, gain. The new distributed amplifier using the proposed gain-cell configuration, fabricated via a TSMC 0.18-/spl mu/m CMOS process, achieves an average power gain of around 10 dB, input match of less than -20 dB, and noise figure of 3.3-6.1 dB with a power consumption of only 19.6 mW over the entire ultra-wideband (UWB) band of 3.1-10.6 GHz. This is the lowest power consumption ever reported for fabricated CMOS distributed amplifiers operating over the whole UWB band. In the high-gain operating mode that consumes 100 mW, the new CMOS distributed amplifier provides an unprecedented power gain of 16 dB with 3.2-6-dB noise figure over the UWB range.     

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

5.8-GHz CMOS T/R switches with high and low substrate resistances in a 0.18-/spl mu/m CMOS process

Two single-pole, double-throw transmit/receive switches were designed and fabricated with different substrate resistances using a 0.18-/spl mu/m p/sup $/substrate CMOS process. The switch with low substrate resistances exhibits 0.8-dB insertion loss and 17-dBm P/sub 1dB/ at 5.825 GHz, whereas the switch with high substrate resistances has 1-dB insertion loss and 18-dBm P/sub 1dB/. These results suggest that the optimal insertion loss can be achieved with low substrate resistances and 5.8-GHz T/R switches with excellent insertion loss and reasonable power handling capability can be implemented in a 0.18-/spl mu/m CMOS process.     

A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and /spl plusmn/2.5-cm range finding

A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in 0.18-/spl mu/m CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of /spl plusmn/2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mW, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mW. The range for data communication is 1 m with BER of 10/sup -3/. For ranging applications, the transmitter can reduce the power to 0.7 /spl mu/W for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 /spl mu/V/m, and thus the UWB system can be operated even under the current Japan radio regulations.     

On the Development of an Integrated CMOS-Based UWB Tunable-Pulse Transmit Module

A novel low-cost low-power fully integrated tunable transmit module composed of a tunable CMOS monocycle pulse generator and compact uniplanar antenna was designed, built, and tested for ultra-wideband (UWB) impulse systems. The CMOS tunable pulse generator integrates a tuning delay circuit, square-wave generator, impulse-forming circuit, and pulse-shaping circuit in a single chip using a standard low-cost 0.25-$muhbox m$CMOS process. It can generate a monocycle pulse and Gaussian-type impulse (without the pulse-shaping circuitry) signals with tunable pulse duration. A compact uniplanar UWB antenna was also developed and integrated directly with the CMOS pulse generator chip to form the complete integrated tunable UWB transmit module. Measured results show that the CMOS tunable pulse generator can produce a 0.3–0.6-V peak-to-peak monocycle pulse with 140–350-ps tunable pulse duration and a 0.5–1.3-V peak-to-peak impulse signal with 100–300-ps tunable pulse-duration, and the uniplanar antenna has less than a 18-dB return loss and is suitable for transmitting/receiving UWB time-domain impulse signals covering the entire UWB bandwidth of 3.1–10.6 GHz. Good agreement between measured and calculated performance is also achieved. The UWB transmit module was experimentally characterized and its performance is verified. This UWB module finds applications in various time-domain UWB systems including wireless communications and radar.     

A UWB CMOS transceiver

A direct-conversion ultra-wideband (UWB) transceiver for Mode 1 OFDM applications employs three resonant networks and three phase-locked loops. Using a common-gate input stage, the receiver allows direct sharing of the antenna with the transmitter. Designed in 0.13-/spl mu/m CMOS technology, the transceiver provides a total gain of 69-73 dB and a noise figure of 6.5-8.4 dB across three bands, and a TX 1-dB compression point of -10 dBm. The circuit consumes 105 mW from a 1.5-V supply.     

15-GHz fully integrated nMOS switches in a 0.13-/spl mu/m CMOS process

Two fully integrated nMOS switches have been demonstrated at 15 GHz in a 0.13-/spl mu/m CMOS foundry process. One incorporates on-chip LC impedance transformation networks (ITNs) while the second one does not. The switches with and without ITNs achieve the same 1.8-dB insertion loss at 15 GHz, but 21.5 and 15 dBm input P/sub 1dB/, respectively. The degradation of insertion loss due to use of ITNs is compensated by reducing the mismatch loss caused by the bond pad parasitics. The switch without ITNs is suitable for 3.1-10.6 GHz ultra-wide-band (UWB) applications. The switch with ITNs has /spl sim/5 dB worse isolation than the switch without. The difference is due to the larger transistor size of the switch with ITNs, which introduces lower parasitic impedance path between Tx/Rx ports and antenna port.     

On the feasibility of CMOS multiband phase shifters for multiple-antenna transmitters

We present the design of an integrated multiband phase shifter in RF CMOS technology for phased array transmitters. The phase shifter has an embedded classical distributed amplifier for loss compensation. The phase shifter achieves a more than 180/spl deg/ phase tuning range in a 2.4-GHz band and a measured more than 360/spl deg/ phase tuning range in both 3.5-GHz and 5.8-GHz bands. The return loss is less than -10dB at all conditions. The feasibility for transmitter applications is verified through measurements. The output power at a 1-dB compression point (P/sub 1 dB/) is as high as 0.4dBmat 2.4GHz. The relative phase deviation around P/sub 1 dB/ is less than 3/spl deg/. The design is implemented in 0.18-/spl mu/mRF CMOS technology, and the chip size is 1200/spl mu/m /spl times/ 2300 /spl mu/m including pads.     

Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications

CMOS transmit-receive (T/R) switches have been integrated in a 0.18-/spl mu/m standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P/sub 1dB/), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P/sub 1dB/, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W).     

A 0.25-mm CMOS T/R switch for UWB wireless communications

A T/R switch, fabricated using standard 0.25-/spl mu/m CMOS process, for ultra wide-band (UWB) wireless communications is presented. The switch is designed based on the concept of synthetic transmission line, utilizing both CPW and CMOS transistors, to achieve not only an extremely wide bandwidth but also a linear phase response necessary for time-domain UWB applications. On-chip measurement is completed in both frequency and time domains. Frequency-domain measured results show insertion loss of 2.2-4.2 dB, isolation from 34-48 dB, and highly linear transmission phase from 0.45 MHz to 13 GHz. These results are quite consistent with the calculations. Particularly, the time-domain pulse measurement shows that the output pulses resemble closely the input pulses with very little reflection, demonstrating the switch's suitability for true time-domain UWB applications. The developed switch is ready to be integrated with other CMOS RFICs to form on-chip transceivers for various UWB applications.     

0.18 /spl mu/m 3-6 GHz CMOS broadband LNA for UWB radio

A 3-6 GHz CMOS broadband low noise amplifier (LNA) for ultra-wideband (UWB) radio is presented. The LNA is fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process. Measurement of the CMOS LNA is performed using an FR-4 PCB test fixture. From 3 to 6 GHz, the broadband LNA exhibits a noise figure of 4.7-6.7 dB, a gain of 13-16 dB, and an input/output return loss higher than 12/10 dB, respectively. The input P/sub 1 dB/ and input IP3 (IIP3) at 4.5 GHz are about -14 and -5 dBm, respectively. The DC supply is 1.8 V.     

Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p/sup -/silicon substrates

A 900-MHz single-pole double-throw (SPDT) switch with an insertion loss of 0.5 dB and a 2.4-GHz SPDT switch with an insertion loss of 0.8 dB were implemented using 3.3-V 0.35-/spl mu/m NMOS transistors in a 0.18-/spl mu/m bulk CMOS process utilizing 20-/spl Omega//spl middot/cm p/sup -/ substrates. Impedance transformation was used to reduce the source and load impedances seen by the switch to increase the power handling capability. SPDT switches with 30-/spl Omega/ impedance transformation networks exhibit 0.97-dB insertion loss and 24.3-dBm output P/sub 1dB/ when tuned for 900-MHz operation, and 1.10-dB insertion loss and 20.6-dBm output P/sub 1dB/ when tuned for 2.4-GHz operation. The 2.4-GHz switch is the first bulk CMOS switch which can be used for 802.11b wireless local area network applications.     

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to- ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area.     

A 18-pJ/Pulse OOK CMOS Transmitter for Multiband UWB Impulse Radio

This letter presents a new transmitter for multiband impulse radio ultra-wideband (IR-UWB) systems. The ultra low-power, low-complexity UWB transmitter operates over three 528-MHz subbands in 3-5 GHz band. It consists of an on-off keying (OOK) modulator and a pulse generator which is based on the ON/OFF switching operation of an LC oscillator. Measurements show a pulse duration of 3.5 ns and a spectrum that fully complies with the FCC spectral mask with more than 20 dB of sidelobe rejection. Implemented in 0.18-mum CMOS technology, the transmitter operates in burst mode and dissipates only 18 pJ of energy consumption per pulse. The transmitter is best suited for energy detection receivers.     

A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications

A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented. The proposed PLL can be employed as a building block for a frequency synthesizer which generates a seven-band hopping carrier for multiband orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) radio. To achieve fast loop settling, integer-N architecture that operates with 528-MHz reference frequency is implemented and a wideband active-loop filter is integrated. An improved phase-frequency detector (PFD) is proposed for faster loop settling. To reduce reference sidebands, a feedback circuit using replica bias is implemented in the charge pump. I/Q carriers are generated by two cross-coupled LC VCOs. The output current of the charge pump is controlled to compensate for the VCO gain nonlinearity and a programmable frequency divider (12/spl les/N/spl les/17) that reliably operates at 9 GHz is designed. Fabricated in 0.18-/spl mu/m CMOS technology, the PLL consumes 32 mA from a 1.8-V supply and achieves phase noise of -109.6dBc/Hz at 1-MHz offset and spurs of -52 dBc.     

A fully integrated SOC for 802.11b in 0.18-/spl mu/m CMOS

A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.     

A 32-GHz non-uniform distributed amplifier in 0.18-/spl mu/m CMOS

This letter presents a fully integrated distributed amplifier in a standard 0.18-/spl mu/m CMOS technology. By employing a nonuniform architecture for the synthetic transmission lines, the proposed distributed amplifier exhibits enhanced performance in terms of gain and bandwidth. Drawing a dc current of 45mA from a 2.2-V supply voltage, the fabricated circuit exhibits 9.5-dB pass-band gain with a bandwidth of 32GHz while maintaining good input and output return losses over the entire frequency band. With a compact layout technique, the chip size of the distributed amplifier including the testing pads is 940/spl times/860/spl mu/m/sup 2/.     

A novel bidirectional CMOS transceiver for chip-to-chip optical interconnects

A novel bidirectional complementary metal-oxide-semiconductor (CMOS) transceiver for chip-to-chip optical interconnects operating at 2.5 Gb/s is proposed, which shares the common block of a receiver and a transmitter on a single chip. The share of the common block of two circuits makes it possible to save 55% or 20% of power dissipation, depending on the operating mode. The chip in 0.18-/spl mu/m CMOS technology occupies an area of 0.82/spl times/0.82 mm/sup 2/, 70% of the total area of a typical unshared transceiver chip. The transmitting and receiving modes of operation show -3-dB bandwidths of 2.2 and 2.4 GHz and electrical isolations of -28 and -40 dB, respectively.     

A fully integrated low power PAM multi-channel UWB transmitter

A new transmitter for ultra-wideband (UWB) impulse radio is described in this paper. The new UWB transmitter implements a low power Gaussian shaping filter to reduce the side-lobe in the frequency domain. A simple pulse amplitude modulation (PAM) circuit is used to keep the power consumption low. The proposed architecture features the simple design, low-power operation, and enables the pulse-shape generation for a multi-channel UWB. The core layout size is only 0.2 mm². The simulation results show that the generated signals satisfy the FCC spectrum mask, and the average power consumption is <1.97 mW for the 1.8 V supply voltage. Pulses are transmitted at a PRF (pulse repetition frequency) of 40.5 MHz in 500 MHz bandwidth channels equally spaced within the 3.1–10.6 GHz UWB. This transmitter is designed and fabricated in a 0.18-μm CMOS process.     

Low-power ultra-wideband wavelets generator with fast start-up circuit

A low-power fully integrated ultra-wideband (UWB) wavelet generator is presented. This UWB generator is intended for low-power and low-complexity UWB radio technology using the noncoherent energy collection approach. The wavelet generator is based on a cross-coupled inductance-capacitance (LC) oscillator. It can be directly driven by two digital signals, which can modulate the length, position, and phase of the output wavelet. An additional digital circuit improves the startup time of the oscillator so that the oscillator and output buffers can be switched off between each wavelet generation. The entire chip-including output buffers-uses a 0.18-/spl mu/m CMOS technology. When operating at 10 megapulses per second (Mp/s) with a 1.2-GHz bandwidth wavelet, the generator provides a typical average output power of -20 dBm and consumes only 1.8 mW. The differential output signal is a multicycle waveform centered at 4.5 GHz.