Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests

We classify all path-delay faults of a combinational circuit intothree categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent} (ST-dependent). The classification uses anyunaltered single stuck-at fault test generation tool. Only two runsof this tool on a model network derived from the original network areperformed. As a by-product of this process, we generate single andmultiple input change delay tests for all testable faults. With thesetests, we expect that most defective circuits are identified. All STfaults are guaranteed detection in the case of a single fault, andsome may be guaranteed detection through robust and validatablenon-robust tests even in the case of multiple faults. An ST-dependentfault can affect the circuit speed only if certain ST faults arepresent. Thus, if all ST faults are tested, the ST-dependent faultsneed not be tested. MT faults cannot be guaranteed detection, butaffect the speed only if delay faults simultaneously exist on a setof paths, none of which is ST. Examples and results on several ISCAS89 benchmarks are presented. The method of classification throughtest generation using a model network is complex and can be appliedto circuits of moderate size. For larger circuits, alternativemethods will have to be explored in the future.     

On Selecting Testable Paths in Scan Designs

We propose an efficient method to select a minimal set of testable paths in scan designs, such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). The proposed path selection approach is based on a stepwise path expansion procedure that uses delay information and compact information about untestable paths to select longest paths while avoiding untestable paths. Techniques called delay analysis and delay-constrained path expansion are used to speedup the selection of paths to test. Compared to earlier approaches, the proposed approach is fast and it is guaranteed to find testable paths. Additionally the procedure also derives tests for the selected paths. Experimental results for ISCAS89 benchmark circuits using standard scan and broadside testing are presented to demonstrate the effectiveness of the proposed method.     

Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

Path delay fault model is the most suitable model for detectingdistributed manufacturing defects which can cause delayfaults. However, the number of paths in a modern design can beextremely large and the path delay testability of many practicaldesigns is very low. In this paper we show how to resynthesize acombinational circuit in order to reduce the total number of paths inthe circuit. Our results show that it is possible to obtain circuitswith a significant reduction in the number of paths while notincreasing area and/or delay of the longest sensitizable path in thecircuit.Research on path delay testing shows that in many circuits a largeportion of paths does not have a test that can guarantee detection ofa delay fault. The path delay testability of a circuit would increaseif the number of such paths is reduced. We show that addition of asmall number of test points into the circuit can help reducing thenumber of such paths in the given design.     

An advanced diagnostic method for delay faults in combinational faulty circuits

Due to physical defects or process variations, a logic circuit may fail to operate at the desired clock speed. So, verifying the timing behavior of digital circuits is always necessary, and needs to test for delay faults. When a delay fault has been detected, a specific diagnostic method is required to locate the site of the fault in the circuit. So, a reliable method for delay fault diagnosis is proposed in this paper. Firstly, we present the basic diagnostic method for delay faults, which is based on multivalued simulation and critical path tracing. Next, heuristics are given that decrease the number of critical paths and improve diagnosis results. In the second part of this paper, we provide an approximate method to refine the results obtained with the basic diagnostic process. We compute the detection threshold of the potential delay faults, and use statistical studies to classify the faults from the most likely to be the cause of failure to the less likely. Finally, results obtained with ISCAS'85 circuits are presented to show the effectiveness of the method.     

False-Path Removal Using Delay Fault Simulation

Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All segments of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a non-enumerative path delay fault simulator based on the path status graph (PSG) data-structure, which duplicates selected gates to separate the detected and undetected path delay faults. The expanded circuit may contain new redundant stuck-at faults, corresponding to those undetected paths that are false. This happens because the expanded circuit has some new interconnects with only false paths passing through them. Such links become the sites for redundant stuck-at faults. Removal of these redundant faults eliminates false paths. The reported results show that the quality of the result may depend on the coverage of testable paths by the vectors that are simulated. When non-enumerative path delay simulation and implication-based redundancy removal techniques are used, the present procedure of false-path elimination can be applied to very large circuits.     

Reduction of Number of Paths to be Tested in Delay Testing

Delay testing is important for high speed ICs. The main difficulty in delay testing comes from the huge number of paths and the large percentage of delay untestable paths. Therefore, it is critical to reduce the number of paths to be tested in delay testing. This paper presents two approaches to delay testing with significant reduction of number of paths to be tested, which provide high path delay fault coverage by testing a small number of paths. In the first approach, it is necessary to sample the primary output twice, one before and another after the transition for each test pair. The second approach is by means of accurate measurement of delays of very limited number of paths. In order to make this approach feasible, the paper also introduces a new concept of path sensitization, termed single-transition sensitization, to allow direct measurement of propagation delay of those paths. The paper presents how to select the very limited number of paths, termed sample paths, and how to generate test pairs and observation times for the sample paths for the first approach. On the other hand, it is noted for the second approach that under the analytical delay model (Proc. 9th International Conf. on VLSI Design, Bangalore, India, Jan. 1996, pp. 162–165), most of the paths are delay testable, which makes the accurate measurement approach feasible. In fact, it would be very difficult to select sample paths based on single path sensitization as it was done in (IEEE Trans. on Computers, Vol. c-29, No. 3, pp. 235–248, March 1980). The paper shows that the number of sample paths is linear to the number of gates in the circuit under test, despite exponential growth in the number of single paths.     

Hierarchical Delay Test Generation

Delay testing is used to detect timing errors in a digital circuit.In this paper, we report a tool called MODET forautomatic test generation for path delay faults in modular combinational circuits. Our technique usesprecomputed robust delay tests for individual modules to computerobust delay tests for the module-level circuit. We present alongest path theorem at the module level ofabstraction which specifies the requirements for path selectionduring delay testing. Based on this theorem, we propose a pathselection procedure in module-level circuits and report efficientalgorithms for delay test generation. MODET hasbeen tested against a number of hierarchical circuits with impressivespeedups in relation to gate-level test generation.     

双倍可变观测点的时滞测试

随着高速集成电路的发展,对时滞测试的研究越来越重要了,时滞测试的主要困难来自于与电路的门数成指数增长的庞大通路数,以及大量的时滞不可测通路。本文提供了一种使用双倍可变观测点进行时滞测试的方法,保证了只需要测试少量通路就能完成整个电路的时滞测试,它所付出的代价是：对每一个测试向量对,测试仪需要在原始输出采样两次以确定预期跳变的传输时间,此方法所需测试的通睡数与被测电路的门数成线性增长关系,从而很大程     

Delay Fault Coverage Enhancement Using Variable Observation Times

Detection of system timing failures has become a very importantproblem whenever high speed system operation is required. It has beendemonstrated that delay fault coverage loss could be significant if improperpropagation paths are used. This occurs when the delay test pair of a targetpropagation path cannot be effectively generated by an ATPG tool, or whenstuck-at test patterns are used as transition (or gate) delay test patterns.In this work, an efficient method is proposed to reduce the amount of faultcoverage loss by using variable observation times. The basic idea is tooffset the shorter propagation paths (really used) by tightening theobservation times. Given a probability distribution of defect sizes and aset of slack differences, this method is able to locate several observationtimes that result in small fault coverage loss.     

Efficient Path Selection for Delay Testing Based on Path Clustering

In this paper, we introduce a way of modeling the differences between the calculated delays and the real delays, and propose an efficient path selection method for path delay testing based on the model. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbances. In order to make precise judgment under this ambiguity, the delays of only the unshared segments of the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths.The experiments used the delays of gates and interconnects, which were calculated from the layout data of ISCAS85 benchmark circuits using a real cell library. Experimental results show the method selects only about one percent of the paths selected by the most popular method.     

Concurrent Delay Testing in Totally Self-Checking Systems

Prompt detection of even small delay faults, sometimes before causing critical paths to fail, gains importance since stricter test quality requirements for high performance and high density VLSI circuits have to be satisfied in critical applications. This can be achieved by using concurrent delay testing.In this paper a novel idea for concurrent detection of two-rail path delay faults is introduced. It is shown that TSC two-rail code error indicators that monitor pairs of paths with similar propagation delays can be used for concurrent delay testing. Our technique is applied to TSC two-rail code checkers as well as to duplication systems which are the most widely used TSC systems. The design of TSC two-rail code checkers and TSC duplication systems with respect to two-rail path delay faults is achieved for first time in the open literature.     

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficient algorithm is proposed to construct ORs for SOC based on a graph model. Experimental results on MCNC benchmark circuits have been included to show the effectiveness of the algorithm. In all experiments, the scheme achieves 100% fault coverage with a small number of tests.     

Cell delay fault testing for iterative logic arrays

C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only if an input transition can not be propagated to the cell's output through a path in the cell in a specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all the paths in a cell is first derived, and then necessary conditions for sending this test set to each cell in the array and simultaneously propagating the fault effects to the primary outputs are given. Test set minimization can be solved in a similar way as for the fault cover problem. We use the pipelined array multiplier as an example, and show that it is C-testable with 214 two-pattern tests. With a small number of additional patterns, all the combinational faults can be detected pseudoexhaustive.     

Scalable Delay Fault BIST for Use with Low-Cost ATE

We present a BIST architecture based on a Multi-Input Signature Register (MISR) expanding single input vectors into sequences, which are used for testing of delay faults. Input vectors can be stored on-chip or in the ATE; in the latter case, a low speed tester can be employed though the sequences are applied at-speed to the block-under-test. The number of input vectors (and thus the area demand on-chip or ATE memory requirements) can be traded for the test application time.We propose several methods for generating input vectors, which differ in test application time, area requirements and algorithm run-time. As all of them require only a two-pattern test as input, IP cores can be handled by these methods.The block-under-test can be switched off for some amount of time between application of consecutive input vectors. We provide arguments why this approach may be the only way to meet thermal and power constraints. Furthermore, we demonstrate how the BIST scheme can use these cool-down breaks for re-configuration.     

Detection of Delay Faults in Memory Address Decoders

In this paper we present an efficient test concept for detection of delay faults in memory address decoders based on the march test tactic. The proposed Transition Sequence Generator (TSG) generates an optimal transition sequence for sensitization of the delay faults in address decoders by Hayes's transformation on a reflected Gray code. It can be used for parallel Built-In Self-Testing (BIST) of high-density RAMs. We also present an efficient Design For Test (DFT) approach for immediate detection of the effects of the delay faults in the address decoders which does not change memory access time. It requires extra logic to be attached to the outputs of the address decoders. This DFT approach can be used to increase memory testability for both on-line and off-line testing of single- and multi-port RAMs.     

基于扫描的VLSI全速测试方法

当工艺进入到超深亚微米以下,传统的故障模型不再适用,必须对电路传输延迟引发的故障采用延迟故障模型进行全速测试.给出了常用的延迟故障模型,介绍了一种基于扫描的全速测试方法,并给出了全速测试中片上时钟控制器的电路实现方案.对芯片进行测试,可以直接利用片内锁相环电路输出的高速时钟对电路施加激励和捕获响应,而测试向量的扫描输入和响应扫描输出则可以采用测试机提供的低速时钟,从而降低了全速测试对测试机时钟频率的要求.最后,对于全速测试方案提出了若干建议.     

Controllability of Static CMOS Circuits for Timing Characterization

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

考虑串扰影响的时延测试

超深亚微米工艺下，串扰的出现会导致在电路设计验证、测试阶段出现严重的问题。本文介绍了一个基于波形敏化的串扰时延故障测试生成算法。该算法以临界通路上的串扰时延故障为目标故障进行测试产生．大大提高了算法的效率。实验表明，以该算法实现的系统可以在一个可接受的时间内。对一定规模的电路的串扰时延故障进行测试产生。     

An Efficient Rerouting Scheme for MPLS-Based Recovery and Its Performance Evaluation

The path recovery in MPLS is the technique to reroute traffic around a failure or congestion in a LSP. Currently, there are two kinds of model for path recovery: rerouting and protection switching. The existing schemes based on rerouting model have the disadvantage of more difficulty in handling node failures or concurrent node faults. Similarly, the existing schemes based on protection switching model have some difficulty in solving problem such as resource utilization and protection of recovery path. This paper proposes an efficient rerouting scheme to establish a LSP along the least-cost recovery path of all possible alternative paths that can be found on a working path, which is calculated by the upstream LSR that has detected a failure. The proposed scheme can increase resource utilization, establish a recovery path relatively fast, support almost all failure types such as link failures, node failures, failures on both a working path and its recovery path, and concurrent faults. Through simulation, the performance of the proposed scheme is measured and compared with the existing schemes.