Mechanism of hemispherical-grained Si formation for dynamic random access memory cells by rapid thermal chemical vapor deposition

An uneven coating made of hemispherical-grained Si (HSG) was formed on an amorphous Si layer by a rapid thermal chemical vapor deposition (CVD) (RTCVD) process. The uneven coating increases the effective surface area of a capacitor electrode in dynamic random access memory (DRAM) cells. The formation of the HSG consists of “seeding” and subsequent isothermal annealing stages. During the seeding stage, nanometer size Si single crystals are formed on the surface of the amorphous Si layer. During rapid thermal annealing at 665°C, under high vacuum, the Si grains grow linearly with increasing temperature and reach an average size of 95 nm after 20 sec. The nucleation and growth of the HSG occurs within a narrow range of temperature and time, which is sufficient for a short diffusion path of Si atoms on the surface of the amorphous Si layer, but insufficient for crystallization of the amorphous Si layer: The HSG coating increases the capacitance of a memory cell by a factor of 2.     

动态随机存储器中堆叠电容器结构的互连寄生电容模拟

在高密度比特位动态随机存储器(DRAM)芯片的发展中,随着多层布线与复杂存储单元结构的日渐普遍使用,互连寄生电容对存储器件性能如时延、功耗、噪声等的影响日渐突出,已成为不可忽视的重要因素,对互连寄生电容提取软件提出了紧迫的要求.本文介绍一个基于直接边界元素法的精度高,速度快,并可适应复杂堆叠(stacked)电容器结构的互连寄生电容模拟软件,并通过实例计算,分析DRAM中互连线寄生电容对电路性能的影响.     

An investigation of LPCVD and PECVD of in situ doped polycrystalline silicon for VLSI

In general, high-temperature processes cause thermal stresses and diffusion of dopants, resulting in reduced device yields. It is thus desirable to reduce the number of high-temperature steps and the use of an in situ doping technique eliminates one such step. In this investigation, low-pressure chemical vapour deposition (LPCVD) and plasma-enhanced chemical vapour deposition (PECVD) have been utilised to deposit in situ doped polycrystalline silicon films. The process characteristics and properties such as spreading resistance, grain structure, etch rate using a plasma and dopant concentrations of these films have been investigated and explained using a simple model for dopant activation and grain growth. It is shown that good-quality films suitable for VLSI can be produced.     

Optimization of the acid leaching process by using an ultrasonic field for metallurgical grade silicon

In the experiment, acid leaching under an ultrasonic field (20 kHz, 80 W) was used to remove Al, Fe, and Ti impurities in metallurgical grade silicon (MG-Si). The effects of the acid leaching process parameters, including the particle size of silicon, the acid type (HCl, HNO3, HF,) and the leaching time on the purification of MG-Si were investigated. The results show that HCl leaching, an initial size of 0.1 mm for the silicon particles, and 8 h of leaching time are the optimum parameters to purify MG-Si. The acid leaching process under an ultrasonic field is more effective than the acid leaching under magnetic stirring, the mechanism of which is preliminarily discussed.     

超声场下工业硅酸洗工艺优化

In the experiment, acid leaching under an ultrasonic field （20 kHz, 80 W） was used to remove AI, Fe, and Ti impurities in metallurgical grade silicon （MG-Si）. The effects of the acid leaching process parameters, including the particle size of silicon, the acid type （HC1, HNO3, HF,） and the leaching time on the purification of MG-Si were investigated. The results show that HC1 leaching, an initial size of 0.1 mm for the silicon particles, and 8 h of leaching time are the optimum parameters to purify MG-Si. The acid leaching process under an ultrasonic field is more effective than the acid leaching under magnetic stirring, the mechanism of which is preliminarily discussed.     

Optimization of n/i and i/p buffer layers in n-i-p hydrogenated microcrystalline silicon solar cells

Hydrogenated microcrystalline silicon (μc-Si:H) intrinsic films and solar cells with n-i-p configuration were prepared by plasma enhanced chemical vapor deposition (PECVD). The influence of n/i and i/p buffer layerson the μc-Si:H cell performance was studied in detail. The experimental results demonstrated that the efficiency is much improved when there is a higher crystallinity at n/i interface and an optimized a-Si:H buffer layer at i/p interface. By combining the above methods, the performance ofμc-Si:H single-junction and a-Si:H/μc-Si:H tandemsolar ceils has been significantly improved.     

Optimization of n/i and i/p buffer layers in n-i-p hydrogenated microcrystalline silicon solar cells

Hydrogenated microcrystalline silicon （μc-Si：H） intrinsic films and solar cells with n-i-p configuration were prepared by plasma enhanced chemical vapor deposition （PECVD）. The influence of n/i and i/p buffer layers on the μc-Si：H cell performance was studied in detail. The experimental results demonstrated that the efficiency is much improved when there is a higher crystallinity at n/i interface and an optimized a-Si：H buffer layer at i/p interface. By combining the above methods, the performance of μc-Si：H single-junction and a-Si：H/μc-Si：H tandem solar cells has been significantly improved.     

Observation of unequal densities for sulfur defects in silicon predeposited by low fluence ion implantation*

The dynathermal current and capacitance responses of two isotopes of sulfur, 32s and 34s predeposited by low fluence ion implantation into siliconp ⁺- n junction diodes are presented. As opposed to all previous studies, in this work unequal densities are seen for the shallow and deep sulfur defects, for both the 32_s− and 34₋ related defects. Additionally, the dynathermal response of the deep 34_s center is seen to exhibit a shift of 3 K from that of 32_S at a fixed heating rate of 9.5 ±0.1 K/s, consistent with the isotope dependence of the thermal emission process observed earlier for these cen-ters by isothermal capacitance measurements. The work was conducted as part of the Semiconductor Technology Program at NBS. Portions of this work were supported by the Division of Electric Energy Systems, Department of Energy (Task Order A021-EES), the Defense Advanced Research Projects Agency (Order No. 2397), and the NBS. Not subject to copyright. NBS-NRC Postdoctoral Research Associate.     

Dielectric characteristics of gamma irradiated Au/SnO2/n-Si/Au (MOS) capacitor

The dielectric characteristics of gamma irradiated Au/SnO₂/n-Si/Au (MOS) capacitor were studied. The MOS capacitor was irradiated by a ⁶⁰Co gamma radiation source with a dose rate of 0.69 kGy/h. The dielectric parameters such as dielectric constant (ε′), dielectric loss (ε″), loss factor (tan δ) and ac electrical conductivity (σ_ac) were calculated from the capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. It is found that the C and G/ω values decrease with the increasing total dose due to the irradiation-induced defects at the interface. Also, the calculated values of ε′, ε″ and σ_ac are found to decrease with an increased radiation dose. This result indicates that the dielectric characteristics of the MOS capacitor are sensitive to gamma-ray dose.     

硅片线锯砂浆中硅粉与碳化硅粉的泡沫浮选分离回收

以对碳化硅表面有选择性的脂肪酸作为捕收剂,采用泡沫浮选分离方法来分离回收硅片线锯砂浆中的和碳化硅粉。研究了捕收剂浓度、起泡剂浓度、浮选溶液的温度及pH值对分离效果的影响。当浮选溶液中捕收浓度为0.315mol/L,起泡剂浓度为0.18mol/L,温度为70℃,pH值为4.5时,分离效果最佳:浮起产物中碳化粉质量分数为99.3%,沉淀产物中硅粉质量分数为95.9%。     

Theoretical approach to estimate laser process parameters for drilling in crystalline silicon

This paper presents a simple method for estimating the ablation rate during drilling processes in crystalline silicon wafers. Using data from literature, the physical process of material heating, melting, and ejection can be estimated on a time scale and leads to a temporal separation of the pulse duration in two parts. The latter one offers a theoretical determination of the expected average ablation rate. The results of this approximation coincide with experimental values and offer solutions to increase drilling efficiency. The experiments were done with a q‐switched solid‐state laser emitting at 1064 nm wavelength at pulse durations between 810 ns and 1440 ns. Copyright © 2010 John Wiley & Sons, Ltd.     

利用多孔硅层增强P型CZ硅中吸杂效率的一种新方法

A new two-step phosphorous diffusion gettering(TSPDG) process using a sacrificial porous silicon layer(PSL) is proposed.Due to a decrease in high temperature time,the TSPDG(PSL) process weakens the deterioration in performances of PSL,and increases the capability of impurity clusters to dissolve and diffuse to the gettering regions.By means of the TSPDG(PSL) process under conditions of 900℃/60 min + 700℃/30 min,the effective lifetime of minority carriers in solar-grade(SOG) Si is increased to 14.3 times ...     

Optimisation of implantation conditions for the formation of buried SiO2 layers in silicon

The substrate temperature dependence of the IR transmission spectra of buried silicon dioxide layers formed by high dose ion implantation (~1017) was investigated for an ion dose ranging from 1017 to 1018 ions/cm2 at 250°C of 16O+ at 100 keV energy. The IR spectra indicate that the silicon/silicon-dioxide/silicon can be obtained after thermal annealing treatment of the implanted sample for 10 mm in hydrogen ambient at 1100°C.     

电解电容器铝箔横向隧道孔的生长控制

在酸性介质中已经产生隧道孔的铝箔表面,继续在中性电解液中采取直流阳极溶解时,隧道孔密度及长度与二次侵蚀时电解质类别相关。在此基础上,通过二次侵蚀前铝箔表面的酸浸泡成膜处理,以及二次侵蚀过程中在中性氯化钠介质中添加复合有机物,达到控制此过程中隧道孔生长方向的目的,使其在原隧道孔的孔壁沿着与铝箔表面平行的方向产生新的隧道孔,这为提高铝箔表面积提出了新的途径,为进一步提高铝电解电容器比容提供了可能性。     

铜镍共沉淀对直拉硅单晶中洁净区形成的影响

The influence of co-precipitation of copper and nickel on the formation of a denuded zone(DZ) in Czochralski silicon(Cz Si) was systematically investigated by means of etching and optical microscopy(OM).It was found that,for conventional high-low-high annealing(CFA),the DZ could be obtained in all specimens contaminated by copper and nickel co-impurity at different steps of the heat treatment,indicating that no copper precipitates or nickel precipitates were generated in the region just below the surface.However,for rapid thermal annealing(RTA)-low-high annealing,the tendency is not the same; the DZ could not be found in the specimen which was contaminated by copper and nickel contamination before the first RTA annealing.On the basis of the experimental results,it was supposed that the concentration and distribution of the vacancies generating during the RTA can influence the distribution of copper precipitation and nickel precipitation along the cross-section of Cz Si significantly,and thus influence the formation of the DZ to a great extent.     

Study of the high throughput flexographic process for silicon solar cell metallisation

A commercially available silver paste was modified to match the flexographic process requirements. Rotational and oscillatory rheological tests were carried out to assess the printability and spreading behaviour of the resulting inks. Then, a multifactorial approach was used on a laboratory‐scale printing press to adapt the flexographic process for the front side metallisation of Cz‐Si solar cells, especially for the seed layer deposit of two layer contacts. To quickly identify the significant process parameters, a fractional design of experiment based on a screening approach at two levels was performed. Afterwards, two full factorial designs of experiments were implemented. While the first one allows a better understanding of the effect of the main factors and interactions, the second allows a fine tuning and a confirmation of the first results. Additionally, this methodology allows corroborating the influence of the ink rheological properties on the printing results. Following the process study and optimisation, a seed layer with an average width of 25 µm was printed at a high 0.3 m/s throughput. Additional results suggest that the line width and the throughput can be further improved, which underlines the potential of flexography for photovoltaic applications. Finally, the light‐induced process was used to thicken the seed layer after a standard firing‐through step, leading to an encouraging 17.9% efficiency on Cz‐Si solar cells. Copyright © 2015 John Wiley & Sons, Ltd.     

Molecular dynamics study on the thickness of damage layer in multiple grinding of monocrystalline silicon

The molecular dynamic (MD) simulation of monocrystalline silicon under multiple grinding is carried out to study the effect of multiple grinding on the thickness of damage layer. Four grinding processes are conducted on (0 0 1) along 〈−1 0 0〉 direction. The depth of grinding of the first grinding is 20 Å. The subsequent grinding is machining on the machined surface with a damage layer left by the first grinding. The second grinding is a spark-out process and the depth of grinding of the third and fourth grinding increases by 5 Å compared with the previous grinding. The changes of structures and mechanical properties of the damage layer in the machined surface after the first grinding are investigated by coordination number (CN), the radial distribution functions (RDF) and nanoindentation. The thickness of the damage layer left by the first grinding can be reduced stably in the second and third grinding, but it will increase in the fourth grinding. Therefore, two more grinding steps between the third and fourth grinding are carried out. One is the spark-out process and the depth of grinding of the other increases by 2 Å compared with the third grinding. The results show the spark-out process can remove the springback left by the previous grinding and promote the residual compressive stress in the machined surface, which can improve the accuracy and quality of grinding. The thickness of damage layer induced by the first grinding can be reduced without new damage structures generating. However, it cannot be reduced unlimited. When the thickness of damage layer reaches half of the original thickness, a re-grinding will cause new damage structures, and the thickness of damage layer will increase. The depth of grinding is suggested to be less than half of the original damage thickness to reduce the damage layer. The research results can be applied in the ultra-precision grinding of monocrystalline silicon to control the thickness of damage layer and improve the quality of machining.     

变温LPCVD沉积氮化硅薄膜的均匀性优化

以低压化学气相沉积(LPCVD)热壁立式炉为实验平台,由二氯硅烷和氨通过LPCVD工艺合成氮化硅薄膜,利用降温成膜提高氮化硅薄膜的膜厚均匀度.基于气体碰撞理论建立了氮化硅薄膜沉积速率与反应气体浓度的关系式.分析比较了LPCVD炉内不同升温速率沉积氮化硅薄膜的表面性能.发现在变温沉积阶段,选择合适的降温速率是实现薄膜沉积...     

Formation of titanium and cobalt germanides on Si (100) using rapid thermal processing

Titanium and cobalt germanides have been formed on Si (100) substrates using rapid thermal processing. Germanium was deposited by rapid thermal chemical vapor deposition prior to metal evaporation. Solid phase reactions were then performed using rapid thermal annealing in either Ar or N₂ ambients. Germanide formation has been found to occur in a manner similar to the formation of corresponding silicides. The sheet resistance was found to be dependent on annealing ambient (Ar or N₂) for titanium germanide formation, but not for cobalt germanide formation. The resistivities of titanium and cobalt germanides were found to be 20 μΩ-cm and 35.3μΩ-cm, corresponding to TiGe₂ and Co₂Ge, respectively. During solid phase reactions of Ti with Ge, we have found that the Ti₆Ge₅ phase forms prior to TiGe₂. The TiGe₂ phase was found to form approximately at 800° C. Cobalt germanide formation was found to occur at relatively low temperatures (425° C); however, the stability of the material is poor at elevated temperatures.     

Analytical model for the effects of the variation of ferrolectric material parameters on the minimum subthreshold swing in negative capacitance capacitor

In this paper, we analytically study the relationship between the coercive field, remnant polarization and the thickness of a ferroelectric material, required for the minimum subthreshold swing in a negative capacitance capacitor. The interdependence of the ferroelectric material properties shown in this study is defined by the capacitance matching conditions in the subthreshold region in an NC capacitor. In this paper, we propose an analytical model to find the optimal ferroelectric thickness and channel doping to achieve a minimum subthreshold swing, due to a particular ferroelectric material. Our results have been validated against the numerical and experimental results already available in the literature. Furthermore, we obtain the minimum possible subthreshold swing for different ferroelectric materials used in the gate stack of an NC-FET in the context of a manufacturable semiconductor technology. Our results are presented in the form of a table, which shows the calculated channel doping, ferroelectric thickness and minimum subthreshold for five different ferroelectric materials.