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1.
文章首先对DVB-T系统的概念和应用进行了阐述,接着重点对其中的FFT模块进行研究.由于DVB-T系统存在2K/8K模式,为方便起见,我们选择采用2K模式进行FFT模块的设计与实现,包括算法实现、系统架构设计、FPGA实现、仿真.最后对仿真结果进行了分析. 相似文献
2.
Burt P.J. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2002,90(7):1188-1200
Real-time vision tasks such as autonomous driving require prodigious computing power yet practical vision systems need to be compact and low cost. I suggest that such systems can be partitioned into two computing stages, for "front-end processing" and "high-level interpretation," respectively, and that each of these stages can be implemented as a single integrated circuit or a small number of such circuits. The two stages differ in data representation and computing architecture: The front-end stage operates on sampled image data and its computations are performed on a processor optimized for signal level processing. The high-level stage operates on abstract and symbolic image data and its computations ate performed on a general-purpose microprocessor. In this paper I describe a "segmented pipeline" architecture for front-end processing and a chip level processor implementation. This vision front-end processor is designed to support early vision functions, such as feature enhancement and motion and stereo analysis, for a broad range of dynamic vision applications. The approach makes systematic use of a multiresolution pyramid framework to achieve high computational efficiency, robustness, and precision. 相似文献
3.
A 1-GS/s FFT/IFFT processor for UWB applications 总被引:1,自引:0,他引:1
Yu-Wei Lin Hsuan-Yu Liu Chen-Yi Lee 《Solid-State Circuits, IEEE Journal of》2005,40(8):1726-1735
In this paper, we present a novel 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed pipelined FFT architecture, called mixed-radix multipath delay feedback (MRMDF), can provide a higher throughput rate by using the multidata-path scheme. Furthermore, the hardware costs of memory and complex multipliers in MRMDF are only 38.9% and 44.8% of those in the known FFT processor by means of the delay feedback and the data scheduling approaches. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for the UWB system has been designed and fabricated using 0.18-/spl mu/m single-poly and six-metal CMOS process with a core area of 1.76/spl times/1.76 mm/sup 2/, including an FFT/IFFT processor and a test module. The throughput rate of this fabricated FFT processor is up to 1 Gsample/s while it consumes 175 mW. Power dissipation is 77.6 mW when its throughput rate meets UWB standard in which the FFT throughput rate is 409.6 Msample/s. 相似文献
4.
A VLSI array processor for 16-point FFT 总被引:1,自引:0,他引:1
Lee Moon-Key Shin Kyung-Wook Lee Jang-Kyu 《Solid-State Circuits, IEEE Journal of》1991,26(9):1286-1292
An implementation of a two-dimensional array processor for fast Fourier transform (FFT) using a 2-μm CMOS technology is presented. The array processor, which is dedicated to 16-point FFT, implements a 4×4 mesh array of 16 processing elements (PEs) working in parallel. Design considerations in both the chip level and the PE level are examined. A layout design methodology based on bit-slice units (BSUs) results in a very simple design, easy debugging, and a regular interconnection scheme through abutment. It contains about 48,000 transistors on an area of 53.52 mm2, excluding the 83-pad area, and operation is on a 15-MHz clock. The array processor performs 24.6 million complex multiplications per second, and computes a 16-point FFT in 3 μs 相似文献
5.
《Electronics letters》2008,44(25):1448-1450
A novel asymmetric fork-like monopole antenna for digital video broadcasting-terrestrial (DVB-T) signal reception for application in the UHF band is presented. The proposed antenna consists of two two-branch strip monopoles on a rectangular ground plane with a concave. The concavity in the ground pattern serves as an effective means for the gap between the radiating element and the ground plane for impedance matching. The influence of various parameters on antenna characteristics has been investigated. Results show a wide bandwidth of 461 MHz (451?912 MHz) or 70% of DVB-T centred frequency (655 MHz). The proposed antenna has omnidirectional radiation patterns in the yz-plane. Details of the proposed antenna design and experimental results of the constructed prototypes are presented. 相似文献
6.
A radix-8 wafer scale FFT processor 总被引:2,自引:0,他引:2
Earl E. Swartzlander Jr. Vijay K. Jain Hiroomi Hikawa 《The Journal of VLSI Signal Processing》1992,4(2-3):165-176
Wafer Scale Integration promises radical improvements in the performance of digital signal processing systems. This paper describes the design of a radix-8 systolic (pipeline) fast Fourier transform processor for implementation with wafer scale integration. By the use of the radix-8 FFT butterfly wafer that is currently under development, continuous data rates of 160 MSPS are anticipated for FFTs of up to 4096 points with 16-bit fixed point data. 相似文献
7.
Area-efficient FPGA-based FFT processor 总被引:5,自引:0,他引:5
A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the 'twiddle factors' sequentially leads to an area saving up to 35% with respect to other cores. 相似文献
8.
在基于正交频分复用(Orthogonal Frequency Division Multiplexing,OFDM)的无线系统中,快速傅里叶变换(Fast Fourier Transform,FFT)作为关键模块,消耗着大量的硬件资源。为此,针对于IEEE802. 11a标准的无线局域网基带技术,提出了一种低硬件开销、低功耗的基-24算法流水线架构FFT处理器设计方案。在硬件实现上,采用单路延迟负反馈(Single-path Delay Feedback,SDF)流水线架构;为了降低硬件资源消耗,基于新型的改良蝶形架构利用正则有符号数(Canonical Signed Digit,CSD)常数乘法器替代布斯乘法器完成所有的复数乘法运算。设计采用QUARTUS PRIME工具进行开发,搭配Cyclone 10 LP系列器件,编译结果显示该方案与其他已存在的方案相比,至少节约硬件成本25%,降低功耗18%。 相似文献
9.
10.
We propose a new VLSI architecture for an FFT processor. Our architecture uses few processing elements and can be laid out in a mesh-interconnected pattern. We show how to compute the discrete Fourier transform at n points with an optimal speed-up as long as the memory is large enough. The control is shown to be simple and easily implementable in VLSI. 相似文献
11.
Thakur Garima Sohal Harsh Jain Shruti 《Multidimensional Systems and Signal Processing》2021,32(3):1041-1063
Multidimensional Systems and Signal Processing - The Fast Fourier Transform (FFT) is the basic building block for DSP applications where high processing speed is the critical requirement. Resource... 相似文献
12.
本文通过对混合基4/2 FFT算法的分析,在优化采样数据、旋转因子存储及读取方法的基础上,提出了将N=2m点,m为奇、偶两种情况的地址产生统一于同一函数的算法,并设计了简单的插入值产生及快速插入位置控制电路,从而用一个计数器、同一套地址产生硬件,通过简单的开关模式控制,可实现任意长度FFT变换的地址产生单元,该地址产生单元在一个时钟周期内产生读取所需旋转因子及并行访存4个操作数的地址.本文设计的FFT处理器每周期完成一个基4或2个基2蝶式运算,在吞吐率高、资源少的基础上实现了处理长度可编程的灵活性,同时避免了旋转因子重复读取,降低功耗. 相似文献
13.
A novel method for reducing the number of equivalent complex multipliers for a multipath mixed-radix 128-point FFT processor using an advanced constant multiplier is proposed. 相似文献
14.
Quenot G.M. Gauvain J.-L. Gangolf J.-J. Mariani J.J. 《Solid-State Circuits, IEEE Journal of》1989,24(2):349-357
A dynamic programming processor with parallel and pipeline architecture is described. A 2-μm CMOS technology was applied to the DP processor, which is composed of 127309 transistors on a 7.17×8.62-mm2 die and is housed in an 84-pin PLCC (plastic leaded chip carrier) or PGA (pin grid array) package. The clock frequency is 20 MHz, and the instruction cycle time is 100 ns. Precise electrical simulations permitted the safe use of nonstandard logic and area and power reduction. Implementation of a direct access to all internal registers has proven useful for chip test and software development. A system using one DP processor has given very good results on a wide variety of applications and 0.48% error rate on tests with standard NATO tapes. These results are significantly better than those published for other systems on the same tests 相似文献
15.
A low-power, high-performance, 1024-point FFT processor 总被引:1,自引:0,他引:1
This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) processor. The 460000-transistor design has been fabricated in a standard 0.7 μm (Lpoly=0.6 μm) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 μs while consuming 9.5 mW, resulting in an adjusted energy efficiency more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate 相似文献
16.
Liang Yang Kewei Zhang Hongxia Liu Jin Huang Shitan Huang 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2006,53(7):585-589
The fast Fourier transform (FFT) is a very important algorithm in digital signal processing. The locally pipelined (LPPL) architecture is an efficient structure for FFT processor designing in a real-time embedded system. Two basic building blocks, to the LPPL FFT processor, the butterfly in pipeline, and address generating, are discussed in this brief. Based on the "deep" feedback to butterfly-2, a novel approach for pipelined architecture, the radix-2 single-path deep delay feedback architecture is proposed. For length-N discrete Fourier transform computation, the dominant hardware requirements are minimal for complex multipliers log/sub 4/N-1 and adders 2log/sub 4/N. As an integral need of the LPPL FFT processor design, address generating and coefficient store-load structures are also presented. 相似文献
17.
Sarmiento R. de Armas V. Lopez J.F. Montiel-Nelson J.A. Nunez A. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1998,6(1):18-30
In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 μm gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 μs, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors 相似文献
18.
《Solid-State Circuits, IEEE Journal of》1981,16(4):372-376
A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed. The processor, fabricated with the most advanced 3 /spl mu/m n-channel E/D MOS technology, incorporates a 16/spl times/16-bit full hardware multiplier and a sophisticated bus structure to minimize bus conflicts, thus attaining the capability to implement 55 second-order filters at a sampling rate of 8 kHz with sufficient dynamic range to process PCM encoded signals. The authors describe the design concept, architecture, instructions, device design, and application techniques. 相似文献
19.
Yamashita K. Kanasugi A. Hijiya S. Goto G. Matsumura N. Shirato T. 《Solid-State Circuits, IEEE Journal of》1988,23(2):336-342
The wafer-scale 170000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using a programmable contact-hole mask. The processor performs parallel 16-bit, eight-point complex FFTs and is implemented with 725 I/O pads in triple-metal 2.3-μm p-well CMOS technology on a 4-in. wafer. It is mounted by controlled-collapse bonding facedown on a 11.8×11.8-cm2 substrate 相似文献