Generalized Ramsey numbers through adiabatic quantum optimization

Ramsey theory is an active research area in combinatorics whose central theme is the emergence of order in large disordered structures, with Ramsey numbers marking the threshold at which this order first appears. For generalized Ramsey numbers r(G, H), the emergent order is characterized by graphs G and H. In this paper we: (i) present a quantum algorithm for computing generalized Ramsey numbers by reformulating the computation as a combinatorial optimization problem which is solved using adiabatic quantum optimization; and (ii) determine the Ramsey numbers \(r({\mathscr {T}}_{m},{\mathscr {T}}_{n})\) for trees of order \(m,n = 6,7,8\), most of which were previously unknown.     

A subgradient approach for constrained binary optimization via quantum adiabatic evolution

Quantum Information Processing - We propose a method to improve the performance of two-way continuous-variable quantum key distribution protocol by virtual photon subtraction. The virtual photon...     

Adapting the traveling salesman problem to an adiabatic quantum computer

We show how to guide a quantum computer to select an optimal tour for the traveling salesman. This is significant because it opens a rapid solution method for the wide range of applications of the traveling salesman problem, which include vehicle routing, job sequencing and data clustering.     

Generalized quantum partial adiabatic evolution

Due to the intrinsic similarity between partial adiabatic evolution and global adiabatic evolution, we generalize the partial adiabatic evolution proposed recently to its local adiabatic algorithm version. However, unlike that the local adiabatic evolution can speed up the global adiabatic algorithm quadratically, we prove that this new quantum algorithm presented here just has the same time complexity as the original partial adiabatic evolution. This may imply the optimality of the original partial adiabatic evolution or its generalized version. Additionally, a concrete example is given to further support our conclusion.     

Superblock-based performance optimization for Sunway Math Library on SW26010 many-core processor

The Journal of Supercomputing - The SW26010 many-core processor is based on the Sunway architecture that is composed of management and computing processing elements (MPE and CPE, respectively),...     

Toward quantum computation: a five-qubit quantum processor

Quantum physics presents intriguing possibilities for achieving computational gains after conventional miniaturization reaches its limits. Accordingly, we describe a nuclear magnetic-resonance quantum computer demonstrating a quantum algorithm that exponentially outperforms classical algorithms     

Differential geometric treewidth estimation in adiabatic quantum computation

The D-Wave adiabatic quantum computing platform is designed to solve a particular class of problems—the Quadratic Unconstrained Binary Optimization (QUBO) problems. Due to the particular “Chimera” physical architecture of the D-Wave chip, the logical problem graph at hand needs an extra process called minor embedding in order to be solvable on the D-Wave architecture. The latter problem is itself NP-hard. In this paper, we propose a novel polynomial-time approximation to the closely related treewidth based on the differential geometric concept of Ollivier–Ricci curvature. The latter runs in polynomial time and thus could significantly reduce the overall complexity of determining whether a QUBO problem is minor embeddable, and thus solvable on the D-Wave architecture.     

Partial adiabatic quantum search algorithm and its extensions

In this paper, we again discuss quantum search by partial adiabatic evolution, which was first proposed by Zhang et al. In contrast to previous conclusions, we show that partial adiabatic search does not improve the time complexity of a local adiabatic algorithm. Firstly, we show a variant of this algorithm and find that it is equivalent to the original partial adiabatic algorithm, in the sense of the same time complexity. But we give two alternate viewpoints on this “new” adiabatic algorithm—“global” adiabatic evolution and local adiabatic evolution approaches, respectively. Then, we discuss how global and local adiabatic quantum search can be recast in the framework of partial adiabatic search algorithm. It is found here that the former two algorithms could be considered as special cases of the later one when appropriately tuning the evolution interval of it. Also this implies the flexibility of quantum search based on partial adiabatic evolution.     

A study of heuristic guesses for adiabatic quantum computation

Adiabatic quantum computation (AQC) is a universal model for quantum computation which seeks to transform the initial ground state of a quantum system into a final ground state encoding the answer to a computational problem. AQC initial Hamiltonians conventionally have a uniform superposition as ground state. We diverge from this practice by introducing a simple form of heuristics: the ability to start the quantum evolution with a state which is a guess to the solution of the problem. With this goal in mind, we explain the viability of this approach and the needed modifications to the conventional AQC (CAQC) algorithm. By performing a numerical study on hard-to-satisfy 6 and 7 bit random instances of the satisfiability problem (3-SAT), we show how this heuristic approach is possible and we identify that the performance of the particular algorithm proposed is largely determined by the Hamming distance of the chosen initial guess state with respect to the solution. Besides the possibility of introducing educated guesses as initial states, the new strategy allows for the possibility of restarting a failed adiabatic process from the measured excited state as opposed to restarting from the full superposition of states as in CAQC. The outcome of the measurement can be used as a more refined guess state to restart the adiabatic evolution. This concatenated restart process is another heuristic that the CAQC strategy cannot capture.     

Mesoscale performance simulation of multicore processor systems

Modern microprocessor design relies heavily on detailed full-chip performance simulations to evaluate complex trade-offs. Typically, different design alternatives are tried out for a specific sub-system or component, while keeping the rest of the system unchanged. We observe that full-chip simulations for such studies is overkill. This paper introduces mesoscale simulation, which employs high-level modeling for the unchanged parts of a design and uses detailed cycle-accurate simulations for the components being modified. This combination of high-level and low-level modeling enables accuracy on par with detailed full-chip modeling while achieving much higher simulation speeds than detailed full-chip simulations. Consequently, mesoscale models can be used to quickly explore vast areas of the design space with high fidelity. We describe a proof-of-concept mesoscale implementation of the memory subsystem of the Cell/B.E. processor and discuss results from running various workloads.     

A performance analysis of Pentium processor systems

Using a CPI metric, we analyze the performance of Pentium-based systems and examine their use of the processor's architectural features under different software environments. We break down the CPI into its basic constituents and examine the effects of various operating systems and applications on the CPI. This analysis indicates where the application spends its time during execution, giving designers a better understanding of design tradeoffs and potential causes of performance bottlenecks     

Optimizing adiabatic quantum program compilation using a graph-theoretic framework

Adiabatic quantum computing has evolved in recent years from a theoretical field into an immensely practical area, a change partially sparked by D-Wave System’s quantum annealing hardware. These multimillion-dollar quantum annealers offer the potential to solve optimization problems millions of times faster than classical heuristics, prompting researchers at Google, NASA and Lockheed Martin to study how these computers can be applied to complex real-world problems such as NASA rover missions. Unfortunately, compiling (embedding) an optimization problem into the annealing hardware is itself a difficult optimization problem and a major bottleneck currently preventing widespread adoption. Additionally, while finding a single embedding is difficult, no generalized method is known for tuning embeddings to use minimal hardware resources. To address these barriers, we introduce a graph-theoretic framework for developing structured embedding algorithms. Using this framework, we introduce a biclique virtual hardware layer to provide a simplified interface to the physical hardware. Additionally, we exploit bipartite structure in quantum programs using odd cycle transversal (OCT) decompositions. By coupling an OCT-based embedding algorithm with new, generalized reduction methods, we develop a new baseline for embedding a wide range of optimization problems into fault-free D-Wave annealing hardware. To encourage the reuse and extension of these techniques, we provide an implementation of the framework and embedding algorithms.     

On the single processor performance of simple lattice Boltzmann kernels

This report presents a comprehensive survey of the effect of different data layouts on the single processor performance characteristics for the lattice Boltzmann method both for commodity “off-the-shelf” (COTS) architectures and tailored HPC systems, such as vector computers. We cover modern 64-bit processors ranging from IA32 compatible (Intel Xeon/Nocona, AMD Opteron), superscalar RISC (IBM Power4), IA64 (Intel Itanium 2) to classical vector (NEC SX6+) and novel vector (Cray X1) architectures. Combining different data layouts with architecture dependent optimization strategies we demonstrate that the optimal implementation strongly depends on the architecture used. In particular, the correct choice of the data layout could supersede complex cache-blocking techniques in our kernels. Furthermore our results demonstrate that vector systems can outperform COTS architectures by one order of magnitude.     

VLIW处理器ISA建模与辅助软件优化技术

在基于VLIW结构的分组密码专用处理器设计过程中,研究了VLIW处理器的指令集体系结构建模技术.设计了一个指令精确的指令集模拟器,通过附加一个流水线相关及停顿统计模块,实现了周期精确的程序运行统计和流水线停顿统计.结合指令集模拟器、汇编器以及调试器,设计了一个面向VLIW处理器的辅助程序优化环境.利用模拟器和调试器来评估程序的指令级并行度以及资源占用情况,辅助程序开发者优化VLIW处理器程序,从而达到软硬件协作开发VLIW处理器指令级并行性的最终目的.     

Real-time blind audio source separation: performance assessment on an advanced digital signal processor

Many on-line blind audio source separation (BASS) algorithms have been presented so far to the scientific community, but only a few of them have been evaluated in terms of their real-time performance. In this paper we consider a well-established BASS method (oriented to voices separation) evaluating its performance in terms of separation quality allowed by a real-time embedded computing implementation, also considering novel and state-of-the-art improvements to the it. To this aim, the algorithm has been implemented and ported for real-time execution onto an advanced low-power digital signal processor targeted for complex-domain applications. The optimized embedded implementation is able to perform up to five iterations of the gradient for any input frame of data, achieving good separation levels (up to 11.8 dB of signal to interference ratio on custom recording in real environments). The proposed solution doubles the performance of a C-optimized version running on a traditional PC processor, achieving a better separation result with lower power requirements.     

移动设备中异构处理器平台的能量优化设计

由于移动设备含有多个传感器,系统往往需要运行连续的感知任务。移动设备中的应用处理器能有效地运行计算密集型任务,而对于连续的感知任务将消耗大量的能量。为了提高移动设备的能量利用率,在包含应用处理器和低功耗处理器的异构处理器上提出了一种异构处理器平台能量优化方法。首先,根据处理器平台的实际能耗和理想能耗提出了能量比例因子。其次,提出了含有两个异构处理器平台的应用程序划分方法。最后,通过模拟器实验验证了该方法的有效性。模拟实验表明,由于将感知任务迁移到低功耗处理器上运行,所提出的优化方法能大大提高移动设备的能量利用效率。     

Accurately modeling superscalar processor performance with reduced trace

Trace-driven simulation of out-of-order superscalar processors is far from straightforward. The dynamic nature of out-of-order superscalar processors combined with the static nature of traces can lead to large inaccuracies in the results when the traces contain only a subset of executed instructions for trace reduction. In this paper, we describe and comprehensively evaluate the pairwise dependent cache miss model (PDCM), a framework for fast and accurate trace-driven simulation of out-of-order superscalar processors. The model determines how to treat a cache miss with respect to other cache misses recorded in the trace by dynamically reconstructing the reorder buffer state during simulation and honoring the dependencies between the trace items. Our experimental results demonstrate that a PDCM-based simulator produces highly accurate simulation results (less than 3% error) with fast simulation speeds (62.5× on average) compared with an execution-driven simulator. Moreover, we observed that the proposed simulation method is capable of preserving a processor’s dynamic off-core memory access behavior and accurately predicting the relative performance change when a processor’s low-level memory hierarchy parameters are changed.     

Adiabatic quantum optimization with qudits

Most realistic solid state devices considered as qubits are not true two-state systems. If the energy separation of the upper energy levels from the lowest two levels is not large, then these upper states may affect the evolution of the ground state over time and therefore cannot be neglected. In this work, we study the effect of energy levels beyond the lowest two energy levels on adiabatic quantum optimization in a device with a double-well potential as the basic logical element. We show that the extra levels can be modeled by adding additional ancilla qubits coupled to the original logical qubits, and that the presence of upper levels has no effect on the final ground state. We also study the influence of upper energy levels on the minimum gap for a set of 8-qubit spin glass instances.     

Minor-embedding in adiabatic quantum computation: II. Minor-universal graph design

In Choi (Quantum Inf Process, 7:193–209, 2008), we introduced the notion of minor-embedding in adiabatic quantum optimization. A minor-embedding of a graph G in a quantum hardware graph U is a subgraph of U such that G can be obtained from it by contracting edges. In this paper, we describe the intertwined adiabatic quantum architecture design problem, which is to construct a hardware graph U that satisfies all known physical constraints and, at the same time, permits an efficient minor-embedding algorithm. We illustrate an optimal complete-graph-minor hardware graph. Given a family F{\mathcal{F}} of graphs, a (host) graph U is called F{\mathcal{F}}-minor-universal if for each graph G in F, U{\mathcal{F}, U} contains a minor-embedding of G. The problem for designing a F{{\mathcal{F}}}-minor-universal hardware graph U _sparse in which F{{\mathcal{F}}} consists of a family of sparse graphs (e.g., bounded degree graphs) is open.