A 20 dBm Fully-Integrated 60 GHz SiGe Power Amplifier With Automatic Level Control

A + 20 dBm power amplifier (PA) for applications in the 60 GHz industrial scientific medical (ISM) band is presented. The PA is fabricated in a 0.13-mum SiGe BiCMOS process technology and features a fully-integrated on-chip RMS power detector for automatic level control (ALC), built-in self test and voltage standing wave ratio (VSWR) protection. The single-stage push-pull amplifier uses center-tapped microstrips for a highly efficient and compact layout with a core area of 0.075 mm². The PA can deliver up to 20 dBm, which to date, is the highest reported output power at mm-wave frequencies in silicon without the need for power combining. At 60 GHz it achieves a peak power gain of 18 dB, a 1-dB compression (P1dB) of 13.1 dBm, and a peak power-added efficiency (PAE) of 12.7%. The amplifier is programmable through a three-wire serial digital interface enabeling an adaptive bias control from a 4-V supply.     

60 G Hz 11 dBm CMOS功率放大器设计

近年来60 GHz附近的一个连续频段可以自由使用,这为短距离的无线个域网等高速率传输的应用提供了条件.设计了一个工作在60 GHz的CMOS功率放大器.采用台积电0.13μmRF-CMOS工艺设计制造,芯片面积为0.35mm × 0.4 mm,最大线性输出功率为11 dBm,增益为9.7 dB,漏极增加效率(η_(PAE))为9.1%.达到应用在通信距离为10 m的无线个域网(WPAN)射频电路中的要求.设计中采用了厚栅氧化层工艺器件和Load-Pull方法设计最优化输出阻抗z_(opt),以提高输出功率.该方法能较大提高CMOS功率放大器的输出功率,可以应用到各种CMOS功率放大器设计中.     

A Wideband Millimeter-Wave Power Amplifier With 20 dB Linear Power Gain and +8 dBm Maximum Saturated Output Power

A millimeter-wave power amplifier fabricated in 90 nm bulk CMOS technology consists of 3 identical cascode stages and on-chip matching networks (inter-stage, input, and output) implemented with wide-gap coplanar waveguides and M6-M5 (MIM) capacitors. The amplifier realizes a linear power gain of 19.7 dB at 52.4 GHz and 10.3 dB at 60 GHz. Maximum saturated output power and output-referred compression point are and 3.1 dBm, respectively. Peak PAE is 4.2%. The 1.180.96 die consumes 75 mA when operating from a 2 V supply.     

A GaN HEMT Class F Amplifier at 2 GHz With > 80% PAE

A Class F amplifier has been designed, fabricated, and tested using a GaN HEMT transistor and hybrid printed circuit board (PCB) packaging. The amplifier has a peak power-added efficiency (PAE) of 85% with an output power of 16.5 W. A gate-connected field-plated and a source-connected field-plated device of the same size and layout were measured in this topology. An output power and drain efficiency tradeoff, dependant on the drain impedance at the fundamental frequency due to the on-state resistance, is explored. A comparison between Class F and Inverse F, given particular operating conditions for this device, is made.     

A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

In this letter, a fully integrated 20-dBm RF power amplifier (PA) is presented using 0.25-mum-gate silicon-on-sapphire metal-oxide-semiconductor field-effect transistors (MOSFETs). To overcome the low breakdown voltage limit of MOSFETs, a stacked FET structure is employed, where transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the optimum load impedance for a 20-dBm PA increases to 50Omega, which is nine times higher than that of parallel FET topology for the same output power. Measurement of a single-stage linear PA shows small-signal gain of 17.1 dB and saturated output power of 21.0dBm with power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access modulated signal, the PA shows an average output power of 16.3 dBm and PAE of 18.7% with adjacent channel power ratio below -42dBc     

基于中和电容的60 GHz CMOS功率放大器设计

功率放大器（Power Amplifier, PA）是射频前端重要的模块,本文基于SMIC 55 nm RF CMOS 工艺,设计了一款60 GHz 两级差分功率放大器。针对毫米波频段下,硅基CMOS晶体管栅漏电容（Cgd）严重影响放大器的增益和稳定性的问题,采用交叉耦合电容中和技术抵消Cgd影响。通过优化级间匹配网络和有源器件参数,提高了功率放大器的输出功率,增益和效率。后仿结果显示,在1.2V的供电电压下,工作在60 GHz的功率放大器饱和输出功率为11.3 dBm,功率增益为16.2 dB,功率附加效率为17.0%,功耗为62 mW。芯片面积380×570 um2 。     

A 1.83 GHz 28.5 dBm CMOS Power Up-Mixer

A power up-mixer is proposed in this letter. A merged CMOS linear power amplifier (PA) and mixer allows low current consumption and smaller chip size than a conventional integrated transmitter including a mixer and a CMOS linear PA. The chip is fabricated in a 0.18 $mu{rm m}$ CMOS process and in an integrated-passive-device. Measurements show a drain efficiency of 27% at 27.2 dBm of 1 dB compression point (P1dB) output power from 1.75 to 1.95 GHz. Power conversion gain is 26.4 dB and LO leakage is $-$43 dBc.      

一种65 nm CMOS 60 GHz高增益功率放大器

设计了一种基于65 nm CMOS工艺的60 GHz功率放大器。采用共源共栅结构与电容中和共源级结构相结合的方式来提高功率放大器的增益,并采用两路差分结构来提高输出功率。采用片上变压器作为输入/输出匹配及级间匹配,以减小芯片的面积,从而降低成本。采用Cadence、ADS和Momentum等软件进行联合仿真。后仿真结果表明,在工作频段为60 GHz时,最大小信号增益为26 dB,最大功率附加效率为18.6%,饱和输出功率为15.2 dBm。该功率放大器具有高增益、高效率、低成本等优点。     

一种2~20 GHz超宽带高效率功率放大器

基于0.25 μm GaAs pHEMT工艺,设计了一种2~20 GHz的超宽带高效率功率放大器。该功率放大器采用非均匀分布式结构,可以为各级晶体管提供最佳负载阻抗。引入了漏极并联电容,以平衡输入与输出传输线的相速度,提高了输出功率和效率。在栅极引入了RC并联电路,能提高输入传输线的截止频率,保证电路稳定。仿真结果表明,在2~20 GHz的频带范围内,该功率放大器的增益为(10.7±1.2) dB,输入回波损耗小于-10 dB,饱和输出功率为28.8~29.7 dBm,功率附加效率(PAE)为33%~47%。     

6～20GHz宽带低噪声中功率放大器

本文介绍了６～２０ＧＨｚ微波宽带低噪声、中功率放大器的研制工作。采用微波宽带匹配和ＣＡＤ技术, 研制出了符合整机要求的放大器。主要性能指标： 工作频率６～２０ＧＨｚ, １ｄＢ压缩输出功率≥１８ｄＢｍ , 增益≥２８ｄＢ, 输入输出驻波比≤２．０∶１, 噪声系数≤４．０ｄＢ, 增益平坦度≤±２．０ｄＢ     

A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 $mu$m CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 802.16e signals.      

一种60 GHz CMOS高效率功率放大器

为了满足短距离无线高速传输的应用需求,基于SMIC 90 nm 1P9M CMOS工艺,设计了一种可工作在60 GHz的功率放大器(PA)。该PA为单端三级级联结构。采用顶层金属方法,设计具有高品质因子的小感值螺旋电感,用于输入、输出和级间匹配电路,以提高电路的整体性能。通过减少传输损耗和输出匹配损耗,提高了附加功率效率。仿真结果表明,在1.2 V电源电压下,该PA的功率增益为17.2 dB,1 dB压缩点的输出功率为8.1 dBm,饱和输出功率为12.1 dBm,峰值功率附加效率为15.7%,直流功耗为70 mW。各性能指标均满足60 GHz通信系统的要求。     

1.95GHz Doherty功率放大器设计

基于SMIC 0.18 μm RF CMOS工艺,设计了一款1.95 GHz的Doherty功率放大器.为了保持两路功放相位最大一致性,主功放(PA1)和辅功放(PA2)采用了同一种CMOS功率放大器,仅改变其偏压使其工作在不同模式.CMOS功率放大器为工作于AB类的两级放大电路,集成了输入和级间匹配网络;功分器以及λ...     

A 30 GHz Variable Gain Amplifier With High Output Voltage Swing for Ultra-Wideband Radar

This paper reports on the analysis, design and characterization of a 30 GHz fully differential variable gain amplifier for ultra-wideband radar systems. The circuit consists of a variable gain differential stage, which is fed by two cascaded emitter followers. Capacitive degeneration and inductive peaking are used to enhance bandwidth. The maximum differential gain is 11.5 dB with ${pm}1.5$ dB gain flatness in the desired frequency range. The amplifier gain can be regulated from 0 dB up to 11.5 dB. The circuit exhibits an output 1 dB compression point of 12 dBm. The measured differential output voltage swing is 1.23 V$_{pp}$ . The 0.75 mm$^2$ broadband amplifier consumes 560 mW at a supply voltage of ${pm}3.3$ V. It is manufactured in a low-cost 0.25 $mu$ m SiGe BiCMOS technology with a cut-off frequency of 75 GHz. The experimental results agree very well with the simulated response. A figure of merit has been proposed for comparing the amplifier performance to previously reported works.      

A monolithic transformer coupled 5-W silicon power amplifier with59% PAE at 0.9 GHz

This paper presents the circuit design and application of a monolithically integrated silicon radio-frequency power amplifier for 0.8-1 GHz. The chip is fabricated in a 25-GHz-f_T silicon bipolar production technology (Siemens B6HF). A maximum output power of 5 W and maximum efficiency of 59% is achieved. The chip is operating from 2.5 to 4.5 V. The linear gain is 36 dB. The balanced two-stage circuit design is based fundamentally on three on-chip transformers. The driver stage and the output stage are connected in common-emitter configuration. The input signal can be applied balanced or single-ended if one input terminal is grounded. One transformer at the input acts as balun as well as input matching network. Two transformers acts as interstage matching network     

一种饱和功率为21dBm，峰值效率为35%的应用于900MHz RFID阅读器的CMOS线性功率放大器

本文在CMOS 0.18μm Mixed Signal工艺上实现了工作于900MHz的两级差分线性功率放大器,该功放工作于class AB状态。本文探讨了低压下输出匹配和谐波抑制网络,以提高功放的输出功率及效率,降低输出谐波。测试结果表明,在1.8V的电源电压下,功放在900MHz频率的输出饱和功率达到21.1dBm,输出1dB压缩点的功率为18.4dBm,峰值功率增加效率为35.4%,功率增益为23.3dB,各谐波分量也得到很好的控制。两级功放加上PAD的芯片总面积为1.2×0.55mm2。通过单芯片测试以及基于原型机的测试结果表明,该功放可以满足UHF RFID阅读器的应用。     

2.45 GHz高线性功率放大器设计

基于SMIC 0.18 μm RF-CMOS工艺,实现了一种工作于2.45 GHz的功率放大器,给出了电路仿真结果和电路版图.电路采用两级放大的结构,分别采用自偏置技术和电阻并联负反馈网络来缓解CMOS器件低击穿电压的限制,同时保证了稳定性的要求.为了提高线性度,采用一种集成的二极管线性化电路对有源器件的输入电容变化提供一种补偿机制,漏端的LC谐振网络和优化的栅偏置用来消除由跨导产生的非线性谐波.在3 V电源电压下,放大器功率增益为23 dB,输出1 dB压缩点约为25 dBm,对应的功率附加效率PAE可达35%.     

A +31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications

A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky lambda/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8times3.2mm² including all pads and bypass capacitors     

A 900 MHz,21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

A two-stage differential linear power amplifier(PA) fabricated by 0.18μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power,efficiency and harmonic performance.Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency(PAE) is 35.4%,the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled.The total area with ESD protected PAD is 1.2×0.55 mm~2.Sy...