Court says that a party can't evade arbitration because its adversary is a nonsignatory

A federal appeals court decision exposes a circuit split on the law involving arbitration for parties that haven't signed an arbitration agreement. Also: details on Miami's mediation calendar girls.     

A multistage hierarchical distributed arbitration technique for priority-based real-time communication systems

ISO 11898 is a communication protocol based on the carrier sense multiple access with collision detection and arbitration on message priority (CSMA/CD+AMP) technique, which at present is largely used as a real-time network for industrial environments. Unfortunately, because of the peculiarities of the arbitration technique it adopts, it suffers from severe limitations on the maximum extension of the network, which cannot be overcome simply by means of improvements in the transceiver's technology as they depend on the limited propagation speed of the signals on the communication support. In this paper, a new kind of network is presented that features a behavior very similar to ISO 11898, but which achieves noticeably larger areas to be covered without having to reduce the bit rate. It relies on a tree topology and adopts a brand new multistage hierarchical distributed arbitration technique, which takes the increased propagation delays into account properly.     

Optimizing uplink TCP-ACK transmission in WiMAZ OFDMA systems

In WiMAX networks, a bandwidth request-grant process is required for uplink operation. However, the process is not optimized for TCP, since the uplink ACK stream is disrupted due to the following: (a) The process consists of several stages which in turn introduce big transmission delay; and (b) it requires additional uplink bandwidth which is significant compared to the ACK packet size. In this paper, the authors propose a new ACK transmission scheme, where ACK packets are combined with a bandwidth request (BR) header. Through simulation, it is demonstrated that the proposed scheme reduces the overheads of TCP-ACK transmissions effectively.     

CMOS design of the tree arbiter element

An asynchronous arbiter dynamically allocates a resource in response to requests from processes. Glitch-free operation when two requests arrive concurrently is possible in MOS technologies. Multiway arbitration using a request-grant-release-acknowledge protocol can be achieved by connecting together two-way arbiters (mutual exclusion and tree arbiter elements). We have devised a fast and compact design for the tree arbiter element which offers eager forward-propagation of requests. It compares favorably with a well-known design in which request propagation must wait for arbitration to complete. Our analysis and simulations also suggest that no performance improvement will be obtained by incorporating eager acknowledgment of releases. All of the designs considered in this paper are speed-independent, a formal property of a network of elements which can be taken as a positive indication of their robustness     

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25-μm CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V     

A programmable NMOS DRAM controller for microcomputer systems with dual-port memory and error checking and correction

An NMOS DRAM controller for use in microcomputer systems based on the iAPX-86 and iAPX-286 microprocessor families or on the Multibus system bus is described. The controller provides complete support for dual-port memories and memories with error checking and correction. The controller has programmable attributes for configuring it to the particular requirements of the system. The controller uses parallel arbitration to minimize arbitration delay. A memory cycle will start on the same clock edge that samples a command if the cycle has been previously enabled. Novel logic and circuit design techniques have been used to achieve 16 MHz operation, 20 ns input setup time, and 35 ns output delay time.     

An advanced SEU tolerant latch based on error detection

This paper proposes a latch that can mitigate SEUs via an error detection circuit.The error detection circuit is hardened by a C-element and a stacked PMOS.In the hold state,a particle strikes the latch or the error detection circuit may cause a fault logic state of the circuit.The error detection circuit can detect the upset node in the latch and the fault output will be corrected.The upset node in the error detection circuit can be corrected by the Celement.The power dissipation and propagation delay of the proposed latch are analyzed by HSPICE simulations.The proposed latch consumes about 77.5％ less energy and 33.1％ less propagation delay than the triple modular redundancy (TMR) latch.Simulation results demonstrate that the proposed latch can mitigate SEU effectively.     

Analysis of resonant tunneling using the equivalenttransmission-line model

Presents a simple general and exact method for solving resonant tunneling problems in multilayered heterostructures. This method is based on the analogy of wave propagation between the transmission line and the potential structure. By using the proposed method, it is shown that electron wave propagation can be treated as wave propagation on an equivalent circuit and that various problems can be systematically solved by using well-developed circuit functions and circuit matrixes. In particular, our equivalent circuit can be effectively used for analysis of resonant interband tunneling (RIT) structures and resonant tunneling structures including Γ-X mixing by using the interface matrix. Various properties of the resonant tunneling structure and a guideline for designing new quantum effect devices can be easily obtained. In order to show the validity and usefulness of this method, some numerical examples of InAs-GaSb and GaAs-AlAs potential barrier structures are presented     

Negative capacitance bus terminator for improving the switching speed of a microcomputer databus

The data transfer speed of a microcomputer bus can be improved by adding an active circuit to the bus. This active circuit amplifies the bus voltage and feeds back to the bus a current which is proportional to the time rate of change of the bus voltage. This circuit effectively adds a negative capacitance to the bus. The practical capacitance canceling capability is limited by the propagation delay time of the operational amplifier in the active circuit. The theory of microcomputer bus structures with negative capacitance including effects of amplifier delay is presented. Typically, an operational amplifier with propagation delay less than one tenth of the bus time constant is required to achieve significant (factor of 2) bus speed improvement. High performance operational amplifiers were used to construct a working model of the negative capacitance bus terminator. The experimental results agree well with the theory.     

Design of a CMOS buffered switch for a Gigabit ATM switchingnetwork

This paper presents the implementation and design of a gigabit ATM Switch element used in a broadcast ATM switching network supporting 600 Mb/s link rates. The system is designed to operate at the clock speed of 100 MHz. The design of the switch element is developed to fabricate prototype chips using 1.2 μ CMOS VLSI technology. The network is constructed with a 256-port Benes topology and the switch element consists of nine identical data slices, and a global controller. Each data slice uses 48 shared buffers. The controller determines which buffer cells are to be sent to the outputs based on its internal contention resolution process. This process is carried out by an arbitration circuit and the decision is made by a buffer control circuit. The controller also generates grant flow control through the network     

Distributed arbitration scheme for on-chip CDMA bus with dynamic codeword assignment

Several code-division multiple access (CDMA)-based interconnect schemes have been recently proposed as alternatives to the conventional time-division multiplexing bus in multicore systems-on-chip. CDMA systems with a dynamic assignment of spreading codewords are particularly attractive because of their potential for higher bandwidth efficiency compared with the systems in which the codewords are statically assigned to processing elements. In this paper, we propose a novel distributed arbitration scheme for dynamic CDMA-bus-based systems, which solves the complexity and scalability issues associated with commonly used centralized arbitration schemes. The proposed arbitration unit is decomposed into multiple simple arbitration elements, which are connected in a ring. The arbitration ring implements a token-passing algorithm, which both resolves destination conflicts and assigns the codewords to processing elements. Simulation results show that the throughput reduction in an optimally configured dynamic CDMA bus due to arbitration-related overheads does not exceed 5%.     

Considerations on Customer Access to the ISDN

A concept for a digital customer access to an integrated services digital network (ISDN) is proposed. It is based on a passive bus which conveys information by means of two circuit switched B channels and aDchannel to support associated signaling (outslot channel) dynamically multiplexed with slow speed packetized data and telemetry. The customer access can support multiple terminal arrangements with simultaneously active users. Information to be conveyed by theDchannel is transferred in the form of messages, each associated with a logical link which has to coexist with other logical links on the common physicalDchannel. Access to that channel is regulated by level 1 arbitration with collision avoidance. It is possible to connect one X.25 DTE with minimum adaptation to the customer installation.     

Wanlass's CMOS circuit

The invention of complementary-MOS (CMOS) logic circuitry by Frank Wanlass in 1963 is recounted. The difficulties encountered by Wanlass in an attempt to make stable silicon MOSFETs and how they led him to the CMOS circuit are described. The first demonstration circuit, a two-transistor inverter, consumed just a few nanowatts of standby power and exhibited propagation delay times on the order of 100 ns     

TCP-Aware Uplink Scheduling for IEEE 802.16

In IEEE 802.16 networks, a bandwidth request-grant mechanism is used to accommodate various QoS requirements of heterogeneous traffic. However, it may not be effective for TCP flows since (a) there is no strict QoS requirement in TCP traffic; and (b) it is difficult to estimate the amount of required bandwidth due to dynamic changes of the sending rate. In this letter, we propose a new uplink scheduling scheme for best-effort TCP traffic in IEEE 802.16 networks. The proposed scheme does not need any bandwidth request process for allocation. Instead, it estimates the amount of bandwidth required for a flow based on its current sending rate. Through simulation, we show that the proposed scheme is effective to allocate bandwidth for TCP flows     

签密的仲裁安全与仲裁安全的签密方案

签密能高效地同时完成数据加密与认证,可用于设计紧凑的安全通信协议.签密中的仲裁机制用于保护签密的不可抵赖性,但同时用于仲裁的信息可能危及协议安全.本文指出签密仲裁中存在仲裁者解密攻击和仲裁机制无法保护明文完整性两种安全隐患,归纳其原因并指出解决方法.提出一个可安全仲裁的安全混合签密方案SASC,并在随机预言机模型下证明SASC方案具有IND-CCA2和UF-CMA安全性;SASC基于明文仲裁,不仅能维护明完整性而且能抵抗仲裁者解密攻击.SASC方案不增加计算量和通信量,且对明文的长度没有限制.     

基于FIFO队列的PCI总线仲裁器的设计与FPGA实现

系统地论述了PCI总线的仲裁机制和常用仲裁协议,简要地分析了常用仲裁协议的优缺点,并在此基础上介绍了一种基于循环优先级仲裁协议和FIFO队列相结合的PCI总线仲裁器的实现方法,旨在解决目前PCI总线仲裁协议中由于优先级循环出现的特权插队问题,并详细说明了基于循环优先级仲裁协议与FIFO队列相结合的总线仲裁器的设计和FPGA硬件实现。     

一款嵌入式芯片总线仲裁器的设计和评估

针对片上系统(SoC)总线设计中仲裁机制的选取往往局限于抽象的定性分析,以一款嵌入式处理器芯片为设计平台,实现了固定优先级、轮转优先级和混合优先级的仲裁电路设计,并建立了仿真测试平台,通过仿真对总线主设备的总线占有率、最差等待响应时间进行了定量分析比较,得出了混合优先级仲裁机制较单一的固定优先级与轮转优先级仲裁机制在体现公平性与优先性上更有效的结论,对其他嵌入式系统总线的仲裁设计与改进提供了很好的参考.     

High-Frequency Propagation on Printed Circuit Board Using a Material With a Low Dielectric Constant, a Low Dielectric Loss, and a Flat Surface

For the next-generation printed circuit boards with a fine pattern, low power consumption and high-speed propagation with low variation of signal propagation must be satisfied. In order to meet such requirements, we investigated a dielectric material for printed circuit boards which has three superior features: low dielectric constant (permittivity), low dielectric loss, and a flat surface with sufficient adhesion force for plating metal. The propagation loss of a microstrip line on the developed material is about 40% of the conventional material at 10 GHz. Significant reduction of the manufacturing fluctuation of the developed materials is achieved due to the flat surface. We adopted a distributed constant model to the propagation results and revealed that the significant reduction of the propagation loss is caused by the flat surface and low dielectric loss. This technology greatly contributes to the next generation of printed circuit boards.      

脉冲神经网络硬件互连系统的动态优先级仲裁策略

本文基于EMBRACE脉冲神经网络硬件实现方案提出了一种片上网络路由器的动态优先级仲裁策略,来解决脉冲神经网络脉冲传输的交通负载非均衡问题.该方案使用二维网格片上网络系统实现神经元之间的互连通讯,其基于脉冲发送频率的动态优先级仲裁策略能够降低高频路径的平均延迟及系统丢包风险,提高系统工作稳定性.使用Noxim片上网络模拟器搭建实验平台,测试结果表明采用提出的动态优先级仲裁策略较轮询及固定优先级仲裁器,高频路径延迟平均降低32.33%和34.69%,降低幅度最大达到84.86%和86.20%.在90nm CMOS工艺下,提出的路由器架构硬件面积为213,471μm²,具有较好的扩展性.     

Loss reduction in a coplanar waveguide on a planar lightwavecircuit (PLC) platform by quenching

The hybrid integration of semiconductor optoelectronic devices on a silica-based optical circuit is one of the key technologies by which to realize opto-electronic components for high-speed wavelength division multiplexing (WDM). However, a coplanar waveguide (CPW) on a silicon-terraced silica (STS)-type planar lightwave circuit (PLC)-platform has a large propagation loss compared with one on a conventional ceramic substrate. We discuss the reduction of the propagation loss of a CPW on a PLC-platform. First we prove that this CPW loss originates from an increase of the loss tangent (tan δ) induced by the thermal donors (TD's) which connect with oxygen in the silicon substrate during the silica deposition process. Second we introduce quenching to eliminate the TD's, and drastically reduce the loss of a CPW on a 30 μm-thick silica from 2.7 to 0.6 dB/cm at 10 GHz. This loss value is almost the same as that of a CPW on a ceramic substrate. Moreover we fabricated a LD module using a 50 mm-long improved CPW on a PLC-platform. The small signal frequency response characteristics of this module reveal that the improved CPW can be applied as a cm-order electrical circuit in a 10 Gb/s module. This exhibits that an established electronic circuit technology including a multi-chip module (MCM) for a microwave application can be developed on a PLC-platform