A simple systematic spiral inductor design with perfected Q improvement for CMOS RFIC application

In this paper, a systematic design procedure based on key factor analysis of the Q curve has been proposed. In addition to inductor design, we also present a technique that combines optimized shielding poly, and proton implantation treatment is utilized to improve the inductor Q value. The shielding effect of poly-silicon and the semi-insulating characteristics of proton-bombarded substrate have added a 37% and 54% increment to the Q value of the inductors, respectively. The combination of the two means has created a multiplication of their individual contribution rather than addition. The dramatic improvement of the Q value resulted from the doping level and film thickness optimization of a poly shield layer combined with a proton implantation treatment. A phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. This technique shall become a critical measure to put inductors on a silicon substrate with satisfactory performance for Si-based RF integrated-circuit applications     

Improved performance of Si-based spiral inductors

Conventional spiral inductors on silicon wafer have suffered low quality (Q) factor due to substrate loss. In this work, a technique that combines optimized shielding poly and proton implantation treatment is utilized to improve inductor Q-value. The optimized poly-silicon and proton-bombarded substrate have added 37% and 54% increment to the Q-value of inductors, respectively. If two techniques are combined, a phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. The combination of the two means has created a multiplication of their individual contribution rather than addition. The technique used in this work shall become a critical measure to put inductors on silicon substrate with satisfactory performance for Si-based radio frequency integrated circuit applications.     

High-Q factor three-dimensional inductors

In this paper, the great flexibility of three-dimensional (3-D) monolithic-microwave integrated-circuit technology is used to improve the performance of on-chip inductors. A novel topology for high-Q factor spiral inductor that can be implemented in a single or multilevel configuration is proposed. Several inductors were fabricated on either silicon substrate (/spl rho/ = 30 /spl Omega/ /spl middot/ cm) or semi-insulating gallium-arsenide substrate demonstrating, more particularly, for GaAs technology, the interest of the multilevel configuration. A 1.38-nH double-level 3-D inductor formed on an Si substrate exhibits a very high peak Q factor of 52.8 at 13.6 GHz and a self-resonant frequency as high as 24.7 GHz. Our 4.9-nH double-level GaAs 3-D inductor achieves a peak Q factor of 35.9 at 4.7 GHz and a self-resonant frequency of 8 GHz. For each technology, the performance limits of the proposed inductors in terms of quality factor are discussed. Guidelines for the optimum design of 3-D inductors are provided for Si and GaAs technologies.     

A broad-band lumped element analytic model incorporating skin effect and substrate loss for inductors and inductor like components for silicon technology performance assessment and RFIC design

We present a broad-band lumped element planar inductor model that is suitable for RFIC design in silicon technologies. We provide extensions of the modeling methodology to similar components such as differential inductors, baluns, and solenoid inductors. The analytic computation of the physics-based model components, incorporating both metal skin effect and substrate loss, is described. The model is validated using measured data from over 200 inductors made with five different silicon back-end process technologies. The physics-based implementation of the model allows its use for determining the optimum process technology characteristics for specific radio frequency integrated circuit (RFIC) designs. The analytical based implementation with lumped elements enables effective integration into a robust CAD system for efficient design of RFIC circuits.     

Accurate Analytical Spiral Inductor Modeling Techniques for Efficient Design Space Exploration

Efficient modeling techniques are required to accelerate design space exploration for integrated spiral inductors. In this letter, closed-form modeling techniques for the inductor's physical inductance and substrate eddy currents are introduced. The model provides several orders of magnitude performance improvement over field-solver-based approaches with typical errors of less than 4% while demonstrating excellent agreement with measured data from fabricated inductors     

陶瓷基板上的集成微电感模型与制作

对陶瓷基板上的集成微电感模型进行了分析.由于陶瓷基板的介电常数比Si基板低,电阻率极高,因此衬底损耗大大减小,从而有效提高了电感的Q值.同时,为了更好进行对比,研究中采用相同工艺在陶瓷基板和Si基板上同批制作了集成电感,两者的结构参数完全一致.测试结果表明,两者的电感值L基本相同,然而陶瓷基板上集成微电感Q值的峰值要比Si基板集成微电感高7左右,Si基板上Q值峰值在5 GHz以下,而陶瓷基板集成微电感的Q值峰值在10 GHz左右.     

The detailed analysis of high Q CMOS-compatible microwave spiralinductors in silicon technology

We present the extensive experimental results and their detailed analysis showing the important effects of layout parameters on the frequency responses of quality factor (Q) of rectangular spiral inductors, which are fabricated on a silicon substrate by using conventional silicon CMOS technology, in order to determine the desirable values of layout parameters for designing the high Q inductors used in RF IC's applications. Analysis of the inductors on Si substrates with three kinds of resistivities has been performed by tailoring the geometric layout and varying the metal thickness. Using these results, the substrate effects on RF performance of inductors are also investigated by observing the frequency responses of Q with varying the substrate resistivity in detail     

RF flip-module BGA package

We recently described a flip-chip package with integrated thin-film inductors and capacitors in a VCO tank circuit of a single chip GSM transceiver integrated circuit (IC). By embedding the passive components in a Si-on-Si substrate, we eliminated spurious resonances that were caused by the parasitics of the original 64-TQFP IC package. However, compared with the bare die, the resultant Si-on-Si structure is larger in all dimensions due to the inclusion of a flip-chip mounted transceiver IC and a surface-mount varactor. We have developed a novel BGA package structure with a hole milled in the center to accommodate the silicon-on-silicon assembly. The interconnections rely exclusively on flip-chip solder technology. To verify that the package does not degrade the performance of the RF circuits, we have performed electromagnetic field simulations to extract critical inductance and capacitance parameters. Parasitic inductances of the original TQFP and the new packages are comparable due to their similar dimensions. None the less, a major advantage of the new package structure is that it permits the integration of key passive components inside the package where they are unaffected by package parasitic impedances     

Design of integrated low noise amplifiers (LNA) using embedded passives in organic substrates

The noise figure of a low noise amplifier (LNA) is a function of the quality factor of its inductors. The lack of high-Q inductors in silicon has prevented the development of completely integrated complementary metal oxide semiconductor (CMOS) LNAs for high sensitivity applications like global system for mobile communications (GSM) (1.9 GHz) and wideband code-division multiple-access (W-CDMA) (2.1GHz). Recent developments in the design of high-Q inductors (embedded in low cost integrated circuit (IC) packages) have made single-package integration of RF front-ends feasible. These embedded passives provide a viable alternative to using discrete elements or low-Q on-chip passives, for achieving completely integrated solutions. Compared to on-chip inductors with low Q values and discrete passives with fixed Q/sub s/, the use of these embedded passives also leads to the development of the passive Q as a new variable in circuit design. However, higher Q values also result in new tradeoffs, particularly with respect to device size. This paper presents a novel optimization strategy for the design of completely integrated CMOS LNAs using embedded passives. The tradeoff of higher inductor size for higher Q has been adopted into the LNA design methodology. The paper also presents design issues involved in the use of multiple embedded components in the packaging substrate, particularly with reference to mutual coupling between the passives and reference ground layout.     

Q-factor definition and evaluation for spiral inductors fabricated using wafer-level CSP technology

A novel Q-factor definition and evaluation method are proposed for low-loss high-Q spiral inductors fabricated by using the wafer-level chip-size package (WLP) on silicon substrates, where the copper wiring technology with a polyimide isolation layer is used. In conventional Q-factor evaluation for inductors, a short-circuited load condition is used, where the Q factor is represented by using Y-parameters as Q=Im{1/Y/sub 11/}/Re{1/Y/sub 11/}. This conventional method provides a Q factor of 20 with 2-5-nH inductance around 3.9 GHz. However, since structures for the spiral inductors are asymmetrical, the short-circuited load condition and short-circuited source condition give different Q values, respectively. The Q-value differences of approximately 100% have often been observed in the WLP. The differences mainly come from differences in loss estimation. In a novel method, a complex conjugate impedance-matching condition is retained both at an input port and an output port of the inductor. The maximum available power gain (G/sub AMAX/) is introduced to evaluate the energy loss in one cycle. This condition provides a unique insertion loss of passive devices. Thus, the difference of the Q factor depends only on the difference of magnetic and electric energy. The difference of the Q value is reduced.     

Integrated RF architectures in fully-organic SOP technology

Future wireless communications systems require better performance, lower cost, and compact RF front-end footprint. The RF front-end module development and its level of integration are, thus, continuous challenges. In most of the presently used microwave integrated circuit technologies, it is difficult to integrate the passives efficiently with required quality. Another critical obstacle in the design of passive components, which occupy the highest percentage of integrated circuit and circuit board real estate, includes the effort to reduce the module size. These issues can be addressed with multilayer substrate technology. A multilayer organic (MLO)-based process offers the potential as the next generation technology of choice for electronic packaging. It uses a cost effective process, while offering design flexibility and optimized integration due to its multilayer topology. We present the design, model, and measurement data of RF-microwave multilayer transitions and integrated passives implemented in a MLO system on package (SOP) technology. Compact, high Q inductors, and embedded filter designs for wireless module applications are demonstrated for the first time in this technology.     

Analysis, design, and optimization of spiral inductors andtransformers for Si RF ICs

Silicon integrated circuit spiral inductors and transformers are analyzed using electromagnetic analysis. With appropriate approximations, the calculations are reduced to electrostatic and magnetostatic calculations. The important effects of substrate loss are included in the analysis. Classic circuit analysis and network analysis techniques are used to derive two-port parameters from the circuits. From two-port measurements, low-order, frequency-independent lumped circuits are used to model the physical behavior over a broad-frequency range. The analysis is applied to traditional square and polygon inductors and transformer structures as well as to multilayer metal structures and coupled inductors. A custom computer-aided-design tool called ASITIC is described, which is used for the analysis, design, and optimization of these structures. Measurements taken over a frequency range from 100 MHz to 5 GHz show good agreement with theory     

片上螺旋电感集总模型中衬底因子的分析与拟合

石英、高阻SOI、高阻硅等衬底上实现的电感具有比低电阻率衬底的电感更优的高频性能,因而研究基于不同衬底的电感性能,并在高频模型中进行精确的衬底因子表征就显得十分重要.综合考虑高频下的趋肤效应和邻近效应及衬底电磁损耗对电感性能的影响,实现了片上螺旋电感的集总元件模型,并通过与SOI、石英衬底的电感仿真参数及高阻硅衬底的电感测试参数进行了模型验证,结果表明,该模型拟合的S参数及Q值曲线能与仿真及测试结果吻合,同时模型中衬底因子的提取值与衬底性质相符合,因而该模型适用于片上电感的模拟与设计.     

Design of Wide Tuning-Range CMOS VCOs Using Switched Coupled-Inductors

Two designs of voltage-controlled oscillators (VCOs) with mutually coupled and switched inductors are presented in this paper to demonstrate that the tuning range of an LC VCO can be improved with only a small increase in phase noise and die area in a standard digital CMOS process. Particular attention is given to the layout of the inductors to maintain Q across the tuning range. In addition, different capacitive coarse-tuning methods are compared based on simulated and measured data obtained from test structures. Implemented in a 90 nm digital CMOS process, a VCO with two extra coupled inductors achieves a 61.9% tuning range with an 11.75 GHz center frequency while dissipating 7.7 mW from a 1.2 V supply. This VCO has a measured phase noise of -106 dBc/Hz at 1 MHz offset from the center frequency resulting in a higher figure-of-merit than other recently published VCOs with similar operating frequencies. In addition, the area overhead is only 30% compared to a conventional LC VCO with a single inductor.     

Improvement of the quality factor of RF integrated inductors bylayout optimization

A systematic method to improve the quality (Q) factor of RF integrated inductors is presented in this paper. The proposed method is based on the layout optimization to minimize the series resistance of the inductor coil, taking into account both ohmic losses, due to conduction currents, and magnetically induced losses, due to eddy currents. The technique is particularly useful when applied to inductors in which the fabrication process includes integration substrate removal. However, it is also applicable to inductors on low-loss substrates. The method optimizes the width of the metal strip for each turn of the inductor coil, leading to a variable strip-width layout. The optimization procedure has been successfully applied to the design of square spiral inductors in a silicon-based multichip-module technology, complemented with silicon micromachining postprocessing. The obtained experimental results corroborate the validity of the proposed method. A Q factor of about 17 have been obtained for a 35-nH inductor at 1.5 GHz, with Q values higher than 40 predicted for a 20-nH inductor working at 3.5 GHz. The latter is up to a 60% better than the best results for a single strip-width inductor working at the same frequency     

Self-assembling MEMS variable and fixed RF inductors

Inductors play a key role in wireless front-end circuitry, yet are not generally well suited for conventional RF integrated-circuit (RFIC) fabrication processes. We have developed inductors that can be fabricated on a conventional RFIC silicon substrate, which use warping members to assemble themselves away from the substrate to improve quality factor (Q) and self-resonance frequency (SRF), and to provide a degree of variation in inductance value. These self-assembling variable inductors are realized through foundry provided microelectromechanical systems (MEMS) processing and have demonstrated temperature stable Q values greater than 13, SRF values well above 15 GHz, and inductance variations greater than 18%. Simulations suggest the potential for Q values above 20 and inductance variations greater than 30%, with optimized processing     

Analysis of on-chip spiral inductors using the distributed capacitance model

In this paper, a distributed capacitance model (DCM) for monolithic spiral inductors is developed to predict the equivalent coupling capacitances C/sub p/ between the two terminals and the equivalent capacitance between the metal track and the substrate C/sub sub/. Therefore, the characteristics of inductors such as the S parameter, the quality factor Q, and the self-resonant frequency f/sub SR/ can be predicted by its series inductance, equivalent capacitances, and series resistance. A large number of inductors have been implemented in 0.25- and 0.35-/spl mu/m CMOS processes to demonstrate the prediction accuracy. For planar and multilayer inductors, DCM can provide a quick and accurate assessment to the design of monolithic spiral inductors.     

有关QFN72和CQFN72的热阻计算

文章介绍了QFN72和CQFN72结到外壳的等效热路分析及结到外壳热阻θJC的简化计算方法,结果表明原设计下CQFN72的热阻约为1.25 K·W-1,几乎是QFN72的一倍。优化CQFN热设计的主要途径是适当减薄陶瓷基板厚度、在陶瓷基板中嵌入钨柱阵列、芯片减薄和采用金基焊料焊接等。从CQFN热设计考虑,不应在主散热区热沉下采用4J29或4J42焊接垫片,否则会使热阻θJC增大10%以上。     

Characteristic Variation of 3‐D Solenoid Embedded Inductors for Wireless Communication Systems

The characteristic variation of 3‐dimensional (3‐D) solenoid‐type embedded inductors is investigated. Four different structures of a 3‐D inductor are fabricated by using a low‐temperature co‐fired ceramic (LTCC) process, and their s‐parameters are measured between 50 MHz and 5 GHz. The circuit model parameters of each building block are optimized and extracted using the partial element equivalent circuit method and an HSPICE circuit simulator. Based on the model parameters, the characteristics of the test structures such as self‐resonant frequency, inductance, and quality (Q) factor are analyzed, and predictive modeling is applied to the structures composed of a combination of the modeled building blocks. In addition, characteristic variations of the 3‐D inductors with different structures using extracted building blocks are also investigated. This approach can provide a characteristic estimation of 3‐D solenoid embedded inductors for structural variations.     

适用于高品质射频集成电感的多孔硅新型衬底制备技术

提出了背向选区腐蚀生长多孔硅的集成电感衬底结构．ASITIC模拟证明，该新型衬底结构的集成电感在高频下仍具有较高的品质因子．采用此工艺，在固定腐蚀液配比的条件下，变化电流密度和阳极氧化时间,制备出了高质量的厚膜多孔硅，并测量了多孔硅的生长厚度、孔径大小和表面形貌，得出了多孔硅生长速率随阳极氧化时间和电流密度的变化关系，为背向选区腐蚀工艺制备高品质硅基集成电感奠定了理论和实验基础．