Ku-band 16×16 planar array with aperture-coupledmicrostrip-patch elements

The design and development of a Ku-band linearly polarized 16×16 microstrip-patch array is presented. The array is fed by a corporate network, using dog-bone shaped coupling apertures. Thin substrates and low-loss foam are used for antenna-bandwidth enhancement. The design of the radiating patches and feed network was aided by the commercial software package, Ensemble(R). Experimental results for the array, in terms of its return loss, radiation pattern, and gain, are presented     

A Monolithic Dual 16-Bit D/A Converter

A monolithic dual high-speed 16-bit D/A converter is described. In the binary weighted current network a dynamic current divider is used to obtain the required high accuracy of the six most significant bits without any adjustment procedure or trimming technique. To construct the ten least significant bits a new approach is used to construct the passive divider stage based on emitter sealing of transistors. As the bit switches are optimized for fast-settling and low-glitch current, both converters can be used without extra sample-and-hold or deglitcher circuitry at sampling frequencies up to 200 kHz. The converter has a differential linearity of 0.5 LSB over a temperature range of -20 to +70/spl deg/ C. The high linearity of the converter results in a distortion of 0.001 percent over the audio band. The chip is processed in a standard bipolar process and the die size is 3.8 X 5.5 mm/sup 2/.     

A Millimeter-Wave (40–45 GHz) 16-Element Phased-Array Transmitter in 0.18-$mu$ m SiGe BiCMOS Technology

This paper demonstrates a 16-element phased-array transmitter in a standard 0.18-mum SiGe BiCMOS technology for Q-band satellite applications. The transmitter array is based on the all-RF architecture with 4-bit RF phase shifters and a corporate-feed network. A 1:2 active divider and two 1:8 passive tee-junction dividers constitute the corporate-feed network, and three-dimensional shielded transmission-lines are used for the passive divider to minimize area. All signals are processed differentially inside the chip except for the input and output interfaces. The phased-array transmitter results in a 12.5 dB of average power gain per channel at 42.5 GHz with a 3-dB gain bandwidth of 39.9-45.6 GHz. The RMS gain variation is < 1.3 dB and the RMS phase variation is < for all 4-bit phase states at 35-50 GHz. The measured input and output return losses are < -10 dB at 36.6-50 GHz, and <-10 dB at 37.6-50 GHz, respectively. The measured peak-to-peak group delay variation is plusmn 20 ps at 40-45 GHz. The output P_-1dB is -5plusmn1.5 dBm and the maximum saturated output power is - 2.5plusmn1.5 dBm per channel at 42.5 GHz. The transmitter shows <1.8 dB of RMS gain mismatch and < 7deg of RMS phase mismatch between the 16 different channels over all phase states. A - 30 dB worst-case port-to-port coupling is measured between adjacent channels at 30-50 GHz, and the measured RMS gain and phase disturbances due to the inter-channel coupling are < 0.15 dB and < 1deg, respectively, at 35-50 GHz. All measurements are obtained without any on-chip calibration. The chip consumes 720 mA from a 5 V supply voltage and the chip size is 2.6times3.2 mm².     

16 QAM Modulation for High Capacity Digital Radio System

A computational method allowing the calculation of bit error rate in the presence of filtering and some other impairments is described for 16 QAM modulation; a breadboard working at a bit rate of 140 Mbits/s has been implemented and experimental results are compared with calculated values. The possible use of this modulation type for a high capacity digital radio-relay system is considered. Some parameters are introduced for this purpose, especially the net fade margin parameter. In the case of the 140 Mbit/s system in the 10.7-11.7 GHz frequency band, 4 PSK and 8 PSK modulation types are compared with 16 QAM. System gain, frequency arrangement, nodal capacity and outage performances are evaluated.     

Integrated CCD transversal filter matched to a pair of 16-bit complementary series

An integrated filter matched to a pair of 16-bit complementary series was fabricated employing four buried channel CCDs with parallel-in/serial-out approach for high speed operation. This letter presents the structure and operation of the filter and demonstrates various advantages, such as negligible deviation (0.016%) from expected signal-to-noise power gain, high peak-to-sidelobe ratio     

A complete high-speed voltage output 16-bit monolithic DAC

A new single-chip 16-bit monolithic digital/analog converter (DAC) with on-chip voltage reference and operational amplifiers has achieved /spl plusmn/0.0015% linearity, 10 ppm//spl deg/C gain drift, and 4-/spl mu/s settling time. Novel elements of the 16-bit DAC include: the fast settling open-loop reference with a buried Zener, a fast-settling output operational amplifier without the use of feedforward compensation, and a modified R-2R ladder network. Thermal considerations played a significant role in the design. The DAC is fabricated using a 20-V process to reduce device sizes and therefore die size. All laser trimming including temperature drift compensation is performed at the wafer level. The converter does not require external components for operation.     

A 3.8-ns CMOS 16×16-b multiplier using complementarypass-transistor logic

A 3.8-ns, 257-mW, 16×16-b CMOS multiplier with a supply voltage of 4 V is described. A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality. Its multiplication time is the fastest ever reported, even for bipolar and GaAs ICs, and it can be enhanced further to 2.6 ns with 60 mW at 77 K     

A high gain frequency convertor using field-effect transistors

A frequency convertor capable of converting to frequencies above and below the input frequency is described. The circuit's operation is based on the parametric action of a matched differential field effect transistor pair in conjunction with a positive feedback network. The main advantages of the circuit are high conversion gain and non-harmonically related output frequencies.     

X波段双层16单元正方形径向线螺旋子阵的设计

矩形径向线螺旋子阵的设计是高功率高增益径向线螺旋阵列天线研究的基础,提出并设计了一个X波段双层16单元正方形径向线螺旋子阵,阐述了子阵的工作原理,简要介绍了X波段的辐射单元和耦合探针,重点分析了双层径向线馈电系统,从而得到了一个X波段的子阵模型,并对其进行了数值模拟,结果表明该子阵在8.6～10.1GHz的频带范围内,天线反射系数小于0.1,在9.0～10.0GHz的频带范围内,天线增益大于18.45dB,副瓣电平小于-11.68dB,轴比值小于1.66。     

Low loss and high extinction ratio strictly nonblocking 16×16thermooptic matrix switch on 6-in wafer using silica-based planarlightwave circuit technology

We describe a silica-based 16×16 strictly nonblocking thermooptic matrix switch with a low loss and a high extinction ratio. This matrix switch, which employs a double Mach-Zehnder interferometer (MZI) switching unit and a matrix arrangement to reduce the total waveguide length, is fabricated with 0.75% refractive index difference waveguides on a 6-in silicon wafer using silica-based planar lightwave circuit (PLC) technology. We obtained an average insertion loss of 6.6 dB and an average extinction ratio of 53 dB in the worst polarization case. The operating wavelength bandwidth completely covers the gain band of practical erbium-doped fiber amplifiers (EDFAs). The total power consumption needed for operation is reduced to 17 W by employing a phase-trimming technique which eliminates the phase-error in the interferometer switching unit     

8～16GHzGaAs单片宽带分布放大器

报道了８～１６ＧＨｚＧａＡｓ单片宽带分布放大器的设计与制作。单级ＭＭＩＣ电路采用三个栅宽为２８０μｍ的ＧａＡｓＭＥＳＦＥＴ作为有源器件，芯片尺寸为１．１ｍｍ×１．６ｍｍ。在８～１６ＧＨｚ频率范围，用管壳封装的两级级联放大器增益Ｇ＿ａ，为１１．３±１ｄＢ，噪声系数Ｆ＿ｎ＜６ｄＢ，输出功率Ｐ＿（１ｄＢ）＞１６ｄＢｍ。     

Performance of erbium-doped fibre amplifier in 16-channel coherent broadcast network

The performance of an erbium-doped fibre amplifier in a 16-channel coherent broadcast network operating at 155 Mbit/s has been experimentally investigated. A fibre-to-fibre gain of 22 dB at 1540 nm allowed simulation of a network that serves 256 end-users over a distance of 102 km.<>     

一种基于连通矩阵的Link16网络设计方法

Link16是美军为适应联合作战的需求而研制的新型数据链,技术上,Link16采用了时分多址的接入方式,使用之前需要进行网络设计,即根据作战计划为网络中的每个平台预先分配适合通信需求的发射时隙和中继时隙等参数。网络设计是Link16应用的开始和关键,详细讨论了Link16的网络设计,给出了网络设计需求,并基于缺省连通矩阵,提出了一种简单、灵活的网络设计方法。该方法既能设计出满足通用信息交换需求的Link16网络,也能通过修改缺省连通矩阵,设计出满足特定作战需求的Link16网络,具有较强的实用价值。     

2 Gbit/s, 16*16 expandable high-speed space-division-switch LSI using SST

A Si bipolar 2 Gbit/s 16*16 high-speed space-division-switch LSI is described. High-speed operation of 2 Gbit/s and low-power dissipation of 2.8 W are achieved by adopting a new expandable structure, a very low voltage swing-differential bipolar circuit design and a super self-aligned process technology (SST-1A). This LSI is applicable to future B-ISDN HDTV switching systems.<>     

SIW 耦合馈电阵列天线

提出一种新型宽带、结构紧凑的基片集成波导(SIW)背腔阵列天线的设计方法。所设计的SIW 阵列由紧密相连的背腔构成馈电网络,每个背腔上开宽缝作为辐射单元。SIW 背腔天线单元紧密排列,主要通过单元间感性耦合窗耦合馈电。SIW 背腔既是辐射单元又能实现能量分配,不需加载额外的馈电网络,因此该阵列结构十分紧凑。工作在20 GHz 频段的2×2 SIW 耦合馈电阵和4×4 SIW 耦合馈电阵已加工实现,仿真和测试结果表明所提出的SIW阵列设计方法简单、阵列结构紧凑、天线辐射性能良好。另外,本文研究了高增益大规模阵列天线的组阵方法。在2×2 SIW 耦合馈电阵的基础上,采用8×8 SIW 并联馈电网络加载天线子阵的方法设计了16×16 宽带高增益SIW 阵列天线并进行了加工测试。结果表明,采用这种组阵方法,天线阵阵元排布紧密,天线具有带宽宽、增益高、损耗低等优点。     

Investigation of Transients in Single-Fiber Bidirectional Closed-Loop WDM Ring Network Using High-Power Gain Clamped EDWA

We investigate a transparent WDM ring network design immune to accumulated power transients where simultaneous bidirectional operation is achieved on a single fiber. This allows cost effectiveness, flexible traffic re-routing, and network operation. We demonstrate that add/drop of 15 out of 16 channels generate negligible $({≪ 0.15}~{hbox {dB}})$ power excursion on the surviving channel. These results have been obtained by using new high-gain erbium-doped waveguide amplifiers in an innovative gain-clamped configuration that allows bidirectional operation. The glass-on-silicon waveguide optical amplifiers are able to achieve a clamped flat gain of 15 dB on full C-band with up to 0-dBm input power. This is the highest output power ever reported for an erbium-doped waveguide amplifier. The amplifier can with almost identical performance operate with signals entering together from both ends or even from opposite ends. The gain properties of the amplifier are almost perfectly symmetric.      

A Large 16*16 IF Analog Switch Matrix for Personal Communications Satellites

A 16 input and 16 output channels single chip intermediate frequency range (160 MHz) analog switch matrix for personal communication satellites has been designed and processed by using a commercial 1.2 µm BiCMOS technology. The circuit has low power consumption (,2W) and low insertion loss with maximum output power of 0 dBm.     

合成孔径雷达中的二维自动增益控制

该文给出一种合成孔径雷达接收机自动增益控制(AGC)的方法,该方法对合成孔径雷达信号 进行二维平均,既保持了信号的原有特性,又提高了接收机的动态范围。与传统的自动增益控制方法相比,它能更好地消除短时间内的干扰以及保留合成孔径雷达图像中的对比度。该文在对二维AGC工作方式及时间参数选择进行阐述之后,给出了二维AGC的计算机仿真结果以及雷达实际使用AGC后获得的图像。     

A CMOS stereo 16-bit D/A converter for digital audio

A complete monolithic stereo 16-bit D/A converter primarily intended for use in compact-disc players and digital audio tape recorders is described. The D/A converter achieves 16-bit resolution by using a code-conversion technique based upon oversampling and noise shaping. The band-limiting filters required for waveform smoothing and out-of-band noise reduction are included. Owing to the oversampling principle most applications will require only a few components for an analog postfilter. The converter has a linear characteristic and linear phase response. The chip is processed in a 2-/spl mu/m CMOS process and the die size is 44 mm/SUP 2/. Only a single 5-V supply is needed.