Suspended SOI structure for advanced 0.1-μm CMOS RF devices

Modern silicon-on-insulator (SOI) technology and 0.1-μm-channel-length complementary metal oxide silicon (CMOS) devices make it possible to fabricate high-performance RF devices by using standard Si ULSI processes. Using the buried oxide layer of an SOI wafer as an etching stopper, we were able to integrate a suspended inductor, with high-inductor resonance-frequency of 19.6 GHz, and high-performance 0.1-μm CMOS devices. Moreover, we experimentally show that this suspended CMOS has acceptable short-channel immunity. Using two-dimensional (2-D) simulation, we clarify that the gate-potential spread sufficiently suppresses the potential shifts, which results in good short-channel characteristics     

Potential design and transport property of 0.1-μm MOSFET withasymmetric channel profile

This paper describes potential design and transport property of a 0.1-μm n-MOSFET with asymmetric channel profile, which is formed by the tilt-angle ion-implantation after gate electrode formation. The relation between device performance and transport property of the asymmetric 0.1-μm device is explored by Monte Carlo simulations, and measured electrical characteristics. The self-consistent Monte Carlo device simulation coupled with a process simulator reveals higher electron velocity at the source end of the channel and velocity overshoot at the source side of the channel, and the smaller high-energy tail of the distribution in the drain. This transport property creates high drain current, large transconductance, and low substrate current of the 0.1-μm n-MOSFET with asymmetric channel profile     

Exploration of velocity overshoot in a high-performance deepsub-0.1-μm SOI MOSFET with asymmetric channel profile

The electron velocity overshoot phenomenon in the inversion layer is experimentally investigated using a novel thin-film silicon-on-insulator (SOI) test structure with channel lengths down to 0.08 μm. The uniformity of the carrier density and tangential field is realized by employing a lateral asymmetric channel (LAC) profile. The electron drift velocity observed in this work is 9.5×10⁶ cm/s for a device with L_eff=0.08 μm at 300 K. The upward trend in electron velocity can be clearly noticed for decreasing channel lengths     

An 0.8-μm high-voltage IC using a newly designed 600-V lateralp-channel dual-action device on SOI

A novel lateral power device, termed a p-channel dual-action device (p-ch DAD), is proposed and experimentally demonstrated in action. This device is based on a new dual-action mechanism. The new device has successfully increased on-state current without lowering the device breakdown voltage. The 600-V level-shifting action of the p-ch DAD has been confirmed by a circuit experiment. A newly designed p-ch DAD on the silicon on insulator can be made by adding four additional masks and trench technology to a 0.8-μm CMOS process. Moreover, the process we have developed is completely compatible with an existing 5-V 0.8-μm CMOS process     

A room temperature 0.1 μm CMOS on SOI

An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C_L=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained     

Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI)MOSFET for deep sub-0.1-μm channel regime

This letter proposes a new device structure which is called the “partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET.” The PGP SOI MOSFET minimizes the short-channel effect (SCE) compared to the conventional single-gate (SG) SOI MOSFET because the gate-induced field in the SOI layer is held high by the PGP region. This results in a lower stand-by leakage current. The PGP SOI MOSFET also shows much better switching performance and extremely high analog performance because of its smaller parasitic capacitance compared to the conventional ground-plane (GP) device. Thus, it is shown that the PGP SOI MOSFET is a promising candidate for future deep-sub-0.1-μm mixed-mode LSIs     

A low-resistance self-aligned T-shaped gate for high-performancesub-0.1-μm CMOS

This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-μm region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 μm to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 μm. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-μm gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability     

The investigation of key technologies for sub-0.1-μm CMOS devicefabrication

The fabrication of sub-0.1-μm CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p⁺/n⁺ poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-μm poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-μm CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-μm CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved     

Advanced process device technology for 0.3-μm high-performancebipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm², and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (f_T) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f_T and base resistance is also discussed     

Simulation of sub-0.1-μm MOSFETs with completely suppressedshort-channel effect

MOSFETs in the sub-0.1-μm regime were investigated using a nonplanar device simulator CADDETH-NP. It was found that even in this regime, the short-channel effect can be suppressed in grooved gate MOSFETs because of the concave corner of the gate insulator. MOSFETs with a gate length of 0.05 μm or less with no threshold voltage lowering can be made by optimizing the concave corner radius, junction depths, and channel doping     

Novel properties of a 0.1-μm-long split-gate MODFET

A MODFET with two 30-nm-long gates (separated by 40 nm) has been fabricated using ultrahigh-resolution electron-beam lithography. The proximity of the two gate fingers along with the ability to independently bias them results in the following features: (a) tunability of the threshold voltage, (b) enhancement of the transconductance, especially at low current levels, (c) reduction in short-channel effects, and (d) high-voltage gain and cutoff frequency     

4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOStechnology on SOI, SOS, and bulk substrates

Four- and 13-GHz tuned amplifiers have been implemented in a partially scaled 0.1-1 μm CMOS technology on bulk, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS) substrates. The 4-GHz bulk, SOI, and SOS amplifiers exhibit forward gains of 14, 11, and 12.5 dB and F_min's of 4.5 (bulk) and 3.5 db (SOS). The 13-GHz SOS and SOI amplifiers exhibit gains of 15 and 5.3 dB and F_unn's of 4.9 and 7.8 dB. The 4-GHz bulk amplifier has the highest resonant frequency among reported bulk CMOS amplifiers, while the 13-GHz SOS and SOI amplifiers are the first in a CMOS technology to have tuned frequencies greater than 10 GHz. These and other measurement results suggest that it may be possible to implement 20-GHz tuned amplifiers in a fully scaled 0.1-1 μm CMOS process     

Temperature dependency of 0.1 μm partially depleted SOI CMOSFET

This work investigates the floating body effect (FBE) on the partially depleted SOI devices at various temperatures for high-performance 0.1 μm MOSFET. The thermal effect on the device's characteristics was investigated with respect to the body contacted MOSFET (BC-SOI) and floating body MOSFET without body contacted (FB-SOI). It is found that the threshold voltage (Vth) and the off state drain current (I_OFF) of the BC-SOI devices are more temperature sensitive than those of the FB-SOI devices. For operation at higher temperatures, there is no apparent difference in driving capability between the BC-SOI and FB-SOI MOSFETs     

Capture rate enhance method of 0.1-μm level defects bypattern-matching inspectors

In this paper, a method of enhancing the capture rate of 0.1-μm level defects by pattern-matching inspectors is studied from the viewpoint of image variances. By our method, defect inspection engineers can obtain quantitative information for enhancing the capture rate of 0.1-μm level defects on both actual devices and test element groups (TEGs). The inspection sensitivities were experimentally evaluated by using the detection rate of the defects on an actual device and on the TEG. The image noise and the defect signal of the captured charge-coupled device (CCD) images of the same defect were quantitatively analyzed. The observed image noise and the defect signal obey a normal distribution. The capture rate calculated by our model, based on normal distribution, almost agrees with the experimental data. Next, we propose a new criterion called the “practical rapture rate” by uniting the rapture rate and the false count. The threshold value optimized from the viewpoint of the practical capture rate agrees with empirical thresholds value set by our defect inspection engineers. Finally, as an example of capture rate enhancement, a unique TEG called TWICE (TEG with image contrast enhancing) for photoresist inspection is demonstrated     

DC and microwave characteristics of sub-0.1-μm gate-lengthplanar-doped pseudomorphic HEMTs

Analytical modeling of these very-short-channel HEMTs (high-electron-mobility transistors) using the charge-control model is given. The calculations performed using this model indicate a very high electron velocity in the device channel (3.2±0.2×10⁷ cm/s) and clearly demonstrate the advantages of the planar-doped devices as compared to the conventional uniformly doped HEMTs. Devices with different air-bridged geometries have been fabricated to study the effect of the gate resistance on the sub-0.1-μm HEMT performance. With reduced gate resistance in the air-bridge-drain device, noise figures as low as 0.7 and 1.9 dB were measured at 18 and 60 GHz, respectively. Maximum available gains as high as 13.0 dB at 60 GHz and 9.2 dB at 92 GHz, corresponding to an f_max of 270 GHz, have also been measured in the device. Using the planar-doped pseudomorphic structure with a high gate aspect-ratio design, a noise figure of less than 2.0 dB at 94 GHz is projected based on expected further reduction in the parasitic gate and source resistances     

Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design andscaling trends

In this paper, we present: 1) design of a single-rail energy-efficient 64-b Han-Carlson ALU, operating at 482 ps in 1.5 V, 0.18-μm bulk CMOS; 2) direct port of this ALU to 0.18-μm partially depleted SOI process; 3) SOI-optimal redesign of the ALU using a novel deep-stack quaternary-tree architecture; 4) margining for max-delay pushout due to reverse body bias in SOI designs; and 5) performance scaling trends of the ALU designs in 0.13-μm generation. We show that a direct port of the Han-Carlson ALU to 0.18-μm SOI offers 14% performance improvement after margining. A redesign of the ALU, using an SOI-favored deep-stack architecture improves the margined speedup to 19%. A 10% margin was required for the SOI designs, to account for reverse body-bias-induced max-delay pushout. Preconditioning the intermediate stack nodes in the dynamic ALU designs reduced this margin to 2%. Scaling the ALUs to 0.13-μm generation reduces the overall SOI speedup for both architectures to 9% and 16%, respectively, confirming the trend that speedup offered by SOI technology decreases with scaling     

1.55-μm fiber-optic transmission experiments for long-spansubmarine cable system design

Results of 1.55-μm transmission experiments at 140, 280, and 565 Mb/s involving conventional and dispersion-shifted single-mode fibers along the Fabry-Perot laser diode (FP-LD) and distributed-feedback laser diode (DFB-LD) optical sources are discussed. The results show which combination of optical fiber and optical source best meet the requirement of long repeater spacing for each bit rate. The results indicate that to achieve repeater spacing more than 100 km with dispersion-shifted fibers and FP-LD optical sources will impose strict requirements on both the optical fibers and the optical sources even at 280 Mb/s. Alternatively, systems using DFB-LD optical sources will not degrade the transmission performances and will considerably loosen requirements on the fibers and optical sources. A combination of dispersion-shifted fibers and DFB-LD optical sources can further loosen the requirements on the fibers and optical sources in 560-Mb/s systems     

Metallized ultra-shallow-junction device technology for sub-0.1μm gate MOSFET's

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 μm MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability     

Design and performance of 0.1-μm CMOS devices usinglow-impurity-channel transistors (LICT's)

0.1-μm CMOS devices using low-impurity-channel transistors (LICTs) with dual-polysilicon gates have been fabricated by nondoped epitaxial growth technology, high-pressure oxidation of field oxide, and electron-beam lithography. These devices, with gate lengths of 0.135 μm, achieved normal transistor operation at both 300 and 77 K using 1.5-V supply voltage. Maximum transconductances are 203 mS/mm for nMOS transistors and 124 mS/mm for pMOS transistors at 300 K. Low-impurity channels grown on highly doped wells provide low threshold voltages of about 0.35 V for nMOS transistors and about -0.15 V for pMOS transistors at 77 K, and preserve good turn-offs with subthreshold swings of 25 mV/decade at 77 K. LICTs suppress short-channel effects more effectively, compared with conventional devices with nearly uniform dopings     

Microwave performance of AlInAs-GaInAs HEMTs with 0.2- and0.1-μm gate length

The millimeter-wave performance is reported for Al_0.48In_0.52As-Ga_0.47In_0.53 As high-electron-mobility transistors (HEMTs) with 0.2-μm and 0.1-μm-long gates on material grown by molecular-beam epitaxy on semi-insulating InP substrates. Devices of 50-μm width exhibited extrinsic transconductances of 800 and 1080 mS/mm, respectively. External f_T (maximum frequency of oscillation) of 120 and 135 GHz, respectively, were measured. A maximum f_T of 170 GHz was obtained from a 0.1×200-μm² device. A minimum noise figure of 0.8 dB and associated gain of 8.7 dB were obtained from a single-stage amplifier at frequencies near 63 GHz