An Efficient and Fast Area Optimization Approach for Mixed Polarity Reed-Muller Logic Circuits

Area has become one of the main bottlenecks restricting the development of integrated circuits.The area optimization approaches of existing XNOR/OR-based mixed polarity Reed-Muller(MPRM)circuits have poor optimization effect and efficiency.Given that the area optimization of MPRM logic circuits is a combinatorial opti-mization problem,we propose a whole annealing adaptive bacterial foraging algorithm(WAA-BFA),which includes individual evolution based on Markov chain and Metropolis acceptance criteria,and individual mutation based on adaptive probability.To address the issue of low conversion efficiency in existing polarity conversion approaches,we introduce a fast polarity conversion algorithm(FPCA).Moreover,we present an MPRM circuits area optimization approach that uses the FPCA and WAA-BFA to search for the best polarity corresponding to the minimum circuits area.Experimental results demonstrate that the proposed MPRM circuits area optimization approach is effective and can be used as a promising EDA tool.     

Spectral interpretation of the fast tabular technique for fixed-polarity Reed-Muller expressions

This paper presents a uniform spectral approach to the fast tabular technique for generating fixed polarity Reed–Muller expressions. Basic operations in the tabular technique are described through the discrete dyadic convolution. The presented results can be extended to various polynomial expansions of discrete functions.     

一种改进的二阶Reed-Muller译码算法

研究了一种改进的RM译码算法—改进的Sidel,nikov-Pershakov算法(简称SP算法),详细叙述了原始算法的原理以及改进算法的译码步骤,并对两种算法进行了仿真实现,对它们的译码性能和算法复杂度进行了比较。改进的译码算法复杂度略优于原始算法,而改进后的算法的译码性能明显优于原始算法。     

利用复制理论生成Reed—Muller码的方法

本文通过复制理论简单地生成Reed0-Muller码,并利用复制理论讨论了它的纠错,检错等相关问题,得到了两个简单实用具具有较高可靠性的检错,纠错译码算法。     

Techniques for dual forms of Reed-Muller expansion conversion

Dual Forms of Reed-Muller (DFRM) are implemented in OR/XNOR forms, which are based on the features of coincidence operation. Map folding and transformation techniques are proposed for the conversion between Boolean and DFRM expansions. However, map techniques can only be used for up to 6 variables. To overcome the limitation, serial tabular technique (STT) and parallel tabular technique (PTT) are proposed. STT deals with one variable at a time while PTT generates terms in parallel. Both tabular techniques outperform significantly published work in terms of conversion time. Methods based on on-set canonical sum-of-products minterms and canonical product-of-sums maxterms are also investigated.     

Design metal-dot based QCA circuits using SPICE model

This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE. In the second half part of the paper, SET and QCA co-design methodology is proposed and SET is used as a readout interface of the QCA cell array. The SET and QCA hybrid circuit is a promising nano-scale solution.     

基于或-符合运算Reed-Muller展开系数的对称变量检测算法

针对或-符合代数系统中缺失对称变量检测的有效方法等问题,提出了该代数系统基于或-符合运算Reed-Muller展开系数的十二类变量对称性检测算法。该算法通过分析逻辑函数关于变量xi、xj展开的子函数系数矩阵和或-符合运算Reed-Muller展开系数按变量xi、xj组合分解系数矩阵的对应关系,揭示了任意两变量间各类对称性所满足的分解系数矩阵的约束条件,提出了各类逻辑变量的对称性检测步骤。应用结果表明,与传统方法相比,免去了从逻辑函数的CRM展开式变换为最小项展开式或RM展开式的变换域转换过程,也解决了在该域中图形方法检测的完备性问题,具有简单、直观、完备及适合计算机编程等优点。     

An intelligent technique for generating equivalent gyrator circuits using Genetic Algorithm

Genetic algorithm (GA) applications in analog design circuits play an important role with promising results. This algorithm is utilized to generate equivalent circuits for the well-known gyrator circuit which is the most commonly used active circuit for the realization of a grounded inductor. The conventional gyrator circuit is realized by the op-amp which has the drawback of frequency limitations. This paper introduces the gyrator-GA Technique. It is an intelligent technique for generating equivalent gyrator circuits utilizing Second Generation Current Conveyor (CCII) as well as Transconductance Amplifier (TA) circuits. The proposed algorithm is based on the pathological representation of the active blocks. As illustrations to demonstrate the systematic realization of gyrator-GA, a fifth-order Butterworth lowpass filter is designed and simulated using PSPICE.     

Exploiting bounds optimization for the semi-formal verification of analog circuits

This paper proposes a semi-formal methodology for modeling and verification of analog circuits behavioral properties using multivariate optimization techniques. Analog circuit differential models are automatically extracted and their qualitative behavior is computed for interval-valued parameters, inputs and initial conditions. The method has the advantage of guaranteeing the rough enclosure of any possible dynamical behavior of analog circuits. The circuit behavioral properties are then verified on the generated transient response bounds. Experimental results show that the resulting state variable envelopes can be effectively employed for a sound verification of analog circuit properties, in an acceptable run-time.     

FPRM逻辑电路最佳极性的启发式搜索

本文将启发式思想引入中规模及以上规模逻辑电路的极性优化过程,提出最少操作遍历方法用于求解当前待评估极性集合的最佳遍历顺序,以达到加快电路极性优化速度的目的.将该方法融入遗传算法中,以电路面积最小化为目标,对12个MCNC Benchmark电路进行测试.结果表明,对变量数目多、结构复杂的电路,该方法的最佳极性搜索效率尤为明显.     

Shorts in self-checking circuits

It has been noted by several authors that the classical stuck-at logical fault model might not be an appropriate representation of certain real failures occurring in integrated circuits. Shorts are an important class of such faults. This article gives a detailed analysis of the effects of shorts in self-checking circuits and proposes techniques for dealing with them. More precisely, we show that, unlike other faults such as stuck-at, stuck-on, and stuck-open—which produce only single errors in the place they occur—shorts can produce double errors on the two shorted lines. In particular, feedback shorts can produce double errors on the two shorted lines. The double error is unidirectional for some feedback shorts and non-unidirectional for some others. Furthermore, in some technologies (e.g., CMOS), non-feedback shorts can also produce double non-unidirectional errors. We also show that unlike stuck-at, stuck-on, and stuck-open faults, redundant shorts can destroy the SFS property. Then we propose several techniques for coping with these problems and we illustrate the results by circuit implementation examples.The present study is given for NMOS and CMOS circuits but we show that it is valid for any other technology.     

基于动态逻辑的MPRM电路低功耗优化设计

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。     

基于多数覆盖的二级MPRM函数逻辑优化

利用不相交乘积项之间逻辑“或”和逻辑“异或”可以互换的特性,该文将原逻辑函数转化成由不相交乘积项组成的二级混合极性Reed-Muller (MPRM)函数.然后通过搜索不相交乘积项的多数覆盖和检测乘积项间的位操作结果,实现了二级MPRM函数的优化.另外,该文还提出一种基于逻辑覆盖的功能验证方法也被提出用于验证逻辑函数优化前后逻辑功能的等效性.实验显示,与已发表的方法相比,该文的优化算法在保证优化效果的同时使运算速度获得了明显的改进.     

异步集成电路设计的研究与进展

回顾了异步集成电路设计发展的历史,阐述了当前异步集成电路重新引起重视的原因,总结了异步集成电路的优势,并对异步集成电路设计方法进行了简要地概括,介绍了实用的异步集成电路芯片,最后分析了异步集成电路面临的挑战,并揭示了它今后的发展方向.     

Ground bounce modelling for digital gigascale integrated circuits

In the paper, an analytical model for ground bounce noise evaluation taking into account the interdependence between I_DD switching current and V_DD noise voltage is presented. The model shows the discrepancies from general accepted assumption of independence between the two variables. The main conclusion is that noise calculations using the independence assumption cause an overestimation of the noise levels. The results are verified through realistic simulations and for different technology nodes and accurate analysis of two canonical circuits.     

集成电路的可靠性再筛选

本文介绍了器件可靠性筛选在集成电路生产过程和工艺生产上的重要性，提出了器件可造性筛选的一些重要方法。     

The probability of error detection in sequential circuits using random test vectors

In this article a method is presented for evaluating the probability of detecting (PD) a single stuck-fault in a sequential circuit as a function of the number of random input test vectors. A discrete parameter Markov-model is used in the analysis to obtain closed-form expressions for PD. The circuit is partitioned into three parts, the input and output combinational logic and the memory. The analysis is based upon the stationary-state transition matrix associated with a circuit, and the probability that a fault in one of the partitions produces an error at the output of that partition when a random input vector is applied. Results are presented to show how this problem can be reduced to that of testing an equivalent combinational circuit.     

Organic integrated circuits using room-temperature sintered silver nanoparticles as printed electrodes

Organic integrated circuits based on organic thin-film transistor (TFT) devices are fabricated with solution-based electrodes by using dense inks of silver nanoparticles, which can be sintered at room-temperature. The TFT devices fabricated at a sintering temperature of 30 °C exhibit good electrical characteristics. There is a strong relation between the sintering temperature of silver nanoparticle inks and transistor characteristics. A work function of silver electrodes can be controlled by changing the sintering temperature of silver nanoparticle inks, thereby threshold voltage of fabricated TFT devices are shifted accordingly. Fabricated pseudo-CMOS inverter circuits are successfully operated at low voltage with small hysteresis, and large gains are obtained. These results suggest that printed organic TFT devices fabricated with a low-temperature process enable large-area and low-cost integrated circuits by using these techniques in future applications.     

共振隧穿二极管基础电路的模拟与分析

简单介绍了RTD的器件特性和器件模型 ,用HSPICE模拟出RTD与电阻、MOS晶体管、RTD本身结合的电路特性。通过对不同电路参数I V特性的模拟和分析 ,为理解RTD器件机理和构造复杂电路提供了初步的基础     

混合电路电磁兼容设计与实例

在设计电子产品时,除了满足特定的功能要求外,还必须考虑产品的电磁兼容性,这对产品的质量和性能技术指标起着非常关键的作用。本文主要介绍了PCB设计时一些常用的解决电磁兼容性问题的措施,主要包括PCB布局、PCB布线、电源与地、时钟信号等方面的电磁兼容设计。并结合具体的工程实例进行说明分析。