Spectral interpretation of the fast tabular technique for fixed-polarity Reed-Muller expressions

This paper presents a uniform spectral approach to the fast tabular technique for generating fixed polarity Reed–Muller expressions. Basic operations in the tabular technique are described through the discrete dyadic convolution. The presented results can be extended to various polynomial expansions of discrete functions.     

一种改进的二阶Reed-Muller译码算法

研究了一种改进的RM译码算法—改进的Sidel,nikov-Pershakov算法(简称SP算法),详细叙述了原始算法的原理以及改进算法的译码步骤,并对两种算法进行了仿真实现,对它们的译码性能和算法复杂度进行了比较。改进的译码算法复杂度略优于原始算法,而改进后的算法的译码性能明显优于原始算法。     

利用复制理论生成Reed—Muller码的方法

本文通过复制理论简单地生成Reed0-Muller码,并利用复制理论讨论了它的纠错,检错等相关问题,得到了两个简单实用具具有较高可靠性的检错,纠错译码算法。     

基于混合多值离散粒子群优化的混合极性Reed-Muller最小化算法

针对布尔函数系统的混合极性Reed-Muller(Mixed-Polarity Reed-Muller,MPRM)最小化问题,该文提出了一种混合多值离散粒子群优化算法.为解决多样性损失,改善优化结果,兼顾算法的效率和精度,算法采用多群协同优化方法,并提出了概率变异更新、没有重复的更新以及群间重复最优变异3种更新和变异策略.实验结果表明,和模拟退火遗传算法相比,所构造算法能够在获得基本相同优化结果的同时,提高MPRM最小化的时间效率.     

Techniques for dual forms of Reed-Muller expansion conversion

Dual Forms of Reed-Muller (DFRM) are implemented in OR/XNOR forms, which are based on the features of coincidence operation. Map folding and transformation techniques are proposed for the conversion between Boolean and DFRM expansions. However, map techniques can only be used for up to 6 variables. To overcome the limitation, serial tabular technique (STT) and parallel tabular technique (PTT) are proposed. STT deals with one variable at a time while PTT generates terms in parallel. Both tabular techniques outperform significantly published work in terms of conversion time. Methods based on on-set canonical sum-of-products minterms and canonical product-of-sums maxterms are also investigated.     

基于近似计算技术的FPRM电路面积优化

近似计算技术通过降低电路输出精度实现电路功耗、面积、速度等方面的优化.本文针对RM（Reed-Muller）逻辑中"异或"运算特点，提出了基于近似计算技术的适合FPRM逻辑的电路面积优化算法，包括基于不相交运算的RM逻辑错误率计算方法，及在错误率约束下，有利于面积优化的近似FPRM函数搜索方法等.优化算法用MCNC（Microelectronics Center of North Carolina）电路进行测试.实验结果表明，提出的算法可以处理输入变量个数为199个的大电路，在平均错误率为5.7%下，平均电路面积减少62.0%，并在实现面积优化的同时有利于实现电路的动态功耗的优化且对电路时延影响不大.     

基于或-符合运算Reed-Muller展开系数的对称变量检测算法

针对或-符合代数系统中缺失对称变量检测的有效方法等问题,提出了该代数系统基于或-符合运算Reed-Muller展开系数的十二类变量对称性检测算法。该算法通过分析逻辑函数关于变量xi、xj展开的子函数系数矩阵和或-符合运算Reed-Muller展开系数按变量xi、xj组合分解系数矩阵的对应关系,揭示了任意两变量间各类对称性所满足的分解系数矩阵的约束条件,提出了各类逻辑变量的对称性检测步骤。应用结果表明,与传统方法相比,免去了从逻辑函数的CRM展开式变换为最小项展开式或RM展开式的变换域转换过程,也解决了在该域中图形方法检测的完备性问题,具有简单、直观、完备及适合计算机编程等优点。     

Design metal-dot based QCA circuits using SPICE model

This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE. In the second half part of the paper, SET and QCA co-design methodology is proposed and SET is used as a readout interface of the QCA cell array. The SET and QCA hybrid circuit is a promising nano-scale solution.     

Synthesis of optical circuits using binary decision diagrams

The advances in silicon photonics motivated the consideration of optical circuits as a new and emerging circuit technology. In particular for ultra-fast interconnects, optical circuits may provide a suitable alternative since it avoids the conversion of signals from the optical to the electrical domain. Accordingly, design automation of this kind of circuits received significant attention. In this work, we consider synthesis of optical circuits based on Binary Decision Diagrams (BDDs). Although BDDs allow for a direct mapping of the function representation to an optical circuit (and, hence, a scalable synthesis), they have their shortcomings with respect to dedicated cost metrics. In this work, we investigate this issue and provide an overview of the BDD-based synthesis schemes which are available thus far. Afterwards, we propose new solutions based on a dedicated BDD optimization which aim for addressing the known shortcomings. Experimental results confirm the benefits of the proposed approach.     

Exploiting bounds optimization for the semi-formal verification of analog circuits

This paper proposes a semi-formal methodology for modeling and verification of analog circuits behavioral properties using multivariate optimization techniques. Analog circuit differential models are automatically extracted and their qualitative behavior is computed for interval-valued parameters, inputs and initial conditions. The method has the advantage of guaranteeing the rough enclosure of any possible dynamical behavior of analog circuits. The circuit behavioral properties are then verified on the generated transient response bounds. Experimental results show that the resulting state variable envelopes can be effectively employed for a sound verification of analog circuit properties, in an acceptable run-time.     

An intelligent technique for generating equivalent gyrator circuits using Genetic Algorithm

Genetic algorithm (GA) applications in analog design circuits play an important role with promising results. This algorithm is utilized to generate equivalent circuits for the well-known gyrator circuit which is the most commonly used active circuit for the realization of a grounded inductor. The conventional gyrator circuit is realized by the op-amp which has the drawback of frequency limitations. This paper introduces the gyrator-GA Technique. It is an intelligent technique for generating equivalent gyrator circuits utilizing Second Generation Current Conveyor (CCII) as well as Transconductance Amplifier (TA) circuits. The proposed algorithm is based on the pathological representation of the active blocks. As illustrations to demonstrate the systematic realization of gyrator-GA, a fifth-order Butterworth lowpass filter is designed and simulated using PSPICE.     

FPRM逻辑电路最佳极性的启发式搜索

本文将启发式思想引入中规模及以上规模逻辑电路的极性优化过程,提出最少操作遍历方法用于求解当前待评估极性集合的最佳遍历顺序,以达到加快电路极性优化速度的目的.将该方法融入遗传算法中,以电路面积最小化为目标,对12个MCNC Benchmark电路进行测试.结果表明,对变量数目多、结构复杂的电路,该方法的最佳极性搜索效率尤为明显.     

Shorts in self-checking circuits

It has been noted by several authors that the classical stuck-at logical fault model might not be an appropriate representation of certain real failures occurring in integrated circuits. Shorts are an important class of such faults. This article gives a detailed analysis of the effects of shorts in self-checking circuits and proposes techniques for dealing with them. More precisely, we show that, unlike other faults such as stuck-at, stuck-on, and stuck-open—which produce only single errors in the place they occur—shorts can produce double errors on the two shorted lines. In particular, feedback shorts can produce double errors on the two shorted lines. The double error is unidirectional for some feedback shorts and non-unidirectional for some others. Furthermore, in some technologies (e.g., CMOS), non-feedback shorts can also produce double non-unidirectional errors. We also show that unlike stuck-at, stuck-on, and stuck-open faults, redundant shorts can destroy the SFS property. Then we propose several techniques for coping with these problems and we illustrate the results by circuit implementation examples.The present study is given for NMOS and CMOS circuits but we show that it is valid for any other technology.     

基于离散三值粒子群算法的MPRM电路面积优化

Having the advantage of simplicity,robustness and low computational costs,the particle swarm optimization (PSO) algorithm is a powerful evolutionary computation tool for synthesis and optimization of ReedMuller logic based circuits.Exploring discrete PSO and probabilistic transition rules,the discrete ternary particle swarm optimization(DTPSO) is proposed for mixed polarity Reed-Muller(MPRM) circuits.According to the characteristics of mixed polarity OR/XNOR expression,a tabular technique is improved,and it is applied in the polarity conversion of MPRM functions.DTPSO is introduced to search the best polarity for an area of MPRM circuits by building parameter mapping relationships between particles and polarities.The computational results show that the proposed DTPSO outperforms the reported method using maxterm conversion starting from POS Boolean functions.The average saving in the number of terms is about 11.5%;the algorithm is quite efficient in terms of CPU time and achieves 12.2%improvement on average.     

基于动态逻辑的MPRM电路低功耗优化设计

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。     

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high‐speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high‐speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan‐in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.     

基于混合离散粒子群算法的MPRM电路延时和面积综合优化

Polarity optimization for mixed polarity Reed-Muller(MPRM) circuits is a combinatorial issue.Based on the study on discrete particle swarm optimization(DPSO) and mixed polarity,the corresponding relation between particle and mixed polarity is established,and the delay-area trade-off of large-scale MPRM circuits is proposed. Firstly,mutation operation and elitist strategy in genetic algorithm are incorporated into DPSO to further develop a hybrid DPSO(HDPSO).Then the best polarity for delay and area trade-off is searched for large-scale MPRM circuits by combining the HDPSO and a delay estimation model.Finally,the proposed algorithm is testified by MCNC Benchmarks.Experimental results show that HDPSO achieves a better convergence than DPSO in terms of search capability for large-scale MPRM circuits.     

基于三值多样性粒子群算法的MPRM电路综合优化

通过对离散三值粒子群算法的研究,提出一种三值多样性粒子群算法以求解MPRM（Mixed-Polarity Reed-Muller,MPRM）电路综合优化问题.首先根据混合极性XNOR/OR展开式的特点和几率换算法则,推导出三值粒子群算法的运动方程,在此基础上,采用广泛学习策略和三值变异操作进行算法改进;然后建立三值多样性粒子群算法的粒子与MPRM电路极性的参数映射关系,结合估计模型和XNOR/OR电路混合极性转换方法,将所提算法应用于MPRM电路的最佳功耗和面积极性搜索;最后对10个PLA格式MCNC Benchmark电路进行测试.结果表明：与已发表的方法相比,该文的优化算法表现出了总体显著性的性能优势.     

基于多数覆盖的二级MPRM函数逻辑优化

利用不相交乘积项之间逻辑"或"和逻辑"异或"可以互换的特性,该文将原逻辑函数转化成由不相交乘积项组成的二级混合极性Reed-Muller(MPRM)函数。然后通过搜索不相交乘积项的多数覆盖和检测乘积项间的位操作结果,实现了二级MPRM函数的优化。另外,该文还提出一种基于逻辑覆盖的功能验证方法也被提出用于验证逻辑函数优化前后逻辑功能的等效性。实验显示,与已发表的方法相比,该文的优化算法在保证优化效果的同时使运算速度获得了明显的改进。     

Kernel-based template attacks of cryptographic circuits using static power

Side-channel attacks using static power have been shown to be successful against cryptographic circuits in different environments. This class of attacks exploits the power leakage when the circuit is in a static state, during which the power leakage is expected to be a fixed value. Due to the low signal-to-noise ratio of static power, usually more traces are needed for a static power attack to reach the same success rate as a dynamic power attack. The probabilistic distribution pattern of static power varies significantly in different devices, which further poses challenges to the accurate modeling of static power. In this paper we propose non-parametric template attacks which use a kernel methodology to improve the accuracy of modeling static power consumption. The proposed template attacks are tested using transistor-level simulations of circuits designed with a 45-nm standard cell library. Our test results show that our approach improves the success rate of template attacks using static power in cases where the distribution of static power consumption cannot be accurately modeled by Gaussian models.