Attenuation mechanisms of aluminum millimeter-wave coplanar waveguides on silicon

The loss mechanisms of silicon coplanar waveguides (CPW) with aluminum metallization are investigated up to 40 GHz. Three main parts contribute to the attenuation of coplanar waveguides (CPWs): the frequency-dependent conductor losses of the metallization, frequency-independent substrate losses, and the specifically investigated bias-dependent interface losses caused by free charges at the Si-SiO/sub 2/ interface. The minimum losses found in 50-/spl Omega/ CPWs with 45-/spl mu/m signal line width were 0.19 db/mm at 10 GHz and 0.33 dB/mm at 40 GHz. High-purity silicon from a float zone (FZ) process was used as substrate. Substrates with lower purity from a Czochralski (CZ) process (resistivity 50-100 /spl Omega/cm) resulted in somewhat higher (0.2-0.3 dB/mm) losses for the same CPW geometry.     

在高阻硅衬底上制备低微波损耗的共面波导

分别在普通的低阻硅衬底、带有3μm厚氧化硅介质层的低阻硅衬底和高阻硅衬底上设计并制备了微波传输共面波导.结果表明,低阻硅衬底导致过高的微波损耗从而不能使用,通过加氧化硅介质层,微波损耗可以大大减少,但是需要较厚的氧化硅厚度.直接制备在高阻硅衬底上的共面波导在所测试的26GHz的频率范围内获得低于2dB/cm的微波损耗,而且工艺十分简单.     

Characterization and attenuation mechanism of CMOS-compatible micromachined edge-suspended coplanar waveguides on low-resistivity silicon substrate

This paper presents detailed characterization of a category of edge-suspended coplanar waveguides that were fabricated on low-resistivity silicon substrates using improved CMOS-compatible micromachining techniques. The edge-suspended structure is proposed to provide reduced substrate loss and strong mechanical support at the same time. It is revealed that, at radio or microwave frequencies, the electromagnetic waves are highly concentrated along the edges of the signal line. Removing the silicon underneath the edges of the signal line, along with the silicon between the signal and ground lines, can effectively reduce the substrate coupling and loss. The edge-suspended structure has been implemented by a combination of deep reactive ion etching and anisotropic wet etching. Compared to the conventional silicon-based coplanar waveguides, which show an insertion loss of 2.5dB/mm, the loss of edge-suspended coplanar waveguides with the same dimensions is reduced to as low as 0.5 dB/mm and a much reduced attenuation per wavelength (dB//spl lambda//sub g/) at 39 GHz. Most importantly, the edge-suspended coplanar waveguides feature strong mechanical support provided by the silicon remaining underneath the center of the signal line. The performance of the coplanar waveguides is evaluated by high-frequency measurement and full-wave electromagnetic (EM) simulation. In addition, the resistance, inductance, conductance, capacitance (RLGC) line parameters and the propagation constant of the coplanar waveguides (CPWs) were extracted and analyzed.     

K-band monolithic InGaP-InGaAs DCFET amplifier using BCB coplanar waveguide technology

A K-band (20 GHz) monolithic amplifier was developed and fabricated by adopting a low-/spl kappa/ benzocyclobutene (BCB) coplanar waveguide (CPW) line and InGaP-InGaAs doped-channel HFETs (DCFETs). This monolithic microwave integrated circuit (MMIC) utilizes a high impedance BCB CPW microstrip line (Z/sub 0/=70 /spl Omega/) for the biasing circuits, and a Z/sub 0/=50 /spl Omega/ line for the RF signal transmission. The low dielectric constant characteristic of the BCB interlayer is beneficial for a common-ground bridge process, which reduces the parasitics. The calculated loss tan/spl delta/ is 0.036 for the BCB at 20 GHz. The one-stage MMIC amplifier achieves an S/sub 21/ of 5 dB at 20 GHz, which is the first demonstration of the K-band InGaP-InGaAs DCFET monolithic circuit.     

Small-size CPW silicon resonating antenna based on transmission-line meta-material approach

A small-size zeroth-order resonating antenna based on a composite right/left-handed transmission line (CRLH TL) fabricated on high resistivity silicon substrate using coplanar waveguides (CPW) is proposed. The CRLH TL consists of a series of CPW interdigital capacitors and parallel short-ended CPWs. The predicted and experimental results for return loss, gain and radiation pattern are in very good agreement.     

Characterization of silver CPWs for applications in silicon MMICs

High-Q broadband passives are needed for monolithic microwave circuits in silicon. Coplanar waveguides (CPWs) provide an effective way to implement passives in silicon monolithic microwave integrated circuits. Silver "fat" wires in the backend interconnects, used for CPW fabrication, will reduce the bulk resistive loss in metallization to the lowest possible level, which is vital to minimize noise. Electromigration, electrochemical migration, and agglomeration issues are not a problem for silver microwave passives, because of their coarse dimensions and the low current densities encountered in these structures. In this letter, Ag and Cu CPWs were designed, fabricated and tested. Silver CPWs showed a 2-3/spl Omega//cm improvement in resistance over copper devices at 20GHz. A circuit was identified in which the application of silver passives could provide an improvement in noise performance.     

Low-loss on-chip transmission lines with micro-patterned artificial dielectric shields

Low-loss coplanar waveguide (CPW) transmission lines integrated on a standard (5 -10 Omega ldr cm) silicon substrate are realised by using an artificial dielectric shield with a very high in-plane dielectric constant. The shield consists of a 30 nm-thick Al₂O₃ film sandwiched by two 100 nm-thick aluminium layers patterned into lattices of mum-size elements. The individual metallic elements are micro-patterned to suppress the flow of eddy currents at microwave frequencies. Inserted below the CPW, the shield blocks the electric field of the line from entering the silicon substrate. The resulting line attenuation (measured up to 25 GHz) is comparable to that of identical CPWs built on a high-resistivity silicon wafer.     

Surface-passivated high-resistivity silicon substrates for RFICs

Surface passivation of high-resistivity silicon (HRS) by amorphous silicon thin-film deposition is demonstrated as a novel technique for establishing HRS as a microwave substrate. Metal-oxide-silicon (MOS) capacitor measurements are used to characterize the silicon surface properties. An increase of the quality factor (Q) of a 10-nH spiral inductor by 40% to Q=15 and a 6.5-dB lower attenuation of a coplanar waveguide (CPW) at 17 GHz indicate the beneficial effect of the surface passivation for radio frequency (RF) and microwave applications. Regarding CPW attenuation, a nonpassivated 3000-/spl Omega//spl middot/cm substrate is equivalent to a 70-/spl Omega//spl middot/cm passivated substrate. Surface-passivated HRS, having minimum losses, a high permittivity, and a high thermal conductivity, qualifies as a close-to-ideal radio frequency and microwave substrate.     

High frequency electrical circuits on a planar lightwave circuitplatform

We investigated the propagation losses and the characteristic impedances Z_L of coplanar waveguides (CPWs) and microstrip lines (MSLs) on a planar lightwave circuit (PLC)-platform formed on a silica/silicon substrate. The loss of the CPWs was 2.7 dB/cm at 10 GHz on the PLC-platform with 30 μm thick silica layer. Thus, a cm-order circuit of this CPW is difficult to fabricate in the 10 Gb/s module. This is because the silicon substrate has a large loss tangent (tan δ). On the other hand, the loss of the MSLs, where a ground plane shielded the high loss silicon substrate, could be improved to 0.9 dB/cm at 10 GHz with 30 μm thick polyimide. These lower loss MSLs on a PLC-platform can be applied to module operation at 10 Gb/s. Furthermore they have the advantage that they are suitable for application to array device circuits or circuits in a module where several devices are integrated because unlike CPWs the ground planes are not divided by signal lines or DC bias lines. The structure of CPWs and MSLs on a PLC-platform with a Z_L of 50 Ω was also studied in detail     

Low-loss CPW on low-resistivity Si substrates with a micromachinedpolyimide interface layer for RFIC interconnects

The measured and calculated propagation constant of coplanar waveguide (CPW) on low-resistivity silicon (1 Ω·cm) with a micromachined polyimide interface layer is presented in this paper. With this new structure, the attenuation (decibels per centimeter) of narrow CPW lines on low-resistivity silicon is comparable to the attenuation of narrow CPW lines on high-resistivity silicon. To achieve these results, a 20-μm-thick polyimide interface layer is used between the CPW and the Si substrate with the polyimide etched from the CPW slots. Only a single thin-film metal layer is used in this paper, but the technology supports multiple thick metal layers that will further lower the attenuation. These new micromachined CPW lines have a measured effective permittivity of 1.3. Design rules are presented from measured characteristics and finite-element method analysis to estimate the required polyimide thickness for a given CPW geometry     

不同材料上共面波导线的损耗研究

研究不同衬底材料上共面波导(CPW)线的损耗特性。实验结果表明,采用低阻SOI(20Ω·cm)作衬底制作的共面波导线的损耗比在低阻硅(20Ω·cm)上制作的有明显减少;而采用低阻硅,并沉积1μmSiO2作衬底的CPW线损耗大大降低。采用高阻SOI(1000Ω·cm)制备的CPW线在2GHz损耗仅为0.13dB/mm;通过在低阻硅上采用地屏蔽技术也可以有效地改善传输线的损耗特性,在整个频段内的损耗可与高阻SOI硅衬底上相比拟。     

RF characterization and isolation properties of mesoporous Si by on-chip coplanar waveguide measurements

We report on the broadband electrical characterization of thick mesoporous silicon layers used as RF microplates for on-chip integration of high-Q passive devices in a CMOS-compatible process. To measure the RF losses of the microplate we have fabricated several designs of Coplanar Waveguides (CPWs), for form-factors relevant to the sizes of on-chip passive RF devices, on thick mesoporous Si layers (RF microplates) of various thicknesses, and we compared the results with those obtained from similar CPWs integrated directly on the p-type Si substrate. For maximum measurement sensitivity of the loss, the CPWs were designed to be very good transmission lines matched to 50 Ω port impedances. We also characterized the grown mesoporous Si by performing electromagnetic simulations of the structure and identifying the measured and simulated S-parameters over a broadband frequency region, for the appropriate simulator input of complex permittivity. The measured results show that, for CPW features commensurate with the scale of on-chip RF passive devices, a 50-μm-thick mesoporous Si layer on the Si substrate reduces the losses to 1/6th–1/4th of the values corresponding to a p-type Si substrate, showing that mesoporous Si is an excellent material for CMOS-compatible on-chip integration of high-Q passive devices.     

Influence of the SRO as passivation layer on the microwave attenuation losses of the CPWs fabricated on HR-Si

In this letter, silicon rich oxide (SRO) is used as the passivation layer of coplanar wave guides (CPWs) fabricated on high resistivity silicon (HR-Si). The microwave performance of the CPWs is evaluated computing the attenuation loss (/spl alpha/) of the device in the 0.045-50 GHz frequency range. It is shown that for frequencies lower than 5 GHz the losses of CPWs using SRO as a passivation layer are lower than those of CPWs using SiO/sub 2/. It is also shown that using a combination of thermal and CVD SiO/sub 2/, a reduction of the losses of CPWs is obtained.     

Attenuation characteristics of coplanar waveguides at subterahertz frequencies

We present experimental and simulation data of subterahertz attenuation of coplanar waveguides (CPWs) with wide and narrow ground planes. Experimental data are obtained by using a subpicosecond measurement technique based on electrooptic sampling. While time-domain data qualitatively describe the attenuation characteristics, they are converted to the frequency domain by a Fourier transform to give a quantitative interpretation. Simulation data are obtained by full-wave analysis and compared with the experimental results. It is shown that the simulation results consistently agree with experimental results. Furthermore, in the case of CPWs with wide ground planes, both of them are consistent with analytical theory. While CPWs with narrow ground planes have not been analytically studied, our results show that they suffer considerably lower attenuation, which we attribute to a reduced coupling between the CPW mode and substrate modes. The effects of ground-plane width and line dimensions on the attenuation characteristics are discussed in detail.     

A Millimeter-Wave System-on-Package Technology Using a Thin-Film Substrate With a Flip-Chip Interconnection

In this paper, a system-on-package (SOP) technology using a thin-film substrate with a flip-chip interconnection has been developed for compact and high-performance millimeter-wave (mm-wave) modules. The thin-film substrate consists of Si-bumps, ground-bumps, and multilayer benzocyclobutene (BCB) films on a lossy silicon substrate. The lossy silicon substrate is not only a base plate of the thin-film substrate, but also suppresses the parasitic substrate mode excited in the thin-film substrate. Suppression of the substrate mode was verified with measurement results. The multilayer BCB films and the ground-bumps provide the thin-film substrate with high-performance integrated passives for the SOP capability. A broadband port terminator and a V-band broad-side coupler based on thin-film microstrip (TFMS) circuits were fabricated and characterized as mm-wave integrated passives. The Si-bumps dissipate the heat generated during the operation of flipped chips as well as provide mechanical support. The power dissipation capability of the Si-bumps was confirmed with an analysis of DC-IV characteristics of GaAs pseudomorphic high electron-mobility transistors (PHEMTs) and radio-frequency performances of a V-band power amplifier (PA). In addition, the flip-chip transition between a TFMS line on the thin-film substrate and a coplanar waveguide (CPW) line on a flipped chip was optimized with a compensation network, which consists of a high-impedance and low-impedance TFMS line and a removed ground technique. As an implementation example of the mm-wave SOP technology, a V-band power combining module (PCM) was developed on the thin-film substrate with the flip-chip interconnection. The V-band PCM incorporating two PAs with broadside couplers showed a combining efficiency higher than 78%.      

Integration of 0/1-Level Packaged RF-MEMS Devices on MCM-D at Millimeter-Wave Frequencies

This paper reports on the development and optimization of 0/1-level packaged coplanar waveguide (CPW) lines and radio-frequency microelectromechanical systems (RF-MEMS) switches up to millimeter-wave frequencies. The 0-level package consists of an on-chip cavity obtained by flip-chip mounting a capping chip over the RF-MEMS device using BenzoCyclobutene (BCB) as the bonding and sealing material. The 0-level coplanar RF feedthroughs are implemented using BCB as the dielectric; gold stud-bumps and thermocompression are used for realizing the 1-level package. The 0-level packaged switches have been flip-chip mounted on a multilayer thin-film interconnect substrate using a high-resistivity Si carrier with embedded passives and substrate cavities. The insertion loss of a single 0/1-level transition is below -0.15 dB at 50 GHz. The measured return loss of a 0/1-level packaged 50-Omega CPW line remains better than -19 dB up to 71 GHz and better than -15 dB up to 90 GHz. It is shown that the leak rate of BCB sealed cavities depends on the BCB width, and leak rates as low as 10^-11 mbar.l/s are measured for large BCB widths (> 800 mum), dropping to 10^-8 mbar.l/s for BCB widths of around 100 mum. Depending on the bonding conditions, shear strengths as high as 150 MPa are achieved.     

Si/SiO_2系统电荷对高阻硅基CPW传输损耗的影响

通过高频C-V测试得到实验制备的共平面波导(CPW)下方的Si/SiO2系统电荷主要表现为正电荷,其密度约为4.8×1010/cm2。三种不同衬底上50Ω共平面波导分别为直接制备于高阻硅上、高阻硅氧化层上、去除信号线与地线间的高阻硅氧化层上。20GHz时,测得上述三种CPW的微波传输损耗分别为-0.88dB、-2.50dB及-1.06dB,因此去除线间氧化层使得传输线损耗降低了1.44dB。此外还测试了高阻硅氧化层和除去线间氧化层的高阻硅氧化层上的两种CPW的传输损耗随外加偏压的变化。     

Zero-level packaging using BCB adhesive bonding and glass wet-etching for W-band applications

A small size zero-level packaging method, by using wafer-level benzocyclobutene (BCB) adhesive bonding and a pyrex glass wet-etching technique, is presented. A simple process was developed to make a pyrex glass to have housing cavities and BCB sealing ring for a packaging. During a wet-etching of glass for making a cavity and pad feedthroughs, BCB was protected by 1.2 /spl mu/m-thick AZ1512 photoresist. To estimate a pyrex 7740 packaging material in W-band, a 50 W coplanar waveguide (CPW) was designed and an insertion loss (S/sub 12/) was measured. The insertion loss change of CPW lines by the fabricated package is below 0.1 dB from DC to 110 GHz.     

Fully integrated unequal Wilkinson power divider with EBG CPW

In this paper, a CPW with electromagnetic bandgap (EBG CPW) is newly proposed for designing a transmission line with high impedance. After designing, fabricating, and evaluating the characteristic impedance of the proposed EBG CPW transmission line, it will be applied to an integrated unequal Wilkinson power divider. In the EM simulation, the EBG-CPW transmission line with 10 /spl mu/m in line width has the same characteristic impedance as a CPW with a line width of 2.5 /spl mu/m. The insertion and return losses of the fabricated power divider with a power ratio of 1 to 3 are less than -0.7 dB and -15 dB, respectively. It also has excellent isolation characteristics with more than -20 dB. The experimental results are good agreement with the simulation.     

High transmission gain inverted-F antenna on low-resistivity Si for wireless interconnect

Inverted-F antennas of 2-mm axial length are designed and fabricated on a low-resistivity silicon substrate (10 /spl Omega//spl middot/cm) using a post back-end-of-line process. For the first time, their performances are measured up to 110 GHz for wireless interconnects. Results show that a sharp resonance can be seen at 61 GHz for the antenna, and a high transmission gain of -46.3 dB at 61 GHz is achieved from the pair of inverted-F antennas at a separation of 10 mm on a standard 10 /spl Omega//spl middot/cm silicon wafer of 750-/spl mu/m thickness.