Memory effects of all‐solution‐processed oxide thin‐film transistors using ZnO nanoparticles

Abstract— Non‐volatile memory effects of an all‐solution‐processed oxide thin‐film transistor (TFT) with ZnO nanoparticles (NPs) as the charge‐trapping layer are reported. The device was fabricated by using a soluble MgInZnO active channel on a ZrHfO^x gate dielectric. ZnO NPs were used as the charge‐trapping site at the gate‐insulator—channel interface, and Al was used for source and drain electrodes. Transfer characteristics of the device showed a large clockwise hysteresis, which can be used to demonstrate its memory function due to electron trapping in the ZnO NP charge‐trapping layer. This memory effect has the potential to be utilized as a memory application on displays and disposable electronics.     

Uniformity and bias‐temperature instability of bottom‐gate zinc oxide thin‐film transistors (ZnO TFTs)

Abstract— Short‐range uniformity and bias‐temperature (BT) instability of ZnO TFTs with SiO^x/SiN^x stacked gate insulators which have different surface treatments have been investigated. The short‐range uniformity of ZnO TFTs was drastically improved by N²O plasma treatment of the gate insulator. The variation in the gate voltage where a drain current of 1‐nA flows (Vgs at an Ids of 1 nA) was dramatically reduced from ±1.73 V to ±0.07 V by N²O plasma treatment of the gate insulator. It was clarified that the variations in the subthreshold characteristics of the ZnO TFTs could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the variation of trap densities in deep energy levels from 0.9–2.0 × 10¹⁷ to 1.2–1.3×10¹⁷ cm^?3‐eV^?1. From the BT stress tests, a positive shift of Vgs at an Ids of 1 nA could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the charge traps in the gate insulator. When the gate‐bias stress increases, state creation occured in the ZnO TFTs in addition to the charge trapping in the gate insulator. However, N²O plasma treatment of the gate insulator has little effect on the suppression of the state creation in ZnO TFTs under BT stress. The surface treatment of the gate insulator strongly affects the short‐range uniformity and the BT instability of Vth in the ZnO TFTs.     

Two‐stage degradation in n‐channel LTPS‐TFTs under negative and positive bias stresses

Device degradation behaviors of n‐channel low‐temperature polycrystalline silicon thin film transistors under negative bias stress and positive bias stress were investigated. It was found that the threshold‐voltage has a two‐stage degradation, shifting to different direction with time. The mobility and the subthreshold swing SS both show a dependence on the stress time. It was determined that the interface trap states, the grain boundary trap states, and electron trapping together dominate the time‐dependent degradation behaviors. The trap is caused by the rupture of Si─H and Si─O bonds. A comprehensive model is proposed to explain the time‐dependent degradation behaviors clearly. In addition, after removing the stress, the recovery behaviors of threshold voltage V_th can be observed, which provide the evidence supporting the degradation model proposed.     

Development of 55” 4K UHD OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs

We investigated oxide TFT backplane technology to employ the internal gate driver IC (GIP circuit) on 55” 4K OLED TV panel. For the GIP circuit, we developed the high reliability oxide TFTs, especially only ?0.4 V Vth degradation under 100‐h long‐term PBTS stress and the short channel length TFTs (L = 4.5um) for narrow bezel. Consequently, we demonstrated the 55‐in 4K OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs.     

Spice model for detection of dynamic threshold voltage shift during failure analysis of oxide TFT‐based AMD gate drivers

We present an accelerated SmartSpice model that can detect dynamic threshold voltage shift (ΔV_th)‐related failure of an oxide thin‐film transistor (TFT)‐based gate driver. During gate driver operation, the alternating HIGH and LOW input signals repeatedly stress and relax the TFT components of the gate driver. Because oxide TFTs do not recover completely during the LOW input level, ΔV_th cumulated during the HIGH input levels may result in failure of gate drivers. For correct failure analysis, a TFT model that can detect dynamic ΔV_th is, therefore, needed to replace current TFT models, as they cannot account for dynamic ΔV_th. The model presented herein works correctly with varying temperature and input signals of any shape.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

Accurate‐gray‐level and quick‐response driving methods for high‐performance electrowetting displays

Abstract— To achieve quick‐response electrowetting displays (EWDs) with accurate multiple‐gray‐level performance for video applications, several phenomena, such as hysteresis, charge trapping, and oil splitting, need to be addressed. This paper proposes a driving scheme that includes the decoupling driving concept, the asymmetric driving concept, the charge‐trapping‐suppression method, and the oil‐splitting method. The proposed driving scheme was extensively investigated on a developed evaluation platform, and satisfactory results for multiple‐gray levels and quick response were obtained for a 6‐in. SVGA EWD.     

Characteristics improvement of top‐gate self‐aligned amorphous indium gallium zinc oxide thin‐film transistors using a dual‐gate control

In this work, we have reported dual‐gate amorphous indium gallium zinc oxide thin‐film transistors (a‐IGZO TFTs), where a top‐gate self‐aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a‐IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (I_ON), sub‐threshold slope (SS^?1), output resistance, and bias‐stress instabilities are improved in comparison with single‐gate control self‐aligned a‐IGZO TFTs. We have also investigated the applicability of the dual‐gate a‐IGZO TFTs in logic circuitry such as 19‐stage ring oscillators.     

Stress control for overlay registration in a‐Si:H TFTs on flexible organic‐polymer‐foil substrates

Abstract— Mechanical stress in hydrogenated amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) is becoming an important design parameter, especially when the TFTs are made on compliant substrates. Excessive stress always has been avoided to prevent film fracture and peeling. Now, attention is turning to the effects of stress on the TFT backplane dimensions and hence on the overlay alignment. The goal is to keep the size of the circuit‐on‐substrate composite structure the same at successive critical photolithographic steps. This is done most easily by keeping the structure flat. We show that a compensating stress can be dialed into the silicon nitride SiN_x) gate dielectric to also keep the substrate size constant. Varying the stress in the SiN_x gate dielectric did not significantly change the as‐fabricated TFT characteristics.     

Instability of light illumination stress on amorphous In–Ga–Zn–O thin‐film transistors

Amorphous In–Ga–Zn–O thin‐film transistors (TFTs) have attracted increasing attention due to their electrical performance and their potential for use in transparent and flexible devices. Because TFTs are exposed to illumination through red, green, and blue color filters, wavelength‐varied light illumination tests are required to ensure stable TFT characteristics. In this paper, the effects of different light wavelengths under both positive and negative V_GS stresses on amorphous In–Ga–Zn–O TFTs are investigated. The TFT instability that is dependent on optical and electrical stresses can be explained by the charge trapping mechanism and interface modification.     

Flexible color LCD panel driven by low‐voltage‐operation organic TFT

Abstract— A flexible color LCD panel driven by organic TFTs (OTFTs) was successfully demonstrated. A pentacene OTFT with an anodized Ta₂O₅ gate insulator, which can be operated at low voltage, was developed. In order to improve the electrical performance of the OTFT, the gate insulator was surface treated by processes such as O₂ plasma, UV light irradiation, and hexamethyldisilane treatments. The fabricated OTFT exhibited a mobility of 0.3 cm²/V‐sec and a current on/off ratio of 10⁷ with a low operating drain voltage of ?5 V. A fast‐response‐time flexible ferroelectric LCD, which contains polymer networks and walls, was integrated with the OTFTs by using a lamination and a printing technique. As a result, color images were achieved on the fabricated panel by using a field‐sequential‐color method at a low driving voltage of less than 15 V_pp.     

Maximizing electro‐optic performances in the fringe‐field switching liquid crystal mode with negative dielectric anisotropic liquid crystal

The fringe‐field switching (FFS) mode that uses liquid crystals (LCs) with negative dielectric anisotropy is used in high‐resolution FFS liquid crystal display owing to its higher transmittance over positive LC, although its response time becomes slow and operating voltage (V_op) becomes high. In the device, reduction of the cell gap is required to achieve fast response time, which results in increase in V_op in general. In this paper, we propose the FFS mode with electrode width 1 µm and distance between the electrodes 1.5 µm. In such an electrode structure, V_op decreases with decreasing cell gap to 2 µm so that a proper V_op, high LC's light efficiency of 90%, a high color temperature, and a fast response time less than 10 ms, can be achieved, which maximizes electro‐optic performance of the FFS mode.     

Letter: Solution‐processed flexible zinc‐tin oxide thin‐film transistors on ultra‐thin polyimide substrates

In this letter, solution‐processed flexible zinc‐tin oxide (Z_0.35T_0.65O_1.7) thin‐film transistors with electrochemically oxidized gate insulators (AlOx:Nd) fabricated on ultra‐thin (30 µm) polyimide substrates are presented. The AlOx:Nd insulators exhibited wonderful stability under bending and excellent insulating properties with low leakage current, high dielectric constant, and high breakdown field. The device exhibited a mobility of 3.9 cm²/V · s after annealing at 300 °C. In addition, the flexible device was able to maintain the electricity performance under various degrees of bending, which was attributed to the ultra‐thin polyimide substrate.     

Circuits and AMOLED display with self‐aligned a‐IGZO TFTs on polyimide foil

A process to make self‐aligned top‐gate amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field‐effect mobility of 12.0 cm²/(V.s), sub‐threshold slope of 0.5 V/decade, and current ratio (I_ON/OFF) of >10⁷. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (?1.0 MV/cm) bias direction after extended stressing time of 10⁴ s. We achieve a stage‐delay of ~19.6 ns at V_DD = 20 V measured in a 41‐stage ring oscillator. A top‐emitting quarter‐quarter‐video‐graphics‐array active‐matrix organic light‐emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V_DD), the brightness of the display exceeds 150 cd/m².     

Modeling power and intermodulation behavior of microwave transistors with unified small‐signal/large‐signal neural network models

This article presents a detailed procedure to learn a nonlinear model and its derivatives to as many orders as desired with multilayer perceptron (MLP) neural networks. A modular neural network modeling a nonlinear function and its derivatives is introduced. The method has been used for the extraction of the large‐signal model of a power MESFET device, modeling the nonlinear relationship of drain‐source current I_ds as well as gate and drain charge Q_g and Q_d with respect to intrinsic voltages V_gs and V_ds over the whole operational bias region. The neural models have been implemented into a user‐defined nonlinear model of a commercial microwave simulator to predict output power performance as well as intermodulation distortion. The accuracy of the device model is verified by harmonic load‐pull measurements. This neural network approach has demonstrated to predict nonlinear behavior with enough accuracy even if based only on first‐order derivative information. © 2003 Wiley Periodicals, Inc. Int J RF and Microwave CAE 13: 276–284, 2003.     

New small‐signal extraction method applied to GaN HEMTs on different substrates

In this article, a new extraction technique is proposed to extract the small‐signal parameters of gallium nitride (GaN) high electron mobility transistors (HEMTs) on three different substrates namely, Si, SiC, and Diamond. This extraction technique used a single small‐signal circuit model to efficiently describe the physical and electrical properties of GaN on different substrates. This technique takes into account any asymmetry between the gate‐source and gate‐drain capacitances on the asymmetrical GaN HEMT structure, charge‐trapping effects, passivation layer inclusion, as well as leakage currents associated with the nucleation layer between the GaN buffer layer and the different substrates. The extracted values were then optimized using the grey wolf optimizer. The proposed technique was demonstrated through a close agreement between simulated and measured S‐parameters.     

Charge‐recombination processes in oligomer‐ and polymer‐based light‐emitting diodes: A molecular picture

Abstract— An overview of our recent work on the mechanisms of singlet and triplet exciton formation in electroluminescent π‐conjugated materials will be presented. According to simple spin statistics, only one‐fourth of the excitons are formed as singlets. However, deviations from that statistics can occur if the initially formed triplet charge‐transfer (CT) excited states are amenable to intersystem crossing or dissociation. Although the electronic couplings between the CT states and the neutral exciton states are expected to be largest for the lowest singlet and triplet excitons (S¹ and T¹, respectively), the possibility for direct recombination into T¹ is always very small due to the large exchange energy. In small molecules, spin statistics is expected to be observed because both singlet and triplet exciton formations proceed via higher‐lying S_n/T_n states with similar electronic couplings and fast formation rates. In extended conjugated chains, however, that the ¹CT → S¹ pathway is faster while the ³CT → ^Tn channels become much slower, opening the route to intersystem crossing or dissociation among the ³CT states.     

An external compensation method for AMOLED using the concept of ramp‐stop

In this paper, we propose an external feedback method to compensate the device variation for active‐matrix organic light‐emitting diode. The pixel data current is controlled by ramping the gate voltage and converted to the sensed voltage V_sense in real time. When V_sense is equal to a preset voltage V_data, the switching block outputs the low potential to stop the ramping. Therefore, the gate voltage is locked at the value corresponding to the target data current. This circuit is implemented with three thin‐film transistors in the active area and some functional blocks in driver integrated circuit (IC), namely, sentinel block, current‐voltage converting block, and switching block. Unlike the other usual methods of external compensation requiring double number of connections between driver IC and glass, by using the common ramping signal and a simple circuit made on glass, the proposed method can be implemented with only one pin per column.     

Amorphous‐silicon gate‐driver circuits of shared‐node dual pull‐down structure with overlapped output signals

Abstract— A novel gate‐driver circuit using amorphous‐silicon (a‐Si) TFTs has been developed. The circuit has a shared‐node dual pull‐down AC (SDAC) structure with a common‐node controller for two neighboring stages, resulting in a reduced number of TFTs. The overlapped clock signals widen the temperature range for stable operation due to the extended charging time of the inner nodes of the circuit. The accelerated lifetime was found to be over 1000 hours at 60°C with good bias‐temperature‐stress (BTS) characteristics. Accordingly, the a‐Si gate‐driver circuit was successfully integrated into a 14.1‐in. XGA (1024 × RGB × 768) TFT‐LCD panel having a single bank form.