Development of 55” 4K UHD OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs

We investigated oxide TFT backplane technology to employ the internal gate driver IC (GIP circuit) on 55” 4K OLED TV panel. For the GIP circuit, we developed the high reliability oxide TFTs, especially only ?0.4 V Vth degradation under 100‐h long‐term PBTS stress and the short channel length TFTs (L = 4.5um) for narrow bezel. Consequently, we demonstrated the 55‐in 4K OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs.     

Integrated gate driver circuit technology with IGZO TFT for sensing operation

In this paper, we propose a new integrated gate driver circuit for random sensing operation of external compensated organic light‐emitting diode (OLED) display using oxide thin‐film transistor (TFT). Using this technology, we successfully launched 55‐inch and 65‐inch ultrahigh definition OLED TVs with gate in panel (GIP) circuit. The structure of the existing OLED TVs implemented gate signals through the gate integrated circuits (ICs) attached to the left and right sides of the panel. The structure using the gate IC was inferior to the panel structure using the GIP in terms of process and product design and cost. Thus, we propose a new oxide GIP circuit for OLED TV. Like the previous gate IC model, the proposed GIP circuit successfully implemented the random sensing function during the display operation. This GIP circuit is also designed to overcome the problems caused by the negative Vth characteristics of the oxide device.     

Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

Highly robust oxide TFT with bulk accumulation and source/drain/active layer splitting

We report stable and high performance amorphous indium‐gallium‐zinc oxide (a‐IGZO) thin‐film transistor (TFT) by using bulk‐accumulation (BA) and split active/source/drain layers. The a‐IGZO TFTs exhibit the mobility over 80 cm²/Vs and extremely stable under bias and mechanical stresses. We demonstrated a 4‐inch semitransparent AMOLED using the oxide TFT backplane with the gate driver integrated.     

Transparent AMOLED display driven by split oxide TFT backplane

We have developed stable and high performance etch‐stopper amorphous indium–gallium–zinc oxide thin‐film transistor (TFT) by using split active oxide semiconductor. The amorphous indium–gallium–zinc oxide TFTs exhibit the mobility as high as over 70 cm²/Vs and the stable operation under positive bias temperature stress. In this work, we demonstrated a 4‐in. transparent active‐matrix organic light‐emitting diode display using oxide TFT backplane with split active layer, where the gate driver is integrated.     

Vertically integrated,double stack oxide TFT layers for high‐resolution AMOLED backplane

We developed a novel vertically integrated, double stack oxide thin‐film transistor (TFT) backplane for high‐resolution organic light‐emitting diode (OLED) displays. The first TFT layer is bulk‐accumulation mode, and the second TFT layer is a single gate with back‐channel etched structure. The extracted mobilities and threshold voltages are higher than 10 cm²/Vs and 0 ~ 1 V, respectively. Both TFTs are found to be extremely stable under the bias and temperature stress. The gate driver with width of 530 μm and a pitch of 18.6 μm was developed, exhibiting well shifted signal up to the last stage of 900 stages without output degradation, which could be used for 1360 ppi TFT backplane.     

Performance enhancement of solution-processed amorphous WZTO TFT with HAO gate dielectric via power ultrasound technology

In this paper, power ultrasound technology (PUT) is employed to prepare the high-k hafnium-aluminum oxide (HAO) dielectric and thin film transistor (TFT). The continuous propagation of high-intensity ultrasonic waves in the metal oxide precursor solution can improve the dissolution efficiency of the solute and speed up the formation of the HAO precursor solution. The prepared HAO films have a smooth surface roughness of 0.36 nm and high optical transmittance of 85 %. Moreover, HAO films obtain excellent electrical properties with a relative permittivity of 15.9 and a leakage current density of 9.1 × 10⁻⁸ A/cm² at 2 MV/cm as well. Finally, we successfully fabricate TFT with HAO dielectric using PUT, these TFTs exhibit switch characteristics with field effect mobility of 18.7 cm²v⁻¹s⁻¹, threshold voltage (V_th) of −0.47 V, and Vth shift of 0.35 V under positive gate bias stress. The results show that the PUT is a promising method that can remarkably decrease the preparation time of the precursor solution and improve the TFT performance.     

Driver‐circuits‐integrated LCDs based on novel amorphous In‐Ga‐Zn‐oxide TFT

Abstract— A liquid‐crystal panel integrated with a gate driver and a source driver by using amorphous In—Ga—Zn‐oxide TFTs was designed, prototyped, and evaluated. By using the process of bottom‐gate bottom‐contact (BGBC) TFTs, amorphous In—Ga—Zn‐oxide TFTs with superior characteristics were provided. Further, for the first time in the world, a 4‐in. QVGA liquid‐crystal panel integrated with a gate driver and a source driver was developed by using BGBC TFTs formed from an oxide semiconductor. By evaluating the liquid‐crystal panel, its functionality was successfully demonstrate. Based on the findings, it is believed that the novel BGBC amorphous In—Ga—Zn‐oxide TFT will be a promising candidate for future large‐screen backplanes having high definition.     

Amorphous‐oxide TFT backplane for large‐sized AMOLED TVs

Abstract— Amorphous‐oxide thin‐film‐transistor (TFT) arrays have been developed as TFT backplanes for large‐sized active‐matrix organic light‐emitting‐diode (AMOLED) displays. An amorphous‐IGZO (indium gallium zinc oxide) bottom‐gate TFT with an etch‐stop layer (ESL) delivered excel lent electrical performance with a field‐effect mobility of 21 cm²/V‐sec, an on/off ratio of >10⁸, and a subthreshold slope (SS) of 0.29 V/dec. Also, a new pixel circuit for AMOLED displays based on amorphous‐oxide semiconductor TFTs is proposed. The circuit consists of four switching TFTs and one driving TFT. The circuit simulation results showed that the new pixel circuit has better performance than conventional threshold‐voltage (VTH) compensation pixel circuits, especially in the negative state. A full‐color 19‐in. AMOLED display with the new pixel circuit was fabricated, and the pixel circuit operation was verified in a 19‐in. AMOLED display. The AMOLED display with a‐IGZO TFT array is promising for large‐sized TV because a‐IGZO TFTs can provide a large‐sized backplane with excellent uniformity and device reliability.     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

An external compensation method for AMOLED using the concept of ramp‐stop

In this paper, we propose an external feedback method to compensate the device variation for active‐matrix organic light‐emitting diode. The pixel data current is controlled by ramping the gate voltage and converted to the sensed voltage V_sense in real time. When V_sense is equal to a preset voltage V_data, the switching block outputs the low potential to stop the ramping. Therefore, the gate voltage is locked at the value corresponding to the target data current. This circuit is implemented with three thin‐film transistors in the active area and some functional blocks in driver integrated circuit (IC), namely, sentinel block, current‐voltage converting block, and switching block. Unlike the other usual methods of external compensation requiring double number of connections between driver IC and glass, by using the common ramping signal and a simple circuit made on glass, the proposed method can be implemented with only one pin per column.     

Novel LTPS technology for large substrate

We developed partial laser anneal silicon (PLAS) thin‐film transistor (TFT) of novel low‐temperature polycrystalline‐silicon (LTPS) technology, which had the mobility of 28.1 cm²/Vs lager than that of mass produced oxide TFT and photo‐stability comparable with that of LTPS TFT in bottom gate structure. This innovative technology enables the conversion from an α‐Si TFT to a high‐mobility TFT most easily and inexpensively. Moreover, there is no limit of substrate size, such as Gen10 and more. Photo‐stability of PLAS will be suitable to organic light‐emitting diode backplane, high‐dynamic range TV, and outdoor IDP.     

Amorphous‐silicon gate‐driver circuits of shared‐node dual pull‐down structure with overlapped output signals

Abstract— A novel gate‐driver circuit using amorphous‐silicon (a‐Si) TFTs has been developed. The circuit has a shared‐node dual pull‐down AC (SDAC) structure with a common‐node controller for two neighboring stages, resulting in a reduced number of TFTs. The overlapped clock signals widen the temperature range for stable operation due to the extended charging time of the inner nodes of the circuit. The accelerated lifetime was found to be over 1000 hours at 60°C with good bias‐temperature‐stress (BTS) characteristics. Accordingly, the a‐Si gate‐driver circuit was successfully integrated into a 14.1‐in. XGA (1024 × RGB × 768) TFT‐LCD panel having a single bank form.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.     

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

Characteristics improvement of top‐gate self‐aligned amorphous indium gallium zinc oxide thin‐film transistors using a dual‐gate control

In this work, we have reported dual‐gate amorphous indium gallium zinc oxide thin‐film transistors (a‐IGZO TFTs), where a top‐gate self‐aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a‐IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (I_ON), sub‐threshold slope (SS^?1), output resistance, and bias‐stress instabilities are improved in comparison with single‐gate control self‐aligned a‐IGZO TFTs. We have also investigated the applicability of the dual‐gate a‐IGZO TFTs in logic circuitry such as 19‐stage ring oscillators.     

Robust integrated shift register circuit over clock noises for in‐cell touch applications

This paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to ?28.95 dB compared with 2.37 dB of the previous circuit.     

A low‐cost low‐temperature thin‐film‐transistor backplane based on oxide semiconductor

Abstract— An indium‐gallium‐zinc‐oxide (IGZO) thin‐film transistor (TFT) based on an anodized aluminum‐oxide gate dielectric and photoresist passivation has been fabricated. The TFT showed a field‐effect mobility of as high as 18 cm²/V‐sec and a threshold voltage of only 0.5 V. A 50 × 50 AMOLED display based on this type of TFT was designed and fabricated. The average luminance of the panel was 150 cd/m², and the maximum pixel luminance was 900 cd/m².     

Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors

Abstract— P‐type low‐temperature (450°C) polycrystalline‐silicon thin‐film‐transistor circuits for peripheral driver integration in active‐matrix displays are proposed and verified. A low‐voltage (5 V) driven poly‐Si scan driver is designed by employing a level shifter and shift register. A source driver for six‐bit digital interface is proposed, and the building blocks such as latch, DAC, and analog buffer are described. The latch samples and holds the digital bits (D and D') without an output voltage loss. A new source‐follower type analog buffer is developed and exhibits a small offset deviation regardless of the V_TH variation of the buffer TFT. The simulation and measurement results ensure that the proposed circuits were successfully designed for p‐type panel integration.     

A novel low‐power gate driver architecture for large 8 K 120 Hz liquid crystal display employing IGZO technology

A novel low‐power gate driver architecture was developed for large 8 K 120 Hz liquid crystal display panel. For this application, not only high‐speed driving but also low power consumption is required. We employed a high mobility In‐Ga‐Zn‐O, dual V_GL level driving method, and gate driver circuit driven by DC supply. The simulation results show that our proposals meet 8 K 120 Hz driving requirements. Also, we have fabricated a prototype panel and confirmed both high‐speed driving and low power consumption.