微波退火法低温制备多晶硅薄膜晶体管

多晶硅薄膜晶体管以其独特的优点在液晶显示领域中有着重要位置。为了满足在普通玻璃衬底上制备多晶硅薄膜晶体管有源矩阵液晶显示器,低温制备（小于600℃）高质量多晶硅薄膜已成为研究热点,文章利用微波加热技术,采用非晶硅薄膜微波退火固相晶化法低温制备出多晶硅薄膜晶体管,研究了微波退火工艺对多晶硅薄膜晶体管电学性能的影响。     

有源矩阵液晶显示集成驱动电路

介绍了多晶硅薄膜晶体管的特性,分析了有源矩阵液晶显示的扫描和数据驱动电路,以及用于多晶硅薄膜晶体管的集成驱动电路的设计方案。     

微波退火非晶硅薄膜低温晶化研究

多晶硅薄膜晶体管以及其独特的优点在液晶显示领域中起着重要的作用。为了满足在普通玻璃衬底上制备多晶硅薄膜晶体管有源矩阵液晶显示器,低温制备（＜600℃高质量多晶硅薄膜已成为研究热点。文章研究了一种低温制备多晶硅薄膜的新工艺;微波退火非晶硅薄膜固相晶化法,利用X射线衍射、拉曼光谱和扫描电镜分析了微波退火工艺对非晶硅薄膜固相晶化的影响,成功实现了低温制备多晶硅薄膜。     

多晶硅TFT及其在AMLCD中的应用

多晶硅薄膜晶体管目前是大面积微电子学领域中最热门的研究课题之一,它以其独特的优点,在液晶显示领域中失常着重要角色,简要介绍了多晶硅薄膜晶体管的结构、器件特性以及在有源矩阵液晶显示器中的应用。     

多晶硅TFTAMLCD的现状与前景

多晶硅有源矩阵液晶显示技术，特别是一体化多晶硅有源矩阵液晶显示技术以它独特的优点，越来越受到重视，并将在液晶显示领域中占有重要地位，但是，多晶硅有源矩阵液晶显示技术还存在一些问题，这也正是目前研究的主要内容，本文对低温下淀积高质量多晶硅薄膜技术；通过退火使非晶硅结晶为多晶硅技术；器件层转移技术；钝化技术；一体化技术以及多晶硅有源矩阵液晶显示的前景等进行了分析和讨论。     

高性能金属诱导单向横向晶化多晶硅薄膜晶体管技术和应用

低温金属单向诱导横向晶化多晶硅薄膜晶体管技术与常规的固相晶化多晶硅薄膜晶体管相比，制作工艺简单，而且提高了场效应迁移率和漏极击穿电压，降低了漏电电流，改进了器件参数空间分布的均匀性。我们使用金属单向诱导横向晶化多晶硅薄膜晶体管技术，成功地制作了有源矩阵液晶显示器和有源矩阵有机发光二极管显示器。     

用非晶硅薄膜晶体管寻址的有源矩阵液晶显示的视频特性

引言近来,平板显示有源矩阵液晶显示(LCD)得到广泛的开发。各种类型的有源矩阵液晶显示已有报导。我们已报导过可用激光再结晶的多晶硅来获得重复性和一致性好的薄膜晶体管(TFT)。然而,由于激光再结晶TFT是用某些高温过程的大规模集成工艺制作的,而且,在大规模集成工艺设备中存在某些尺寸限制,使得激光再结晶多晶硅TFT阵列不适用于大面积显示。另一方面,非晶硅TFT目前普遍用作有源矩阵LCD中的开关管。最近,我们已经制成由非晶硅TFT组成的,对角线尺寸为5英寸和10英寸的有源矩阵LCD。     

微波退火法制备多晶硅薄膜的电学特性研究

为实现多晶硅薄膜晶体管有源矩阵液晶显示器的实用化与产业化 ,低温 (<6 0 0°C)、快速制备高质量多晶硅薄膜已成为研究热点。文中将微波加热技术应用于金属诱导 a- Si薄膜横向晶化工艺中 ,成功实现了低温快速制备多晶硅薄膜。通过薄膜电阻率的测试 ,分析了多晶硅薄膜的电学特性。     

一门引人注目的新学科——大面积电子学

概述了大面积电子学的发展现状与趋势，介绍了太阳能电池、薄膜晶体管，有源矩阵液晶显示和场发射阵列等大面积电子器件的目前研制水平及其应用前景。     

一门引人注目的新学科——大面积电子学

概述了大面积电子学的发展现状与趋势，介绍了太阳能电池、薄膜晶体管、有源矩阵液晶显示和场发射阵列等大面积电子器件的目前研制水平及其应用前景。     

Self-aligned offset gated poly-Si TFTs with a floating sub-gate

We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained     

A novel polysilicon thin-film transistor with a p-n-p structuredgate electrode

We propose and fabricate a novel polycrystalline silicon thin-film transistor (poly-Si TFT) which exhibits the properties of an offset gated structure in the OFF state, while acting as a nonoffset structure in the ON state. The fabrication process is compatible with the conventional nonoffset poly-Si TFT's process and does not require any additional mask. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device. It is observed that the ON/OFF current ratio of the proposed poly-Si TFT is improved remarkably     

Polycrystalline silicon-germanium thin-film transistors

The fabrication of p- and n-channel MOS thin-film transistors (TFT's) in polycrystalline silicon-germanium (poly-Si_1-xGe _x) films is described, and their electrical characteristics are presented. Various technological issues are then addressed in order to provide direction for further work in optimizing the fabrication process. The initial devices fabricated in this work exhibit well behaved electrical characteristics; enhanced performance is expected to accompany improvements in the crystallization and defect-passivation processes. Compared to a poly-Si TFT technology, an optimized poly-Si _1-xGe_x TFT technology may ultimately be able to provide a lower-temperature, shorter-time processing capability at little expense to device performance and it is therefore promising for large-area electronics applications     

基于 P-Type 多晶硅TFT技术的集成型有源 OLED 驱动电路

低温多晶硅(LTPS:Low-temperature poly-Si)技术已经成为薄膜晶体管(TFT:thin film transistor)制作中最具吸引力的技术,并应用在AMOLED显示器中.P-type 技术能够简化 TFT 的制作过程.本文提出了一种应用 p-type 多晶硅 TFT的 AMOLED 驱动电路结构,包括栅极驱动器、数据驱动器以及像素阵列.数据驱动器采用分块方法,使得显示屏的输出线数大大减少.作者采用一种改进的 p-type 移位寄存器实现逐行选通的功能,并采用由 4 个 p-type 反相器级联构成的缓冲器来提高电路的驱动能力.为了验证上述电路结构的正确性,作者采用 HSPICE 软件进行仿真分析.结果表明,电路工作正常.利用韩国汉城国立大学及 Neo Poly 公司在多晶硅制作方面的优势,我们已经合作完成了应用上述电路结构的分辨率为96×3×128的有源 OLED 的制作.     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

Characterization of the novel polysilicon TFT with a subgatecoupling structure

Proposed and fabricated a novel polysilicon thin film transistor (poly-Si TFT) with a subgate coupling structure that behaves as an offset gated structure in the OFF state while acting as a conventional nonoffset structure in the ON state. The OFF state leakage current of the new TFT is two orders of magnitude lower than that of the conventional nonoffset TFT, while the ON current of the new TFT is one order of magnitude higher than that of the offset TFT and is almost identical to that of the conventional non-offset TFT. The ON/OFF current ratio of the new TFT is greatly improved by two orders of magnitude. No additional photo-masking steps are required to fabricate the subgate of the new TFT and its fabrication process is fully the same as the conventional nonoffset TFTs     

A high-endurance low-temperature polysilicon thin-film transistorEEPROM cell

A planar type polysilicon thin-film transistor (poly-Si TFT) EEPROM cell with electron cyclotron resonance (ECR) N₂O-plasma oxide has been developed with a low temperature (⩽400°C) process. The poly-Si TFT EEPROM cell has an initial threshold voltage shift of 4 V for programming and erasing voltages of 11 V and -11 V, respectively. Furthermore, the poly-Si TFT EEPROM cell maintains the threshold voltage shift of 4 V after 100 000 program/erase cycles. The excellent high endurance of the fabricated poly-Si TFT EEPROM cell is attributed to the ECR N₂O-plasma oxide with good charge-to-breakdown (Qbd) characteristics     

A Novel Blocking Technology for Improving the Short-Channel Effects in Polycrystalline Silicon TFT Devices

An original blocking technology is proposed for improving the short-channel characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs). In particular, two types of modified devices called poly-Si TFT with block oxide and poly-Si on partial insulator (POPI)-TFT are designed for the first time in this field to enhance device performance. The proposed TFT structures can significantly reduce short-channel effects when compared with a thick source/drain (S/D) poly-Si TFT (i.e., the fully depleted TFT). In addition, an ultrathin (UT) S/D structure (UT-TFT) is designed to verify that the block oxide TFT devices do achieve improved performance without needing the thin active layers and ultrashallow junction depth. Also, the POPI-TFT is found to reduce the thermal instability through its natural body-tied scheme.     

Stable polycrystalline silicon TFT with MICC

We studied the bias-induced changes in the performance of the poly-Si thin-film transistor (TFT) by metal-induced crystallization of amorphous silicon through a cap layer (MICC) poly-Si. The p-channel poly-Si TFT exhibited a field-effect mobility of 101 cm/sup 2//V/spl middot/s and a minimum leakage current of <1.0/spl times/10/sup -12/ A//spl mu/m at V/sub ds/=-10 V. The MICC poly-Si TFT performance changes little by either gate or hot-carrier bias stress. The better stability appears to be due to the smooth surface of MICC poly-Si, which is /spl sim/2 nm that is much smaller than that (13 nm) of a laser-annealed poly-Si.     

Fabrication of Poly—Si TFT by Al—induced Lateral Crystallization at Low Temperature

Using a new low-temperature process (<600 ℃), the poly-Si TFT was fabricated by metal-induced lateral crystallization (MILC). An ultrathin aluminum layer was deposited on a-Si film and selectively formed by photolithography. The films were then annealed at 560 ℃ to obtain laterally crystallized poly-Si film, which is used as the channel area of a TFT. The poly-Si TFT showed an on/off current ratio of higher than 1×10 6 at a drain voltage of 5 V. The electrical properties are much better than TFT fabricated by conventional crystallization at 600 ℃.