基于摄动法研究短沟道SOI MOSFET亚阈值特性

提出了一种新的方法对短沟道SOI MOSFETs亚阈区的二维表面势的解析模型进行了改进,即摄动法.由于在短沟道SOI MOSFETs中不仅需要计及不可动的电离杂质,而且需要考虑自由载流子的数量和分布的影响.利用摄动法求解非线性泊松方程可以得到短沟道SOI MOSFETs二维的表面势解析模型.通过与二维数值模拟器MEDICI模拟结果比较,证明了在亚阈区改进模型所得的结果比只计及不可动的电离杂质的SOI MOSFETs模型所得的结果吻合更好.     

一种非对称双栅应变硅HALO掺杂沟道MOSFET阈值电压解析模型

提出了一种非对称双栅应变硅HALO掺杂沟道金属氧化物半导体场效应管结构.该器件前栅和背栅由两种不同功函数的金属构成,沟道为应变硅HALO掺杂沟道,靠近源区为低掺杂区域,靠近漏区为高掺杂区域.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,分别求解了前背栅表面势、前背栅表面电场及前背栅阈值电压,建立了双栅器件的表面势、表面电场和阈值电压解析模型.详细讨论了物理参数对解析模型的影响.研究结果表明,该器件能够很好的抑制短沟道效应、热载流子效应和漏致势垒降低效应.模型解析结果与DESSIS仿真结果吻合较好,证明了该模型的正确性.     

双栅肖特基源漏MOSFET的阈值电压模型

通过求解泊松方程得到了双栅肖特基势垒MOSFET的解析模型. 这个解析模型包括整个沟道的准二维电势分布和适用于短沟双栅肖特基势垒MOSFET的阈值电压模型.数值模拟器ISE DESSIS验证了模型结果.     

双栅肖特基源漏MOSFET的阈值电压模型

通过求解泊松方程得到了双栅肖特基势垒MOSFET的解析模型. 这个解析模型包括整个沟道的准二维电势分布和适用于短沟双栅肖特基势垒MOSFET的阈值电压模型.数值模拟器ISE DESSIS验证了模型结果.     

非均匀沟道DMOS器件阈值电压模型

提出了DMOS器件的二维电荷阈值电压模型。基于沟道区杂质的二维分布,求解泊松方 程,得到沟道区中耗尽电荷总量,给出DMOS二维阈值电压模型的解析式。该模型的解析解与实验 结果和数值解相吻合。并对DMOS的短沟效应和阈值电压与沟道表面扩散浓度、沟道结深和沟道 长度等参数的关系进行了深入分析,给出了短沟DMOS器件阈值电压的解析式。文中还给出了沟 道表面掺杂浓度在2.0×1016cm-3到10.0×1016cm-3范围内DMOS器件的阈值电压简明计算式。该 模型解决了习用的DMOS器件阈值电压模型解析值比实验结果大100％以上的问题。     

深结短沟道MOS晶体管准二维阈值电压模型

提出了一个新的短沟道MOS晶体管表面势的准二维解析模型。不同于经典模型,该模型对沟道耗尽层横向剖分,由高斯定理导出沟道耗尽层电势的一维微分方程,方程考虑了漏、源的横向电场对沟道耗尽层厚度的影响。求解方程得到了耗尽层厚度与表面势的关系函数,由此得出了一个包含有沟道长度的阈值电压公式。通过MEDICI软件对多种不同参数的MOS晶体管进行了仿真,此模型计算结果与MEDICI仿真数据吻合较好,比电荷分享模型精度高。     

适用于亚微米沟道MO SFET的阈值电压解析模型

本文利用本征函数方法,采取一定的边界条件,得到了二维泊松方程的解析解.并由此导得适用于亚微米沟道MOS场效应管阈值电压的解析表达式.本解析模型未引进复杂的几何结构参数及经验参数,适用于不同的衬底反偏电压、漏极电压等条件.这些结果与数值模拟的结果以及有关实验的结果符合得较好,对短沟道MOSFET的设计及性能的了解有实际参考价值.     

对称三材料双栅应变硅MOSFET亚阈值电流与亚阈值斜率解析模型

基于泊松方程和边界条件,推导了对称三材料双栅应变硅金属氧化物半导体场效应晶体管（MOSFET：metal oxide semiconductor field effect transistor）的表面势解析解.利用扩散-漂移理论,在亚阈值区电流密度方程的基础上,提出了亚阈值电流与亚阈值斜率二维解析模型.分析了沟道长度、功函数差、弛豫SiGe层的Ge组份、栅介质层的介电常数、应变硅沟道层厚度、栅介质高k层厚度和沟道掺杂浓度等参数对亚阈值性能的影响,并对亚阈值性能改进进行了分析研究.研究结果为优化器件参数提供了有意义的指导.模型解析结果与DESSIS仿真结果吻合较好.     

短沟道MOS FET亚阈值电流的解析模型

利用二维泊松方程的解析解,得到了短沟道MOS FET亚阈值电流的解析模型.在弱反型区,解析模型的结果与数值模拟的结果符合较好.     

短沟DMOS阈值电压模型

该文提出了短沟DMOS阈值电压模型。基于沟道区耗尽电荷的二维分布,计算沟道区中耗尽电荷总量,由此给出短沟DMOS阈值电压模型的计算式。该模型的解析解与二维仿真器MEDICI的数值解吻合。分析表明,DMOS沟道长度小于0.80m,就应考虑短沟效应。     

Numerical study of the effect of the doping profile on the threshold voltage of narrow-channel MOS transistor

A two-dimensional MOS process and device simulator, called IMPEDANCE, is used to study the influence of various doping profiles of stopper and channel implantations on the threshold voltage of narrow-channel MOS transistor (made with LOCOS isolation technology). For enhancement-mode transistors without channel implantation the lateral spread of the stopper implantation is the main factor for the threshold voltage increase with decreasing channel width. However the increase of the channel implantation dose reduces the dependence of the threshold voltage on the width especially at higher ion energies. In case of depletion-mode transistors the dependence of the threshold voltage on width is stronger owing to: (1) the existence of a lateral p-n junction between the channel and the stopper region and (2) the weaker gate control of the channel carriers.     

Substrate current in short n-channel MOS transistors

Tho substrain current against gate voltage characteristics or relatively short n-channel MOS transistors were examined for various substrate and drain voltages, channel length and surface doping conditions : namely without implantation, implantation for threshold voltage adjustment and implantation for depletion mode device types A, B and C, respectively. The substrate current may increase or decrease when increasing the aubstrate voltage magnitude duo to the fact that the drain current decreases and the multiplication factor increases with the substrate bias. The substrate current increases when decreasing the channel length. It increases for the devices of type B, but is lower for type C. These experimental results were qualitatively explained by using published models in which the substrate current is caused by low-level impact ionization within the pinched-off region. A simple model in which the ionization coefficient and the field derivative with respect to x wore assumed to be power-law field-dependent correctly predicts the behaviour of the substrate current.     

Threshold voltage predictions from MICROMOS: A 3-D MOS simulator

This paper provides predicted values of threshold voltage for the fully recessed MOS structure obtained from the 3-D code called MICROMOS. Uniform and implanted channel cases are both considered. Additionally, short channel, narrow width and small geometry effects are automatically included. Results for these conditions as well as variable oxide thickness and substrate doping are shown. All of the results obtained indicate the correct tendency of change for threshold voltage. Values for threshold voltage prediction are obtained from 3-D computer generated drain current vs gate voltage characteristics.     

A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs

A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs. Different short channel field effects, such as fringing fields, junction-induced lateral fields and substrate fields, are carefully investigated, and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model. Through analytical model-based simulation, the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations. Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model. The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET. The short channel effects are found to be reduced in an SON, thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope. This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.     

Analysis and impact of process variability on performance of junctionless double gate VeSFET

This paper presents an in-depth analysis of junctionless double gate vertical slit FET (JLDG VeSFET) device under process variability. It has been observed that junctionless FETs (JLDG VeSFET) are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties. Sensitivity analysis reveals that the slit width, oxide thickness, radius of the device, gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage, on current, off current and subthreshold slope (Ssub) as compared to its junction based counterpart i.e. MOSFET, because various short channel effects are well controlled in this device. The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device. However, variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.     

Continuous model for gate-induced charge in short-channel MOSFETs

The threshold voltage in a short-channel MOS transistor is a sensitive function of the effective channel length, substrate bias and the channel impurity profile. A continuous model is developed in this letter to obtain a simple analytical expression for the above described sensitivities suitable for CAD program implementation. The calculated values for the threshold voltage are compared with the measurements on MOSFETs with effective channel lengths between 9.7 ?m and 1.2 ?m.     

自对准双扩散MOS器件的阈值电压分析

文章提出了精确描述自对准双扩散MOS器件阀值电压的解析模型，给出了其沟道中杂质的二维分布和源结耗尽层宽度的计算方法；分析了边缘效应对氧化层电容的影响，借助电荷共事模型，建立了反映非均匀沟道中耗尽层电荷变化及其对开启电压影响的阀值电压模型；同时，借助二维仿真器，计算出自对准双扩散MOS器件的阈值电压，其值与解析值相吻合。     

An analytical model for the narrow-width effect in ion-implanted MOSFETs

A closed-form analytical expression is derived to predict the threshold voltage of an ion-implanted narrow-width MOSFET. The method makes use of the Fourier transform to analyse the voltage distribution in the width cross section of the basic MOS device structure. No fitting parameter is necessary, but the dependence of threshold voltage on channel width and substrate bias thus obtained is in reasonable agreement with numerical results. The effects of peak doping, straggle and range of the implantation on the threshold voltage are also taken into account.     

A buried channel/surface channel CMOS IC isolated by an implanted silicon dioxide layer

The design and experimental results for a buried channel/ surface channel CMOS IC isolated by an implanted silicon dioxide layer are presented. A Poisson equation is used in proposing a threshold voltage model for a FET with metal-insulator-semiconductor-insulator-semiconductor (MISIS) structure. Good agreement between measured and calculated threshold voltage versus substrate voltage characteristics is obtained. The propagation delay for an inverter is 0.83 ns, which agrees with that from simulation.     

一种耗尽型短沟道MOS器件阈电压模型

本文研究了耗尽型MOS器件的短沟道效应,把Yau的电荷分配理论推广到耗尽型器件,并作了适当修正。提出一种简单而精确的耗尽型短沟道MOS器件阈电压分析模型,与实验数据吻合良好。该模型可以应用于这类器件及电路的CAD。