基于遗传算法的测试访问机制最优化

讨论了使测试访问机制最优化的几个问题,然后试着采用遗传算法来解决这些问题,在两个SoC上用遗传算法进行实验,把实验结果与采用整数线性规划方法(Integer Linear Programming,ILP)的结果进行比较可以发现效果改善的很明显。实验结果说明采用遗传算法对测试访问机制进行最优化处理的效果要好于ILP。     

嵌入式系统芯片级测试技术

针对目前流行的嵌入式芯片级测试技术,本文介绍了SoC测试技术的基本工作原理,利用93000 SoC测试系统,提出了相关测试内容、方法并得出最终测试结果.     

基于安全控制边界单元的IP核测试封装方法

为了解决测试信息传递的问题,IEEE组织推出了IEEE1500 IP(Intellectual Property)核测试封装标准以标准化口核测试接口.然而该标准给出的典型测试封装存在由测试数据扫描移人造成的不安全隐患.本文提出了一种基于安全控制边界单元的IP核测试封装方法.这种方法的核心思想是在典型的测试封装边界单元的...     

SoC测试结构复用技术研究

在设计基于IP模块的SoC同时,必须引入可测性设计以解决SoC的测试问题.为了简化SoC中的可测性设计的工作,本文设计了一种新型测试结构复用技术,通过分析SoC内部的各种测试应用情况,实现了一个兼容IEEE1149.1标准的通用测试访问逻辑IP.在运动视觉SoC中的应用以及仿真结果验证了这种测试复用结构的有效性,并有助于提高SoC的测试覆盖率.     

SOC测试结构优化研究

结合SOC测试结构的特点,采用量子进化算法对SOC测试结构进行优化.通过对量子进化算法中群体尺寸、旋转角度的合适设定,达到减少SOC测试所用时间的目的.针对国际SOC标准电路验证表明,与同类算法相比,该算法能够获得较短的测试时间.     

复用NoC测试IP芯核测试存取链优化配置

论述了层次型IP芯核不同测试模式之间的约束关系,给出了层次型IP芯核的测试壳结构,提出了一种复用片上网络测试内嵌IP芯核的启发式测试存取链优化配置方法.该方法可有效减小测试数据分组数量和被测芯核的测试时间.使用片上网络测试平台,在测试基准电路集ITC'02中的基准电路p22810上进行了实验验证.     

一种基于微处理器的SOC自测试方案

提出了一种基于片上微处理器和透明路径测试访问的SOC自测试方案。以片上微处理器为测试加载和响应收集比较的主体,构造透明路径并行传输测试数据,以嵌入程序控制测试过程。可以在提高测试速度的同时,降低对测试设备性能的依赖,并可以进行全速测试,所需额外面积开销较小。实验表明,该测试方案是有效的。     

模块结构的SOC集成电路测试系统

根据不完全的统计,从1980年代开始集成电路的工艺快速更新换代,集成度按摩尔定律每18个月增加一倍,此增长势头将会延续至2010年。相应生产每晶体管成本从0.5美分下降至200年的0.001美分,而测试每个晶体管成本只从0.4     

基于BIST的编译码器IP核测试

介绍了用于IP核测试的内建自测试方法（BIST）和面向测试的IP核设计方法,指出基于IP核的系统芯片（SOC）的测试、验证以及相关性测试具有较大难度,传统的测试和验证方法均难以满足。以编译码器IP核为例,说明了基于BIST的编译码器IP核测试的基本实现原理和具体实现过程,通过加入测试外壳实现了对IP核的访问、隔离和控制,提高了IP核的可测性。     

最新SOC测试的发展趋势

随着SOC芯片结构的复杂化，功能模块的多样化，SoC芯片的测试也面对诸多挑战，诸如测试资源和成本的兼顾。本文简单描述了现今SOC芯片的发展和趋势，以及相对应ATE测试系统的应对。     

一种基于数据总􀀂 线的测试结构

复用数据总线作为测试传输机构的测试结构可以大大减小可测性设计的面积开销。因此，提出了一种针对该结构的测试包设计新方法：通过对测试包中与测试传输机构相连的测试包单元和相连的测试包单元分别设计，使前者设计成可寻址的测试数据缓冲器，从而构建了一种复用数据总线作为测试传输机构的新测试结构。由此让该结构具备了硬件开销小，测试过程控制简单，可实现并行测试的优点。     

A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips

This paper deals with the design of SOC test architectures which are efficient with respect to required ATE vector memory depth and test application time. We advocate the usage of a TestRail Architecture, as this architecture, unlike others, allows not only for efficient core-internal testing, but also for efficient testing of the circuitry external to the cores. We present a novel heuristic algorithm that effectively optimizes the TestRail Architecture for a given SOC by efficiently determining the number of TestRails and their widths, the assignment of cores to the TestRails, and the wrapper design per core. Experimental results for four benchmark SOCs show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.     

基于网络通信架构的分布式测试系统

飞行试验具有试验强度高,测试参数多,测试、处理、监控与显示实时性高,试飞风险大,技术要求高等特点.如何满足现代技术条件下,对多测试系统之间数据传输的实时性与可靠性,是研究的重点.针对这种要求,专门研制了一套分布式飞行试验测试系统.系统采用分布式双光纤网络体系架构,结合数字视频组播、光传输时间码、NTP网络授时等技术,实...     

Multiple-Constraint Driven System-on-Chip Test Time Optimization

The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modular core-based SOCs where each module has its distinct tests, concurrent application of the tests can reduce the test application time dramatically, as compared to sequential application. However, when concurrent testing is used, resource conflicts and constraints must be considered. In this paper, we propose a test scheduling technique with the objective to minimize the test application time while considering multiple conflicts. The conflicts we are considering are due to cross-core testing (testing of interconnections between cores), module testing with multiple test sets, hierarchical conflicts in SOCs where cores are embedded in cores, the sharing of the TAM (test access mechanism), test power limitations, and precedence conflicts where the order in which tests are applied is important. These conflicts must be considered in order to design a test schedule that can be used in practice. In particular, the limitation on the test power consumption is important to consider since exceeding the system's power limit might damage the system. We have implemented a technique to integrate the wrapper design algorithm with the test scheduling algorithm, while taking into account all the above constraints. Extensive experiments on the ITC'02 benchmarks show that even though we consider a high number of constraints, our technique produces results that are in the range of results produced be techniques where the constraints are not taken into account.     

A Graph-Based Approach to Power-Constrained SOC Test Scheduling

The test scheduling problem is one of the major issues in the test integration of system-on-chip (SOC), and a test schedule is usually influenced by the test access mechanism (TAM). In this paper we propose a graph-based approach to power-constrained test scheduling, with TAM assignment and test conflicts also considered. By mapping a test schedule to a subgraph of the test compatibility graph, an interval graph recognition method can be used to determine the order of the core tests. We then present a heuristic algorithm that can effectively assign TAM wires to the cores, given the test order. With the help of the tabu search method and the test compatibility graph, the proposed algorithm allows rapid exploration of the solution space. Experimental results for the ITC02 benchmarks show that short test length is achieved within reasonable computation time.     

基于SCA无线通信系统的安全体系结构研究

采用软件无线电技术和模块化设计思路,构造新一代的无线通信系统,是无线通信发展的趋势。介绍了软件通信体系结构(SCA)的无线通信系统,描述了基于SCA无线通信系统的安全体系结构,详细分析了加密子系统、信息安全子系统和设备安全子系统。这样定义的安全体系结构保证了基于SCA无线通信系统实现不同的安全模式,提供不同的安全级别。     

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip

Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.     

基于外壳架构与测试访问机制的数字芯核可测试性设计

深亚徽米技术的应用以及芯核的嵌入性特点.使传统的测试方法不再能满足芯核测试的需要.IEEEStdl 500针对此问题提出了芯核的可测试性设计方案——外壳架构和测试访问机制.基于IEEE Stdl 500.以74373与741 38软梭为例,提出数字芯梭可测试性设计的方法,并通过多种指令仿真验证了设计的合理性;设计的TAM控制器复用JTAC-端口,节约了测试端口资源.提供了测试效率.