High-voltage 4H-SiC PiN diodes with the etched implant junction termination extension

This paper presents the design and fabrication of an etched implant junction termination extension(JTE) for high-voltage 4H-SiC PiN diodes. Unlike the conventional JTE structure, the proposed structure utilizes multiple etching steps to achieve the optimum JTE concentration range. The simulation results show that the etched implant JTE method can improve the blocking voltage of SiC PiN diodes and also provides broad process latitude for parameter variations, such as implantation dose and activation annealing condition. The fabricated SiC PiN diodes with the etched implant JTE exhibit a highest blocking voltage of 4.5 kV and the forward on-state voltage of 4.6 V at room temperature. These results are of interest for understanding the etched implant method in the fabrication of high-voltage power devices.     

SiC power Schottky and PiN diodes

The present state of SiC power Schottky and PiN diodes are presented in this paper. The design, fabrication, and characterization of a 130 A Schottky diode, 4.9 kV Schottky diode, and an 8.6 kV 4H-SiC PiN diode, which are considered to be significant milestones in the development of high power SiC diodes, are described in detail. Design guidelines and practical issues for the realization of high-power SiC Schottky and PiN diodes are also presented. Experimental results on edge termination techniques applied to newly developed, extremely thick (e.g., 85 and 100 μm) 4H-SiC epitaxial layers show promising results. Switching and high-temperature measurements prove that SiC power diodes offer extremely low loss alternatives to conventional technologies and show the promise of demonstrating efficient power circuits. At sufficiently high on-state current densities, the on-state voltage drop of Schottky and PiN diodes have been shown to be comparable to those offered by conventional technologies     

Device processing and characterisation of high temperature silicon carbide Schottky diodes

High temperature silicon carbide diodes with nickel silicide Schottky contacts were fabricated by deposition of titanium-nickel metal film on 4H-SiC epitaxial wafer followed by annealing at 550 °C in vacuum. Room temperature boron implantation have been used to form single zone junction termination extension. 4H-SiC epitaxial structures designed to have theoretical parallel-plain breakdown voltages of 1900 and 3600 V have been used for this research. The diodes revealed soft recoverable avalanche breakdown at voltages of 1450 and 3400 V, respectively, which are about 80% and 95% of theoretical values. I-V characteristics of fabricated 4H-SiC Schottky diodes have been measured at temperatures from room temperature up to 400 °C. The diodes revealed unchangeable barrier heights and ideality factors as well as positive coefficients of breakdown voltage.     

Analysis of bulk and surface components of leakage current in 4H-SiC PiN MESA diodes

The leakage current in circular- and ring-shaped epitaxial 4H-SiC PiN mesa diodes with different size and periphery to area ratios was evaluated under the influence of the UV irradiation and temperature in the range from room temperature (RT) to 250 °C. The surface leakage current component was found to dominate the reverse current characteristics and was found to be dependent on time and temperature both after reactive ion etching (RIE) of the diodes in the SF₆/Ar gas mixture and after the UV irradiation. Charging of the surface states is believed to be responsible for the observed behavior. The UV irradiation is believed to charge the surface positively. The drift of the I(V) characteristics is due to the trapping of the electrons neutralizing the positive donor states.     

对拥有结终端保护的高压4H-SiC PIN二极管的研究

在对4H-SiC高压PIN二极管进行了理论分析的基础上,利用仿真软件ISE10.0对具有结终端保护的高压4H-SiC PIN二极管耐压特性进行了模拟仿真计算,并取得了很多有价值的计算结果。利用平面制造工艺,结合仿真提取的参数,试制了高压4H-SiC PIN二极管。实验测试结果表明,仿真计算的结果与实际样品测试的数据一致性较好,实测此器件击穿电压值已达到1 650V。     

一种带P型埋层的4H-SiC PiN二极管

碳化硅(SiC)PiN二极管是应用在高压大功率整流领域中的一种重要的功率二极管。受SiC外延材料的载流子寿命限制以及常规SiC PiN二极管较低的阳极注入效率的影响,SiC PiN二极管的正向导通性能较差,这极大限制了其在高压大电流领域的应用。文章提出了一种带P型埋层的4H-SiC PiN二极管,较常规SiC PiN二极管增强了阳极区的少子注入效率,降低了器件的导通电阻,增大了正向电流。仿真结果表明,当正向偏压为5 V时,引入P型埋层的SiC PiN二极管的正向电流密度比常规SiC PiN二极管提升了52.8%。     

Influence of Temperature on Shockley Stacking Fault Expansion and Contraction in SiC PiN Diodes

While Shockley stacking fault (SSF) creation and expansion within 4H-SiC bipolar devices is well known, only recently was it observed that this expansion and the associated increase in the forward voltage drop (V _f) could be completely reversed via low-temperature annealing. Here we report the temperature dependence of the recovery rate of the V _f drift via annealing, reporting an activation energy of 1.3 ± 0.3 eV. The V _f drift was observed to saturate following extended electrical stressing, and it was observed that the value of V _f at this saturation was inversely proportional to the stressing temperature. We also observed that SSF and V _f drift recovery could occur in highly stressed diodes at elevated temperatures even under high current injection conditions (14 A/cm²).     

Fabrication of SiC lateral super junction diodes with multiple stacking p- and n-layers

Using epitaxial multiple p-n junction structures of 4H-SiC, lateral super junction diodes were fabricated for the first time. The breakdown voltage of the device was 400 V, which is more than 3/spl times/ higher than the theoretical value calculated for a device with uniformly-doped drift layer (130 V), indicating the effective operation of the super junction structure.     

8.5 m/spl Omega/ /spl middot/ cm/sub 2/ 600-V double-epitaxial MOSFETs in 4H-SiC

The most important issue in realizing a 4H-SiC vertical MOSFET is to improve the poor channel mobility at the MOS interface, which is related to high on-resistance. This letter focuses on a novel 4H-SiC vertical MOSFET device structure where a low acceptor concentration epitaxial layer is used as a channel. We call this structure a double-epitaxial MOSFET (DEMOSFET). In the structure, the p-well is composed of two p-type epitaxial layers, while an n-type region between the p-wells is formed by low-dose n-type ion implantation. A buried channel is formed at the surface of the upper p/sup $/epitaxial layer. A fabricated DEMOSFET showed an on-resistance of 8.5 m/spl Omega//spl middot/cm/sup 2/ at a gate voltage of 15 V and a blocking voltage of 600 V. This on-resistance is the lowest so far reported for a vertical MOSFET with a blocking voltage of 600 V.     

Fabrication and characterization of 4H-SiC P-N junction diodes by selective-epitaxial growth using TaC as the mask

Selective nitrogen doping of 4H-SiC by epitaxial growth using TaC as the high-temperature mask has been demonstrated. Nomarski optical microscopy and scanning electron microscopy (SEM) were used to characterize selective growth of SiC. In addition, 250-μm, square-shaped, p-n junction diodes by selective n-type epitaxial growth on a p-type epilayer were fabricated. The refilled fingers with different width were designed to vary the periphery/area (P/A) ratio. The effects of P/A ratio on the current-voltage (J-V) characteristics have been investigated. The ideality factor extracted from J-V characteristics is ≈2 at a temperature range of 25–275°C, which indicates that the Shockley-Read-Hall recombination is the dominant mechanism in the conduction region. The reverse leakage current does not show dependence on P/A ratio for trench-refilled diodes. The room-temperature reverse leakage-current density at 100 V is less than 3.5×10⁻⁷ A/cm² for all diodes. Also, the reverse leakage current does not increase significantly with temperature up to 275°C. The breakdown voltages measured at room temperature are about 450 V and 400 V for diodes without and with fingers, respectively.     

Intrinsic 4H-SiC parameters study by temperature behaviour analysis of Schottky diodes

The main intrinsic parameters in silicon carbide material are not exhaustively studied up to now. An experimental study of the behaviour of electrical parameters of Schottky barrier diodes (SBD) fabricated on the Si face of 4H-SiC epitaxial layers with respect to temperature is shown. Analysed devices present an electrical behaviour in accordance to thermoionic emission and a good metal-semiconductor interface uniformly confirmed by capacitance/voltage measurements (C-V). Current/voltage measurements (I-V) have been performed in a large temperature range and lead to an evaluation of the Richardson constant.     

Improvements of the SiC homoepitaxy process in a horizontal cold-wall CVD reactor

In this research effort, we investigate the influence of the cold-wall reactor geometry on the chemical vapor deposition (CVD) growth process of 4H-SiC and the quality of lightly doped epitaxial layers. Stable growth conditions with respect to growth rate and C/Si ratio of the gas-phase can be achieved by the appropriate choice of the distance between susceptor and walls of the inner quartz tube. A background doping concentration in the range of 10¹⁴ cm⁻³ is realized by employing a high temperature stable and hydrogen etch resistant coating of the graphite susceptor. Doping and thickness homogeneity of epitaxial layers on 35 mm diam. 4H-SiC substrates, expressed by σ/mean, are as low as 6.9 and 7.7%, respectively. From deep level transient spectroscopy measurements, the concentration of the frequently reported intrinsic Z₁-center in 4H-SiC is determined to be below the detection limit of 10¹² cm⁻³.     

Simulation and Experimental Study on the Junction Termination Structure for High-Voltage 4H-SiC PiN Diodes

Designing and fabrication of 10-kV 4H-SiC PiN diodes with an improved junction termination structure have been investigated. An improved bevel mesa structure and a single-zonejunction termination extension (JTE) have been employed to achieve a high breakdown voltage $(geq!hbox{10} hbox{kV})$ . The improved bevel mesa structure, nearly a vertical sidewall at the edge of the p-n junction and a gradual slope at the mesa bottom, has been fabricated by reactive ion etching. The effectiveness of the improved bevel mesa structure has been experimentally demonstrated. The JTE region has been optimized by device simulation, and the JTE dose dependence of the breakdown voltage has been compared with experimental results. A 4H-SiC PiN diode with a JTE dose of $hbox{1.1} times hbox{10}^{13} hbox{cm}^{-2}$ has exhibited a high blocking voltage of 10.2 kV. The locations of electric field crowding and breakdown are also discussed.      

Normally-off trench JFET technology in 4H silicon carbide

A double gate normally-off silicon carbide (SiC) trench junction field effect transistors (JFET) design is considered. Innovative migration enhanced embedded epitaxial (ME³) growth process was developed to replace the implantation process and realize high device performance. Strong anisotropic behavior in electrical characteristics of the pn junction fabricated on (1 1 −2 0) and (1 −1 0 0) trench a-planes was observed, although quality of the pn diodes was found to be independent of trench plane orientations. Fabricated normally-off trench 4H-SiC JFET demonstrates the potential for lower specific on-resistance (R_onS) in the range of 5-10 mΩ cm² (1200 V class). A relative high T^−2.6 dependence of R_onS is observed. A breakdown voltage of 400 V in the avalanche mode was confirmed at zero gate bias conditions for cell design without edge termination. It was demonstrated that the normally-off JFETs are suitable for high temperature applications. Average temperature coefficient of threshold voltage (V_th) was calculated as −1.8 mV/°C, which is close to the MOS based Si power devices.     

Thermal Annealing and Propagation of Shockley Stacking Faults in 4H-SiC PiN Diodes

Stacking faults within 4H-SiC PiN diodes are known to be detrimental to device operation. Here, we present electroluminescence (EL) images of 4H-SiC PiN diodes providing evidence that electrically and optically stimulated Shockley stacking fault (SSF) propagation is a reversible process at temperatures as low as 210°C. Optical beam induced current (OBIC) images taken following complete optical stressing of a PiN diode and that lead to a small number of completely propagated SSFs provide evidence that such defects propagate across the n–/p+ interface and continue to grow throughout the p+ layer. These observations bring about questions regarding the validity of the currently accepted driving force mechanism for SSF propagation.     

The magnetic field dependence of R0A products in n-on-p homojunctions and p-on-n heterojunctions from Hg0.78Cd0.22Te liquid phase epitaxy films

The analysis of R₀A products as a function of magnetic field in n-on-p diodes using a simple diffusion current model has previously been shown to yield both J_ep/J_total ratio (the relative contribution of the p-side diffusion current) and μ_ep (the minority carrier, electron mobility). In this paper, we report the good agreement between the experimental and theoretical dependence of μ_ep on the hole concentration over a wide range between 1 x 10¹⁶ and 4 x 10¹⁷ cm⁻³ in n-on-p homojunction diodes fabricated on undoped p-type Hg_0.78Cd_0.22Te liquid phase epitaxial (LPE) films. The averaged J_ep/J_total ratio varied between 68 and 90% with the hole concentration. These J_ep/J_total ratios indicate that other leakage current mechanisms than the p-side diffusion current were not negligible. Also, for the first time, comparative measurements were made on p⁺/n heterojunction diodes consisting of As-doped Hg_0.07Cd_0.30Te and In-doped Hg_0.78Cd_0.22Te LPE layers. Unlike a typical change in R₀A products by a factor of 2–3 in n-on-p homojunction diodes, the R₀A products in p⁺/n heterojunction diodes at 7 kG were typically only 2–3% higher than that at the zero field. The typical J_ep/J_total ratio in p⁺/n heterojunction diodes was about 3–4 %, which confirms the general belief that the p⁺ cap layer, due to the high doping and a larger bandgap, contributes very little to the total leakage current.     

Correlation between the electrical properties and the interfacial microstructures of TiAl-based ohmic contacts to p-type 4H-SiC

In order to understand a mechanism of TiAl-based ohmic contact formation for p-type 4H-SiC, the electrical properties and microstructures of Ti/Al and Ni/Ti/Al contacts, which provided the specific contact resistances of approximately 2×10⁻⁵ Ω-cm² and 7×10⁻⁵ Ω-cm² after annealing at 1000°C and 800°C, respectively, were investigated using x-ray diffraction (XRD) and high-resolution transmission electron microscopy (HRTEM). Ternary Ti₃SiC₂ carbide layers were observed to grow on the SiC surfaces in both the Ti/Al and the Ni/Ti/Al contacts when the contacts yielded low resistance. The Ti₃SiC₂ carbide layers with hexagonal structures had an epitaxial orientation relationship with the 4H-SiC substrates. The (0001)-oriented terraces were observed periodically at the interfaces between the carbide layers and the SiC, and the terraces were atomically flat. We believed the Ti₃SiC₂ carbide layers primarily reduced the high Schottky barrier height at the contact metal/p-SiC interface down to about 0.3 eV, and, thus, low contact resistances were obtained for p-type TiAl-based ohmic contacts.     

The planar 6H-SiC ACCUFET: a new high-voltage power MOSFETstructure

A novel planar accumulation channel SiC MOSFET structure is reported in this paper. The problems of gate oxide rupture and poor channel conductance previously reported in SiC UMOSFETs are solved by using a buried P⁺ layer to shield the channel region. The fabricated 6H-SiC unterminated devices had a blocking voltage of 350 V with a specific on-resistance of 18 mΩ.cm² at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 2.5× of the value calculated for the epitaxial drift region (10¹⁶ cm^-3, 10 μm), which is capable of supporting 1500 V     

The growth of Magnesium-doped GaAs by the Om-Vpe process

Magnesium-doped GaAs has been grown by organometallic vapor phase epitaxy (OM-VPE). Bis (cyclopentadienyl) mag-nesium (Cp₂Mg) is used as the organometallic precursor to Mg. The epitaxial layers have been characterized by resis-tivity and Hall measurements, photoluminescence spectro-scopy and optical microscopy. The material is of high electrical and optical quality; controllable doping over the range 10¹⁵ to 10¹⁹cm^-3 is reproducibly attained. The ionization energy of the Mg acceptor is determined to be 30 ± 2.5 meV at 77K. Negligible compensation is observed, consistent with clean thermolysis of the Cp₂Mg under growth conditions. GaAs diodes have been fabricated using Mg as the p-dopant and either Se, Si, or Sn as the n-dopant. The diodes show very low leakage currents under reverse bias, even at relatively high doping levels. Degenerately-doped junctions for interconnecting monolithic cascade concentrator solar cells have also been successfully grown, displaying forward conductivities as high as 19 amps V⁻¹ cm^-2 at 0.05V forward bias.     

A Comparison of the Microwave Photoconductivity Decay and Open-Circuit Voltage Decay Lifetime Measurement Techniques for Lifetime-Enhanced 4H-SiC Epilayers

This work compares the optical microwave photoconductivity decay (μPCD) and electrical open-circuit voltage decay (OCVD) techniques for measuring the ambipolar carrier lifetime in 4H-silicon carbide (4H-SiC) epitaxial layers. Lifetime measurements were carried out by fabricating P⁺/intrinsic/N⁺ (PiN) diodes on 100-μm-thick, 1 × 10¹⁴ cm^?3 to 4.5 × 10¹⁴ cm^?3 doped N-type 4 H-SiC epilayers, and measuring the lifetime optically using μPCD prior to metallization, then electrically using OCVD after contact deposition. Both as-grown epilayers as well as epilayers with improved lifetime (via thermal oxidation) were measured using both techniques. The observed ambipolar lifetime was improved from 1.4 μs on an unenhanced wafer to 4 μs on a wafer enhanced through the oxidation process as measured by μPCD. Little difference was observed between the μPCD and OCVD measurements on the unenhanced wafer; the ambipolar lifetime on the enhanced wafer measured by OCVD was approximately 5.5 μs, or 1.5 μs higher than the μPCD measurement. Continuous evaluation of the OCVD transient waveform was necessary due to the high lifetime in the enhanced wafer; shunt resistances included to discharge the P⁺/N junction capacitance were found to damp the OCVD response and yield low values for the measured lifetime. Simulation of the μPCD measurement including various surface recombination conditions yielded a good match to experimentally observed μPCD measurements for high values of the surface recombination velocity. The OCVD lifetime measurement technique is expected to yield measured lifetime values closer to the physical value due to its independence from surface conditions, provided that the experimental conditions are appropriately chosen.