A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesiser

A 2.4 GHz 6.6 mA fully differential CMOS phase-locked loop (PLL) frequency synthesiser with an on-chip capacitance-calibrated loop filter is presented. The frequency synthesiser includes a differential-tuning voltage-control oscillator (VCO) and a fully differential charge-pump (CP) to reject the common-mode noise. A combination of analogue tuning and digital tuning techniques (4-bit binary weighted capacitor array) is utilised to extend the tuning range of the VCO. A novel topology and an optimisation strategy are utilised to reduce the power consumption of the frequency divider. The capacitance in the loop filter is on-chip calibrated so that the loop dynamic characteristics are accurately controlled despite the process variation. The frequency synthesiser has been implemented in UMC 0.18 μm CMOS. The measured results show that the VCO achieves a 29% tuning range, from 2.056 to 2.758 GHz. The phase noise of the frequency synthesiser is ? 117.2 dBc/Hz at 1 MHz frequency offset from the 2.3 GHz carrier. The settling time is less than 50 μs, and the capacitance in the loop filter could be on-chip calibrated to ±3.9% precision. The whole frequency synthesiser only consumes 6.6 mA current from a 1.8 V power supply.     

A low-cost, wide-band DCO with an on-chip 3-D solenoid inductor in 0.13 μm digital CMOS

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 μm digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 μm process and the die area of the solenoid inductor is 0.013 mm². The DCO tuning range is about 52 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is ?110.17 dBc/Hz at 1 MHz offset.     

A Reconfigurable Low-Noise Amplifier Using a Tunable Active Inductor for Multistandard Receivers

A reconfigurable low-noise amplifier (LNA) based on a high-value active inductor (AI) is presented in this paper. Instead of using a passive on-chip inductor, a high-value on-chip inductor with a wide tuning range is used in this circuit and results in a decrease in the physical silicon area when compared to a passive inductor-based implementation. The LNA is a common source cascade amplifier with RC feedback. A tunable active inductor is used as the amplifier output load, and for input and output impedance matching, a source follower with an RC network is used to provide a 50 Ω impedance. The amplifier circuit has been designed in 0.18 µm CMOS process and simulated using the Cadence Spectra circuit simulator. The simulation results show a reconfigurable frequency from 0.8 to 2.5 GHz, and tuning of the frequency band is achieved by using a CMOS voltage controlled variable resistor. For a selected 1.5 GHz frequency band, simulation results show S ₂₁ (Gain) of 22 dB, S ₁₁ of ?18 dB, S ₂₂ of ?16 dB, NF of 3.02 dB, and a minimum NF (NFmin) of 1.7 dB. Power dissipation is 19.6 mW using a 1.8 V dc power supply. The total LNA physical silicon area is (200×150) µm².     

A superheterodyne receiver front-end with on-chip automatically Q-tuned notch filters

A superheterodyne receiver front-end with on-chip automatically Q-tuned notch filters is proposed. The front-end includes a differential LNA and a Gilbert down-converter, where each block is coupled with an on-chip image-rejection notch filter to get high image-rejection ratio. Each notch filter is formed by one on-chip LC network and one negative-resistance cross-coupled pair to compensate for the loss of the LC network. The current through the cross-coupled pairs is automatically adjusted by an automatic Q tuning circuit so that the loss of the notch filter is perfectly compensated to achieve a deepest notch. The automatic Q tuning circuit is an analog?Cdigital mixed signal circuit, and successive approximation register algorithm is used to search for the optimum current value. The superheterodyne receiver front-end has been implemented in 0.18???m CMOS. Experimental results show that the circuit could achieve an image rejection ratio of 75?dB with 105?MHz IF Frequency. The LNA draws 5.86?mA current, and the down-converter draws 1.27?mA current while two image-rejection filters and the master VCO totally draw 363???A current, all from a 1.8?V power supply.     

A wide-bandwidth PSR-enhanced low-dropout regulator using a bandpass feedforward supply ripple rejection circuit

A low-dropout regulator with a wide-bandwidth feedforward supply noise cancellation path for enhancing supply noise rejection at middle-to-high frequency is presented in this paper. This idea has been realized by a bandpass filter and a signal-nulling technique with the help of a voltage buffer. For the PSR filter design, the total on-chip capacitance is about 18.75 pF. This circuit has been implemented in a 0.35 µm CMOS process and occupies an active chip area of 0.062 mm². From the experimental results, the proposed LDO can operate with nominal dropout voltage of 200 mV at maximum load of 25 mA and quiescent current of 26 μA. It achieves a power-supply rejection better than ?59 dB up to 10 MHz with a 4 μF output capacitor.     

A calibration-less low error two-point modulation transmitter for 802.15.4 application

A low power phase locked loop (PLL) based transmitter for wireless sensor application is presented in this paper. The transmitter adopts two-point modulation architecture in high-pass and low-pass paths of PLL; it modulates the divide ratio through sigma-delta modulator and voltage controlled oscillator (VCO) frequency tuning port simultaneously. An interleave-biased varactor pair is used to linearize the frequency tuning curve of the VCO. Besides, to achieve the desired frequency deviation of 500 kHz, we use a capacitance desensitization technique through combined parallel and serial capacitances with tuning varactors. This topology does not need the minimum size varactor, which is sensitive to process variation and mismatch. Implemented in standard 0.18-μm CMOS process, the transmitter achieves a 5.2 % FSK error for 2 Mbps data rate without using any auto-calibration circuit, consuming 7.8 mW power. Loop filter and crystal are the only off-chip components.     

片上自动调谐的可编程有源RC滤波器

研制了一款可编程6阶巴特沃斯有源RC滤波器.为提高滤波器中运算放大器的增益带宽积,设计了一种新型的前馈补偿运算放大器.为消除工艺偏差和环境变化对截止频率的影响,设计了一种片上数字控制频率调谐电路,并采用TSMC 0.18 μm CMOS工艺进行了流片.滤波器采用低通滤波结构,测试结果表明,3 dB截止频率为1～32 MHz,步进1 MHz,带内增益0 dB,带内纹波0.8 dB,2倍带宽处带外抑制不小于24 dBc,5倍带宽处带外抑制不小于68 dBc,滤波器等效输入噪声为340 nV/√Hz@1MHz,调谐误差为±3％.滤波器裸芯片面积0.87 mm×1.05 mm.采用1.8V电源电压,滤波器整体功耗小于20 mW.     

A ±1.5-V, 4-MHz CMOS continuous-time filter with asingle-integrator based tuning

A 4-MHz, fifth-order elliptic low-pass Gm-C filter is described whose characteristics are tuned by an on-chip automatic tuning circuit. The tuning circuit uses only one integrator as the master of tuning instead of problematic voltage controlled oscillator (VCO) and voltage controlled filter (VCF). MOS transistors in linear operation region perform the voltage-to-current conversion in an operational transconductance amplifier, and thereby we achieved ±1.5 V operation. A prototype filter was implemented in a 0.8-μm double-poly, double-metal CMOS process. The filter exhibits the dynamic range of 57.6 dB and dissipates 10 mW with ±1.5-V supply. The stopband attenuation is better than 45.0 dB and the passband ripple is smaller than 1.0 dB     

A compact ADPLL based on symmetrical binary frequency searching with the same circuit

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη (MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δη of the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm², which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δη is not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter.     

A flicker-free CMOS LED driver control circuit for visible light communication enabling concurrent data transmission and dimming control

Recent breakthroughs in solid-state lighting technology have opened the door to a variety of applications using light-emitting diodes (LED’s) for not only illumination, but also optical wireless communication. Low-power CMOS technology enables realization of system-on-chip driver circuits integrating multiple functions to control LED device performance, luminance, and data modulation for “intelligent” visible light networking. This paper presents an LED driver circuit architecture, incorporating analog and digital circuit blocks to deliver concurrent dimming control, and data transmission. This is achieved by independent control of output voltage and current using buck converter and current control loops, respectively. This integrated system incorporates the feedback mechanisms to provide uniform light output together with the peak current control, which also prevents flickering. The proposed architecture is flexible enough to take any digital base band modulation format. Designed and implemented in a 180 nm CMOS process, it provides linear 10–90 % dimming control while transmitting data. It also introduces a mechanism which can be applied to the off-the-shelf LED drivers and make them applicable for the visible light communication applications. The power consumption of on-chip circuitry, is negligible compared to the overall power consumption which yields an efficiency of 89 % at 120 mA of load current. The measured bit error rate (BER) varies from 10^?6 at the data rate of 2.5 Mbps to 10^?2 at the data rate of 7 Mbps. All control functions integrated on-chip with the total power consumption of 5 mW.     

A CMOS transconductance amplifier architecture with wide tuningrange for very low frequency applications

A pseudodifferential CMOS operational transconductance amplifier (OTA) with wide tuning range and large input voltage swing has been designed for very small G_M's (of the order of a few nanoamperes per volt). The OTA is based on a modified four-quadrant multiplier architecture with current division. A common-mode feedback circuit structure has been proposed and designed using floating-gate transistors to handle large differential signals. Large on-chip capacitors are emulated through impedance scaling circuits. The circuits, fabricated in a 1.2-μm CMOS process, have been used to design a fourth-order bandpass filter and a relaxation oscillator. Experimental results are in good agreement with the theoretical results     

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm², which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.     

10 Gb/s adaptive receive-side merged near-end and far-end crosstalk cancellation circuitry in 65 nm CMOS

Crosstalk between neighboring channels can have significant impact on system bit-error rate (BER) as serial I/O data rates scale above 10 Gb/s. This paper presents receive-side circuitry which merges the cancellation of both near-end and far-end crosstalk (NEXT/FEXT) and can automatically adapt to different channel environments and variations in process, voltage, and temperature. NEXT cancellation is realized with a novel 3-tap FIR filter which combines two traditional FIR filter taps and a continuous-time band-pass filter IIR tap for efficient crosstalk cancellation, with all filter tap coefficients automatically determined via an on-die sign–sign least-mean-square (SS-LMS) adaptation engine. FEXT cancellation is realized by coupling the aggressor signal through a differentiator circuit whose gain is automatically adjusted with a power-detection-based adaptation loop. A prototype fabricated in a general purpose 65-nm CMOS process includes the adaptive NEXT and FEXT circuitry, along with a continuous-time linear equalizer (CTLE) to compensate for frequency-dependent channel loss. Enabling the crosstalk cancellation circuitry while operating at 10 Gb/s over coupled 4-in FR4 transmission line channels with NEXT and FEXT aggressors opens a previously closed eye and allows for a 0.2 UI timing margin at a BER = 10^?9. Total power including the NEXT/FEXT crosstalk cancellation circuitry, CTLE, and high-speed output buffer is 34.6 mW, and the core circuit area occupies 0.3 mm².     

具有片上频率自动调谐功能的4MHz Gm-C滤波器

本文实现了一个应用于全集成L带DAB接收机的5阶Gm-C椭圆低通滤波器,该滤波器上集成了基于锁相环的片上频率自动调谐电路,使得该滤波器的截止频率可以准确控制在4MHz.该滤波器已经采用0.35μm CMOS工艺实现.测试结果表明,该滤波器的频率精度可以控制在1%以内,动态范围约为54dB,阻带抑制率大于40dB.该滤波器采用3.3V电源,消耗的电流约为13mA.     

一种面向多标准无线收发器的低功耗宽调谐范围基带滤波器设计

本论文提出了一种面向多标准收发器的具有精确片上调谐电路的低功耗宽调谐范围基带滤波器。设计的滤波器是由三级Active-Gm-RC类型的双二次单元级联组成的六阶巴特沃斯低通滤波器。采用改进的线性化技术来提高低通滤波器的线性度。论文提出了一种新的匹配性能与工艺无关的跨导匹配电路和具有频率补偿的频率调谐电路来增加滤波器的频率响应精度。为了验证设计方法的有效性,采用标准的130nm CMOS工艺对滤波器电路进行流片。测试结果表明设计的低通滤波器带宽调谐范围为0.1MHz-25MHz,频率调谐误差小于2.68%。滤波器在1.2V的电源电压下,功耗为0.52mA到5.25mA,同时取得26.3dBm的带内输入三阶交调点。     

A 4-MHz CMOS continuous-time filter with on-chip automatic tuning

A third-order elliptic low-pass continuous-time filter with a 4-MHz cutoff frequency, integrated in a 3-μm p-well CMOS process, is presented. The design procedure is based on the direct simulation of a doubly terminated LC ladder filter by capacitors and fully balanced, current-controlled transconductance amplifiers with extended linear range. The on-chip automatic tuning circuit uses a phase-locked loop implemented with an 8.5-MHz controlled oscillator that matches a specific two-integrator loop of the filter. The complete circuit features 70-dB dynamic range (THD<-50 dB) and consumes only 16 mW from ±2.5-V supplies     

A digitally controlled on-chip monotonic reference current generator with low LSB current for fast and accurate optical level monitoring

This paper describes a digitally controlled on-chip monotonic Reference Current Generator (RCG) with 8-bit resolution and a LSB (Least Significant Bit) current as low as 100 nA. It was designed as a building block of a generic DC-coupled Burst Mode Laser Diode Driver (BM-LDD) for GPON (Gigabit Passive Optical Network) applications and acts as an on-chip RCG with a settling time of 18 ns for fast and accurate optical level monitoring with guaranteed monotony. The proposed architecture of the on-chip RCG is based on an 8-bit segmented current-steering Digital-to-Analog Converter (IDAC) and a bandgap voltage reference. The (3 + 5) segmented architecture of the 8-bit IDAC is an optimum combination of a 3-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 5-bit LSBs binary-weighted sub-DAC offering good DNL (Differential Nonlinearity) performance. The bandgap voltage reference deviates only 0.6% of the nominal value over temperature and power supply variations. A cascade current mirror with a super beta helper circuit is used to guarantee monotony and high accuracy. The linearity errors caused by systematic influences and random variations are reduced by the proposed 2-D double centroid symmetrical architecture. Experiments confirm a DNL of ±0.5 LSB for the proposed RCG. The tested performance of optical level monitoring and APC (Automatic Power Control) algorithm is compliant to ITU-T GPON standards. The design was realized in a 0.35 μm SiGe BiCMOS technology with 3.3 V power supply. The technology choice was made by heavy requirements of the innovative DC-coupled 1.25 Gbit/s BM-LDD chip. Although the proposed structure was designed as a building block for a BM-LDD chip, the design concept can be applied for developing other high linearity on-chip RCG for a wide junction temperature range (?40 to 110°C).     

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm². The receiver achieves S11 input matching below ?10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.     

A widely tunable continuous-time LPF for a direct conversion DBS tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in 0.35μm SiGe BiCMOS technology. The filter's -3 dB cutoff frequency f0 can be tuned from 4 to 40 MHz. A novel on-chip automatic tuning scheme has been successfully realized to tune and lock the filter's cutoff frequency. Measurement results show that the filter has -0.5 dB passband gain, +/- 5% bandwidth accuracy, 30 nV/Hz1/2 input referred noise, -3 dBVrms passband IIP3, and 27 dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 13 mA (with f0 = 20 MHz) from 5 V supply, and occupy 0.5 mm2.     

A Zero-Pole Reposition Based, 0.95-mW, 68-dB,Linear-in-dB,Constant-Bandwidth Variable Gain Amplifier

A variable-gain amplifier with very low power consumption and wide tuning range is presented. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by simulation in TSMC 0.18-μm N-well CMOS fabrication process. Owing to the novel zero-pole repositioning technique, the proposed circuit demonstrates very high frequency bandwidth of 79 MHz while drawing only 0.52 mA from 1.8 V power supply. The interesting results such as a very small core area of about 0.0025 mm² as well as a wide linear-in-dB and constant-bandwidth tuning range of 68.2 dB along with a very low power consumption of 0.95 mW are achieved utilizing standard CMOS technology. The stability of the proposed VGA is verified through transient sinusoidal response analysis. Full process, voltage and temperature (PVT) variation analysis of the circuit is also investigated through Monte Carlo and corner case analysis in order to approve the robustness of the structure. Monte Carlo simulations show standard deviation values of 4.6 dB and 78.3 MHz in gain and gain-bandwidth product, respectively. These results show that our zero-pole repositioning method would lend itself well for use in low-power and high-frequency applications, especially in high-speed automatic gain control amplifiers.