A 0.03 mm2 delta-sigma modulator with cascaded-inverter amplifier

A single stage inverter is introduced as a replacement for the conventional OTA to implement an inverter-based delta-sigma modulator. It achieves a high power and area efficiency. However, the low DC-gain and gain-bandwidth (GBW) have limited the application. This paper proposes a cascaded-inverter to increase the DC-gain and GBW, while maintaining the advantages of power and area efficiency. By cascading three inverters, the DC-gain is increased from 44 dB to 82 dB, and the GBW is increased from 100 MHz to 697 MHz. A third-order delta-sigma modulator using the proposed cascaded-inverter has been fabricated in a 0.11-μm CMOS process. When operating from a 1.2-V supply and clocked at 80 MHz, the prototype modulator achieves 59.4-dB peak SNDR over 500-kHz signal bandwidth while consuming 249 μW. Measurement results demonstrate that the application of the inverter-based amplifier, which is becoming popular due to its high power efficiency, can be extended to significantly higher speed circuits     

A delta-sigma modulator for a 1-bit digital switching amplifier

A seventh-order single-loop single-bit delta-sigma modulator for a 1-bit digital audio switching amplifier is presented. To achieve high SNR and ensure the modulator stability for a large input range, the positions of the modulator loop filter poles and zeros are optimized, and a feedback comparator is used. A test chip was fabricated in a 0.35-/spl mu/m CMOS process with optional 5-V transistors. The modulator achieves an SNR of 111 dB and 0.0015-% THD+N over the audio band. The normalized maximum allowable input range is 0.89. There are two modulators on one chip, one for each left and right audio channel. The isolation between both channels is over 135 dB. The chip area is 12.6 mm/sup 2/ and it draws 60 mA from a 5-V supply.     

Wideband cascade delta-sigma modulator with digital correction forfinite amplifier gain effects

The authors present an alternative approach to reducing the effects of finite amplifier open-loop gain in cascade delta-sigma modulators. The proposed gain compensation is carried out in the digital domain and thus requires no additional analogue circuitry. The method is illustrated by the example of a double third-order cascade circuit which, when properly compensated for finite gain effects, can yield 1-20 bit resolution with oversampling ratios as low as 16-24     

A novel low-voltage operational amplifier for low-power pipelined ADCs

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.     

一种用于低功耗流水线模数转换器的新型低电压运算放大器

本文提出一种新型适用于低电压的两级运算放大器。该放大器采用电平平移技术和电流镜镜像技术分别在第一级和第二级实现CLASS-AB偏置,在相同的电流消耗下,有效输入跨导相对传统的两级运放提高了一倍,从而实现了低功耗、大带宽、建立时间短的目标。采用嵌套米勒补偿技术和对称结构的共模反馈电路,运放在动态工作时可以达到很好的稳定性。在1.2伏的电源电压、0.18微米CMOS工艺下,该运放用于12位40兆赫兹采样频率的流水线模数转换器前端采样保持中,仿真结果显示,采样保持电路的无杂散动态范围达到95.7dB,总谐波失真-94.3dB,信噪失真比达到89.5dB,功耗仅为5.8毫瓦。     

Inductance simulation with a single differential-input operational amplifier

On combining the functions of negative-immittance conversion and positive-immittance inversion in a combined invertor/convertor stage of bridge configuration, a realisation of pure inductance has been achieved using a single operational amplifier of the differential-input type. On modifying the parameters, a grounded series LC branch may be obtained and used as a notch filter.     

A low-voltage switched-current delta-sigma modulator

This paper presents the design of a fully differential switched-current delta-sigma modulator using a single 3.3-V power-supply voltage. At system level, we tailor the modulator structure considering the similarity and difference of switched-capacitor and switched-current realizations. At circuit level, we propose a new switched-current memory cell and integrator with improved common mode feedback, without which low power-supply-voltage operation would not be possible. The whole modulator was implemented in a 0.8-μm double-metal digital CMOS process. It occupies an active area of 0.53×0.48 mm² and consumes a current of 0.6 mA from a single 3.3-V power supply. The measured dynamic range is over 10 b     

低压低功耗运算放大器结构设计技术

低电压、低功耗、动态摆幅达到轨到轨（Rail—to—Rail）的运放是实现SOC设计的核心，而相关的输入输出模块是其中的关键技术。本文分析了两种分别工作于弱反型区和强反型区的恒跨导Rail—to—Rail输入级，同时给出了低压和极低压下两种AB类控制输出级的实现方案，并对各方案进行了比较和总结。     

A novel sine-wave generator using a single operational amplifier

A new realization of a variable frequency active RC oscillator using a single operational amplifier is given. The frequency variation is obtained by controlling a single grounded capacitor in the network.     

Single-loop delta-sigma modulator with swing suppression

A single-loop higher-order delta-sigma modulator with a new loop topology is presented. The loop-filter is composed of both feedback and feedforward paths. No active summing element is required in the modulator implementation. The modulator has low integrator output swings and a high input dynamic range, resulting in relaxed op-amp requirements even for low-voltage operation. Simulation results of a fourth-order modulator having the proposed loop filter are also given     

A noise-shaped switching power supply using a delta-sigma modulator

A technique to reduce in-band tones in switch-mode power supplies is described. It takes advantage of the noise-shaping properties of the delta-sigma (/spl Delta//spl Sigma/) modulator to eliminate the spikes normally present in switching power supplies. A framework is introduced for comparing the conventional pulsewidth modulated (PWM) controller and this approach. A buck converter test circuit is constructed that is designed for a PWM controller clocked at 200 kHz and then substituted with a /spl Delta//spl Sigma/ modulator controller clocked at 400 kHz. The RMS noise power of the PWM controller is 14.9 mW compared to the rms noise power for the /spl Delta//spl Sigma/ modulator of 75.85 mW measured in a 2-MHz bandwidth. Although the /spl Delta//spl Sigma/ modulator rms noise power is higher, the noise floor is below the tones seen at the output of the PWM controller. A multibit /spl Delta//spl Sigma/ modulator controller, however, provides a significant reduction in the spectral output of the power supply. Values of 3.75 and 0.24 mW rms noise power are observed at the output of a 2-bit and 4-bit /spl Delta//spl Sigma/ modulator controller, respectively.     

Switched-capacitor immittance convertors using a single operational amplifier

The improved switched-capacitor immittance convertors using a single operational amplifier are proposed. The general scheme which enables the conversion of the capacitive (n + 1)-terminal networks into the corresponding bilinearly equivalent networks consisting of LC parallel branches is also proposed.     

A switched-capacitor delta-sigma modulator with reduced sensitivityto op-amp gain

Low operational amplifier (op-amp) gain can degrade the performance of a switched-capacitor delta-sigma modulator (ΔΣM). A ΔΣM that incorporates a new gain-compensated switched-capacitor integrator is described. The resulting ΔΣM topology has reduced sensitivity to op-amp gain. Simulation and measurement results for an experimental ΔΣM that demonstrate the advantages of the new architecture are presented     

A stable high-order delta-sigma modulator with an FIR spectrumdistributor

A stable high-order delta-sigma modulator topology is presented. The topology can be completely stabilized for arbitrary order by a finite impulse response (FIR) spectrum distribution technique. The stability of the modulator is examined by means of the root locus method. The topology inherently has less sensitivity to component mismatch, and can be realized without any hardware penalty compared to noise-shaping integrators of the same order. The modulator realizes 16-b resolution at 20-kHz bandwidth when a filter order of four and an oversampling ratio of 64 are employed     

A second-order double-sampled delta-sigma modulator usingindividual-level averaging

A second-order double-sampled delta-sigma modulator is described. It uses all individual-level-averaging switching scheme to convert capacitor mismatch into high-pass noise. With a sampling rate of 25 MHz and an oversampling ratio of 128, the maximum measured signal-to-noise-and-distortion ratio is 82.2 dB, and the total harmonic distortion is -91.0 dB when the input is 2.5 dB below full scale. The modulator is fully differential, occupies 3.75 mm² in a 1.2-μm CMOS process, and dissipates 25.9 mW (10.2 mW analog and 15.7 mW digital)     

A second-order double-sampled delta-sigma modulator usingadditive-error switching

A second-order double-sampled delta-sigma modulator is described. It uses an additive-error switching scheme to convert capacitor mismatch into an additive out-of-band tone that can be removed by a digital filter. With a sampling rate of 5 MHz and an oversampling ratio of 256, the maximum measured signal-to-noise-and-distortion ratio (SNDR) is 86.3 dB, and the total harmonic distortion is -88.7 dB when the input is 2 dB below full scale. The modulator is fully differential, occupies 5 mm², and dissipates 13 mW     

MOS-C single amplifier biquads using the operational transresistance amplifier

A configuration for the realization of voltage-mode second-order filters employing a single operational transresistance amplifier (OTRA) as the active element is presented. This topology can synthesize lowpass, highpass, bandpass, notch and allpass filtering functions. The presented filters are suitable for MOS-C implementation, yielding the filter parameters to be electronically tunable. Theoretical analysis is verified with PSPICE simulation.     

A fourth-order bandpass delta-sigma modulator with reduced numbersof op amps

A switched-capacitor quadrature demodulation technique, which is insensitive to first-order errors resulting from 90° phase inaccuracy and path mismatch, is demonstrated to shift a band-pass spectrum directly to dc. A sampling rate of four times the passband center frequency facilitates the quadrature demodulation and removes the 90° phase error. Furthermore, the path-mismatch error is canceled using the same signal path repeatedly, thereby reducing the number of op amps. A fourth-order band-pass Δ-Σ modulator, integrated in an area of 1 mm² using 2-μm CMOS, consumes 0.8 mW with a single 3.3-V supply and exhibits an SNR of 56 dB within a 30-kHz bandwidth     

A 5-MHz bandwidth 78.1-dB SNDR 2-2 MASH delta-sigma modulator

ABSTRACT

This paper presents a 4-bit, 2–2 multi-stage noise shaping (MASH) delta-sigma modulator (DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The DSM was designed using a cascade-of-integrators with a feedforward (CIFF) structure. The first integrator was designed to reduce the loading effect of the system’s front-end circuit using a switched-resistor integrator instead of the conventional switched-capacitor method. The CIFF structure requires an active adder, which is generally implemented with a high-bandwidth high-swing amplifier. In this paper, the active adder is eliminated and an adder-less integrator is implemented in the MASH DSM. The DSM prototype has an over-sampling ratio (OSR) of 16 and a 160 MHz sampling frequency. The prototype’s measured signal-to-noise ratio (SNR) is 82.4 dB and the signal-to-noise-plus-distortion ratio (SNDR) is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm². The energy required per conversion step is 0.4 pJ/conv.