A Low Voltage and Low Power Current-Mode Analog Computational Circuit

A new current-mode analog computational circuit is presented. The circuit can be digitally controlled to produce multiplying, squaring and inverse functions. The design is based on using MOSFETs operating in sub-threshold region to achieve ultra low power dissipation. The circuit is operated from a ±0.75 V DC supply. The proposed circuit has been simulated using Tanner in 0.35-μm TSMC CMOS process. Simulation results confirm the functionality of the circuit. The total power consumption is 2.3 μW, total harmonic distortion is 1.1 %, maximum linearity error is 0.3 % and the bandwidth is 2.3 MHz.     

A CMOS current-mode log(x) and log(1/x) functions generator

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.     

Design and application of precise analog computational circuits

New versatile building blocks for implementing analog functional circuits such as a multiplier, a squarer, and a square rooter based on functional terms of a differential input circuit are proposed and implemented in 0.25 um CMOS process. The input range of these circuits is over  ±1.0 V with a high linearity of less than 4% for 3.3 V power supply. The  ?3 dB bandwidth of all discussed circuits has been measured to over 200 MHz. The functional circuit size is 340 μm², and its typical power consumption is about 90 uW.     

A CMOS inverter-based class-AB pseudo-differential amplifier with current-mode common-mode feedback (CMFB)

This paper presents a CMOS inverter-based class-AB pseudo-differential amplifier comprising current-mode common-mode feedback (CMFB). The circuit employs two CMOS inverters and the complementary CMFB consisting of current-mode common-mode (CM) detector and transimpedance amplifier. The circuit has been designed using 0.18 μm CMOS technology and operates at 1 V supply. The simulation results demonstrate rail-to-rail operation with low CM gain (?15 dB). The power dissipation of the circuit is 102.5 μW.     

A CMOS current-mode squaring circuit free of error resulting from carrier mobility reduction

This paper presents a new current-mode squaring circuit. The design is based on MOSFETs translinear principle in strong inversion. A new compensation technique to minimize the second order effects caused by carrier mobility reduction in short channel MOSFETs is proposed. Tanner T-spice simulation tool is used to confirm the functionality of the proposed design in 0.18 µm CMOS process technology. Simulation results indicate that the maximum linearity error is 1.2 %; power consumption is 326 µW and bandwidth of 340 MHz.     

CMOS current-mode exponential-control variable-gain amplifier

A CMOS current-mode exponential-control variable-gain amplifier is presented. It consists of a first-order current-mode pseudo-exponential circuit and a current-mode multiplier. Based on the Taylor's series expansion, the pseudo-exponential circuit can be realised by MOSFETs in saturation. The proposed circuit has been fabricated in a 0.5 μm n-well CMOS process with a gain control range of 15 dB. The experimental results confirm the feasibility of the proposed variable-gain amplifier     

Equivalent circuit models in current-mode circuits for time delay calculations

In this paper time delay calculations for current-mode circuits are considered and equivalent circuit models for delay estimation are developed. Three different equivalent circuit structures for the Core Circuit used in the multipurpose IC DU-TCC1209 are examined separately; however the relation obtained for the time delay can be applied to any CMOS current-mode circuit. The proposed calculation methods are verified with SPICE using 0.35 μm TSMC MOSIS technology parameters and with bench-test measurements using DU-TCC1209.     

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valuedMOS current-mode circuits with dual-rail source-coupled logic

A new multiple-valued current-mode MOS integrated circuit is proposed for high-speed arithmetic systems at low supply voltage. Since a multiple-valued source-coupled logic circuit with dual-rail complementary inputs results in a small signal-voltage swing while providing a constant driving current, the switching speed of the circuit is improved at low supply voltage. As an application to arithmetic systems, a 200 MHz 54×51-b pipelined multiplier using the proposed circuits with a 1.5 V supply voltage is designed with a 0.8-μm standard CMOS technology. The performance of the proposed multiplier is evaluated to be about 1.4 times faster than that of a corresponding binary implementation under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the multiple-valued arithmetic circuit     

Four-quadrant analogue multiplier using operational amplifier

A method to realise a four-quadrant analogue multiplier using general-purpose operational amplifiers (opamps) as only the active elements is described in this article. The realisation method is based on the quarter-square technique, which utilises the inherent square-law characteristic of class AB output stage of the opamp. The multiplier can be achieved from the proposed structure with using either bipolar or complementary metal-oxide-semiconductor (CMOS) opamps. The operation principle of the proposed multiplier has been confirmed by PSPICE analogue simulation program. Simulation results reveal that the principle of proposed scheme provides an adequate performance for a four-quadrant analogue multiplier. Experimental implementations of the proposed multiplier using bipolar and CMOS opamps are performed to verify the circuit performances. Measured results of the experimental proposed schemes based on the use of bipolar and CMOS opamps with supply voltage ±2.4 V show the worst-case relative errors of 0.32% and 0.47%, and the total harmonic distortions of 0.47% and 0.98%, respectively.     

Body-driven log/antilog PVT compensated analog computational block

A four quadrant analog multiplier is proposed in this paper. It is using body-driven MOSFETs operating in subthreshold region. In essence, the subthreshold approach is too susceptible to PVT variations. However, these effects have been intrinsically mitigated by the log/antilog characteristics and enable the realization of current-mode multiplication function in simple and power efficient way at the same time. The multiplier is designed in CMOS 0.18 µm 1P6 M process technology. It occupies an active area of 250 µm² and consumes 0.698 µW from ± 0.3 V voltage supply. The results are in agreement with the theory under different conditions.     

一种用模拟LSI实现的新型概率解码器的研究

本文利用工作在亚阈值模式的MOS管特性,设计了一种低功耗的模拟电流型乘法器,并以此乘法器为核心,设计了一组利用电流进行概率计算的模拟单元电路.根据这些单元电路,基于最大后验概率算法(MAP),实现了(5,2,3)格码软判决译码的概率解码器.在解码器的输入部分设计了新型的具有流水线结构的串行输入接口.用标准的0.6μm CMOS工艺对解码器进行了性能模拟验证.     

Fast transient DC–DC converter with adaptive compensation zero technique

This letter is to present an adaptive compensation zero circuit to achieve good transient response in current-mode DC–DC buck converter. The proposed structure introduces an adaptive resistance dynamically adjusted according to the different output load conditions, which achieves an adequate system phase margin. A monolithic DC–DC buck converter using the proposed structure was fabricated with 0.35 μm CMOS process. Measurement results show that the transient undershoot/overshoot voltage and the recovery time do not exceed 60 mV and 20 μs for a load current variation from 0 to 1 A.     

Analysis and design of a new COA-based current-mode instrumentation amplifier with robust performance against mismatches

In this paper, analysis and design of a new current-mode instrumentation amplifier (CMIA) circuit is presented. The proposed circuit employs two Current Operational Amplifiers (COA) as active building blocks, one resistor and two transistors operating as variable resistors to electronically control the differential-mode gain. The main feature of the proposed CMIA is that unlike most previously reported CMIAs, its CMRR has negligible sensitivity to mismatches. In addition, in the proposed circuit both active building blocks operate in negative feedback loop which results in an overall enhanced performance. SPICE simulation results using 0.18 μm TSMC CMOS parameters and supply voltage of ±0.9 V show a constant CMRR of about 51 dB regardless of mismatches and wide bandwidth ranging from 14.8 MHz to about 3 MHz for differential-mode gains between 3 and 18 dB, respectively.     

0.5 V CMOS inverter-based tunable transconductor

A new technique for CMOS inverter-based tunable transconductors is proposed in this paper. The proposed technique employs the master–slave approach and offers large transconductance tuning range using a control current. The transconductor was designed using triple-well 0.13 μm CMOS process under the ultra low supply voltage of 0.5 V. The circuit features 37 dB open loop gain, CMRR = 31 dB at each output node, PSRR = 90 dB and GBW = 530 MHz for 120 μA current consumption.     

A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion

A new four quadrant voltage mode bulk input analog multiplier is presented .The proposed multiplier is designed to operate in weak inversion. Multiplication is done by driving the bulk terminals of the MOS devices which offers linear dynamic range of ±80 mV. The simulation shows, it has a linearity error of 5.6 %, THD of nearly 5 % and ?3 dB band width of 221 kHz. Total power consumption is very low i.e. 714 nW. The circuit operates at a supply voltage of 0.5 V and is designed using 180 nm CMOS technology. It is suitable for low power bioelectronics and neural applications.     

A new compact CMOS C-multiplier

This paper presents a new compact CMOS capacitance multiplier. The multiplier is based on using the translinear principle with MOSFETs operating in subthreshold region. The multiplication factor is controllable to meet the designer requirements. Tanner TSPICE simulator was used to confirm the functionality of the design in 0.18 µm CMOS Technology. The circuit operates from ±0.75 supply voltage. Simulation results indicate that the multiplication factor can be varied from 10 to 300. The functionality of the proposed capacitance multiplier was demonstrated by using it in designing a low pass filter and a relaxation oscillator.     

A current-mode continuous-time filter for software defined radio solutions

A 3rd-order continuous-time current-mode filter in 65 nm CMOS technology is presented. The filter has a switchable cut-off frequency between 1.1 and 4.4 MHz and is designed for software defined radio on chip (SDR) solutions. An innovative extension to structures in literature is proposed, that allows saving chip area at low cut-off frequencies. Furthermore a mathematical estimation is presented to show the usability of the structure. The realized chip has an active area of 350 μm × 220 μm and consumes 12.3 mW at 1.2 V. The dynamic range for a bandwidth of 1.1 MHz is 77.2 dB, the in-band output current noise is \(31.16\,\hbox{pA}/\sqrt{\hbox{Hz}}\) and the IIP3 is 1.8 mA_p.     

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ± 60 μ A, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ± 1V from ± 1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 μV/√Hz, and the maximum linearity error is 4.1%. Mohammed A. Hashiesh was born in Elkharga, New Valley, Egypt, in 1979. He received the B.Sc. degree with honors from the Electrical Engineering Department, Cairo University, Fayoum-Campus, Egypt in 2001, and he received the M.Sc. degree in 2004 from the Electronics and Communication Engineering Department, Cairo University, Egypt. He is currently a Teacher Assistant at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include analog CMOS integrated circuit design and signal processing, and digitally programmable CMOS analog building blocks. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. He has published more than 50 papers. His research and teaching interests are in circuit theory, fully integrated analog filters, high frequency transconductance amplifiers, low voltage analog CMOS circuit design, current-mode analog signal processing and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.     

CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques

A CMOS analogue current-mode multiplier/divider circuit is presented. It is based on a dynamic biasing applied at the bulk terminal of MOS transistors operating in both saturation and triode. With the proposed structure, the multiplier forms a feedback loop that improves the current swing and accuracy. The multiplier has been fabricated using a standard 0.18 µm CMOS technology. The circuit consumes 144 µW using a single supply voltage of 1.8 V with a measured THD lower than 1% for an output current of 38 µA, and requires a die area of 90 µm x 45 µm.