UML到Verilog同态映射在SOC系统级建模上的应用

SOC设计变得日益复杂要求我们在更高层次抽象上分析和验证系统行为。更精细的系统级建模方法变得日趋重要。文章主要目标是阐述怎样使用统一建模语言UML来构建一个复杂SOC设计框架及抽象其各个模块间行为的交互，建立了一个UML到Verilog的同态映射。提出了一个基于同态映射的从UML模型子集自动导出相应可综合Verilog描述的算法，为UML模型对于建模硬件系统提供了形式化的语义，从而能够验证并综合UML模型，加快了SOC设计流程。     

Performance effects of formal modeling language differences: a combined abstraction level and construct complexity analysis

Understanding data-modeling performance can provide valuable lessons for the selection, training, research, and development of data models. Data modeling is the process of transforming expressions in loose natural language communications into formal diagrammatic or tabular expressions. While researchers generally agree that abstraction levels can be used to explain general performance differences across models, empirical studies have reported many construct level results that cannot be explained. To explore further explanations, we develop a set of model-specific construct complexity values based on both theoretical and empirical support from complexity research in databases and other areas. We find that abstraction levels and complexity values together are capable of providing a consistent explanation of laboratory experiment data. In our experiment, data were drawn from three models: the relational model, the extended-entity-relationship model, and the object-oriented model. With the newly developed complexity measures, a consistent explanation can be made for findings from other studies which provide sufficient model details for complexity values to be calculated.     

Performance in Planning — Smart Systems for the Access Network

Improvements in system technologies continue apace — with new developments in software methods arguably outstripping even the breakneck progress in hardware power described by 'Moore's Law'. The software developments are timely, since they offer solutions to the urgent problems of increasing customer demands, complexity of network technologies, and more competitive markets. The increasing availability of cheap computing power, with developments in object orientation and artificial intelligence, offer the possibility of a more holistic approach to network performance planning and management. The most fundamental aspects of network performance (functionality, reliability, and cost) can now feasibly be considered simultaneously and interactively. Common, comprehensive network models are within sight, which could be utilised by network planners, installers, repair staff, marketeers and at point-of-sale. The resulting improvements in productivity and service quality could be immense. Specific examples of 'intelligent' access network planning tools, produced using rapid application development techniques within BT, are described to illustrate their potential.     

MMV: A Metamodeling Based Microprocessor Validation Environment

With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges. The systematic validation approach starts with defining the correct behaviors of the hardware and software components and their interactions. This requires new modeling paradigms that support multiple levels of abstraction. Mutual consistency of models at adjacent levels of abstraction is crucial for manual refinement of models from the full chip level to production register transfer level, which is likely to remain the dominant design methodology of complex microprocessors in the near future. In this paper, we present microprocessor modeling and validation environment (MMV), a validation environment based on metamodeling, that can be used to create models at various abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage, and test generation tools. We illustrate the functionalities in MMV by modeling a 32-bit reduced instruction set computer processor at the system, instruction set architecture, and microarchitecture levels. We show by examples how consistency across levels is enforced during modeling and also how to generate constraints for automatic test generation.     

Combining aspects and object-orientation in model-driven engineering for distributed industrial mechatronics systems

Recent advances in technology enable the creation of complex industrial systems comprising mechanical, electrical, and logical – software – components. It is clear that new project techniques are demanded to support the design of such systems. At design phase, it is extremely important to raise abstraction level in earlier stages of product development in order to deal with such a complexity in an efficient way. This paper discusses Model Driven Engineering (MDE) applied to design industrial mechatronics systems. An aspect-oriented MDE approach is presented by means of a real-world case study, comprising requirements engineering up to code generation. An assessment of two well-known high-level paradigms, namely Aspect- and Object-Oriented paradigms, is deeply presented. Their concepts are applied at every design step of an embedded and real-time mechatronics system, specifically for controlling a product assembler industrial cell. The handling of functional and non-functional requirements (at modeling level) using aspects and objects is further emphasized. Both designs are compared using a set of software engineering metrics, which were adapted to be applied at modeling level. Particularly, the achieved results show the suitability of each paradigm for the system specification in terms of reusability quality of model elements. Focused on the generated code for each case study, statistics depicted an improvement in number of lines using aspects.     

Polynomial circuit models for component matching in high-levelsynthesis

Design reuse requires engineers to determine whether or not an existing block implements desired functionality. If a common high-level circuit model is used to represent components that are described at multiple levels of abstraction, comparisons between circuit specifications and a library of potential implementations can be performed accurately and quickly. A mechanism is presented for compactly specifying circuit functionality as polynomials at the word level. Polynomials can be used to represent circuits that are described at the bit level or arithmetically. Furthermore, in representing components as polynomials, differences in precision between potential implementations can be detected and quantified. We present a mechanism for constructing polynomial models for combinational and sequential circuits. Furthermore, we derive a means of approximating the functionality of nonpolynomial functions and determining a bound on the error of this approximation. These methods have been implemented in the POLYSYS synthesis tool and used to synthesize a JPEG encode block and infinite impulse response filter from a library of complex elements     

基于矩阵分解和注意力多任务学习的客服投诉工单分类

投诉工单自动分类是通信运营商客服数字化、智能化发展的要求。客服投诉工单的类别有多层,每一层有多个标签,层级之间有所关联,属于典型的层次多标签文本分类问题,现有解决方法大多数基于分类器同时处理所有的分类标签,或者对每一层级分别使用多个分类器进行处理,忽略了层次结构之间的依赖。提出了一种基于矩阵分解和注意力的多任务学习的方法(MF-AMLA),处理层次多标签文本分类任务。在通信运营商客服场景真实投诉工单分类数据下,与该场景常用的机器学习算法和深度学习算法的Top1F1值相比分别最大提高了21.1%和5.7%。已在某移动运营商客服系统上线,模型输出的正确率97%以上,对客服坐席单位时间的处理效率提升22.1%。     

Perceptual learning and abstraction in machine learning: an application to autonomous robotics

This paper deals with the possible benefits of perceptual learning in artificial intelligence. On the one hand, perceptual learning is more and more studied in neurobiology and is now considered as an essential part of any living system. In fact, perceptual learning and cognitive learning are both necessary for learning and often depend on each other. On the other hand, many works in machine learning are concerned with "abstraction" in order to reduce the amount of complexity related to some learning tasks. In the abstraction framework, perceptual learning can be seen as a specific process that learns how to transform the data before the traditional learning task itself takes place. In this paper, we argue that biologically inspired perceptual learning mechanisms could be used to build efficient low-level abstraction operators that deal with real-world data. To illustrate this, we present an application where perceptual-learning-inspired metaoperators are used to perform an abstraction on an autonomous robot visual perception. The goal of this work is to enable the robot to learn how to identify objects it encounters in its environment.     

Functional verification of instruction processing units through control flow modeling

The design verification of state-of-the-art high-performance microprocessors has become a significant challenge for test engineers. Deep pipelines, multiple execution units, out-of-order and speculative execution techniques, typically found in such microprocessors, contribute much to this complexity. Conventional methods, which treat the processor as a logic state machine or apply architectural level tests, fail to provide coverage of all possible corner cases in the design. This paper presents a functional verification method for modern microprocessors, which is based on innovative models of the microprocessor architecture, intended to cover the testing of all corner cases. In order to test the models presented in this work, an architecture independent coverage measurement system has been developed. The models were tested with both random code and real world applications in order to determine which of the two achieves higher coverage.     

A Service Engineering framework to design and assess an integrated product-service

Companies are striving to create new sources of value, providing integrated product-service solutions to customers, evolving from a “pure product” orientation towards a Product-Service System (PSS) perspective. In this context, Service Engineering (SE), the discipline concerned with the systematic development and design of product-services, is becoming a predominant field. Most of the available Service Engineering models, methods and tools come from traditional engineering, business and computer science approaches adapted to the Service System or Product-Service System. In order to fill this gap, this paper proposes a Service Engineering framework that integrates a product-service design modelling tool developed at the Tokyo Metropolitan University with a discrete event simulation test-bench, enabling the comparison of several PSS configurations considering both customer satisfaction measures and internal performance. A sample case is reported to exemplify the different phases of the framework implementation.     

The practical engineer [IC design, power reduction]

The need of popular portable electronics for long battery life is placing power reduction at the top of every IC design engineer's to-do list. A new breed of design automation tools is helping them scrimp on power at every step of the VLSI design process. The automation tools can be differentiated, to a first order, by the level of abstraction on which they operate. Lowest of all are the transistor level tools. These possess the best accuracy, but commensurately require the longest run times and have the smallest capacities-the size of the circuit that can be analyzed. While transistor level tools can assist with analyses earlier in the design process, they are typically used to characterize cells and modules for use at the higher abstraction levels. The next level of abstraction embraces the logic-level power analysis tools. The highest abstraction level for which power analysis tools exist today is the architectural level. This type of tool analyzes abstract design representations such as Verilog or VHDL RTL code. The use of these tools in power reduction design is outlined