新型电子工业清洗工艺研究

本文报告了一种新型电子工业清洗工艺，用该工艺清洗过的硅片上的钠残留量低于常规ｃｍｏｓ／ｓｏｓ栅氧化工艺，去重金属离子的能力及对器件参数的影响与常规ｃｍｏｓ／ｓｏｓ栅氧化工艺相当。新型清洗工艺具有操作简单，价格低廉等优点，无毒，无腐蚀性，对人体无危害，对环境无污染。     

SIMOX结构隐埋氧化层的体电学传导

ＳＩＭＯＸ结构隐埋氧化层的体电学传导＝ＢｕｌｋｅｌｅｃｔｒｉｃａｌｃｏｎｄｕｃｔｉｏｎｉｎｔｈｅｂｕｒｉｅｄｏｘｉｄｅｏｆＳＩＭＯＸｓｔｒｕｃｔｕｒｅ［刊，英］／Ｒｅｖｅｓｚ，Ａ．Ｇ．…／／Ｊ．Ｅｌｅｃｔｒｏｃｈｅｍ．Ｓｏｃ．－１９９３，１４０（１１...     

顶层氧化对氧－氮－氧叠式膜的可靠性的影响

顶层氧化对氧－氮－氧叠式膜的可靠性的影响＝Ｔｏｐ－ｏｘｉｄａｔｉｏｎｅｆｆｅｃｔｓｏｎｔｈｅｒｅｌｉａｂｉｌｉｔｙｏｌｏｘｉｄｅ－ｎｉｔｒｉｄｅ－ｏｘｉｄｅｓｔａｃｋｅｄｆｉｌｍ［刊，英］／Ｙｏｎｅｄａ，Ｋ．…Ｊ．Ｅｌｅｃｔｒｏｒｈｅｍ．Ｓｏｃ．－１...     

一种新型超净高纯试剂在半导体技术中的应用

通过对新型超净高纯试剂同常规CMOS酸碱试剂同时进行CMOS工艺中栅氧化前的清洗实验,从清洗后硅片残留金属量的电感耦合高频等离子体原子发射光谱分析、硅片表面形貌的AFM分析和MOS电容测量三个方面进行了应用实验.结果表明,以超净高纯乙腈为主要组分的新型试剂,其清洗效果总体优于常规CMOS酸碱试剂,可以考虑在半导体器件相应清洗工艺中采用.     

WinSock规范

ＷｉｎＳｏｃｋ规范ＷｉｎＳｏｃｋ（ＷｉｎｄｏｗｓＳｏｃｋｅｔｓ）是近来开发出来的一种标准，它为ＷｉｎｄｏｗｓＴＣＰ／ＩＰ提供一个ＢＳＤ型插口的接口，并首次推出与卖主无关的Ｗｉｎｄｏｗｓ版本网络接口。一、什么是ＷｉｎｓｏｃｋＷｉｎＳｏｃｋ是类似ＢＳＤ／...     

短沟道CMOS／SOI器件加固技术研究

通过大量辐照实验分析了采用不同工艺和不同器件结构的薄膜短沟道ＣＭＯＳ／ＳＩＭＯＸ器件的抗辐照特性，重点分析了Ｈ２－Ｏ２合成氧化和低温干氧氧化形成的薄栅氧化层、ＣｏＳｉ２／多晶硅复合栅和多晶硅栅以及环形栅和条形栅对ＣＭＯＳ／ＳＩＭＯＸ器件辐照特性的影响，最后得到了薄膜短沟道ＣＭＯＳ／ＳＩＭＯＸ器件的抗核加固方案．     

利用MFC Socket类实现TCP/IP通信

分析了利用 Ｗｉｎｄｏｗｓ Ｓｏｃｋｅｔｓ进行网络通信程序的基本原理，给出了利用 ＭＦＣ的套接字类 ＣＡｓｙｎｃＳｏｃｋｅｔ，ＣＳｏｃｋｅｔ编写 ＴＣＰ／ＩＰ网络通信程序步骤和方法。     

用电子回旋共振等离子淀积非晶硅

用电子回旋共振等离子淀积非晶硅＝Ｄｅｐｏｓｉｔｉｏｎｏｆａｍｏｒｐｈｏｕｓｓｉｌｉｃｏｎｂｙａｎｅｌｅｃｔｒｏｎｃｙ－ｃｌｏｔｒｏｎｒｅｓｏｎａｎｃｅｐｌａｓｍａｓ［刊，英］／Ｙｏｋｏｔａ，Ｋ．…／／Ｊ．Ｅｌｅｃｔｒｏｃｈｅｍ．Ｓｏｃ．－１９９３，１...     

高质量栅氧化层的制备及其辐照特性研究

通过大量工艺实验开发了采用低温Ｈ２－Ｏ２合成氧化方法制备薄栅氧化层的工艺技术,得到了性能优良的薄栅氧化层,对于厚度为３０ｎｍ的栅氧化层,其平均击穿电压为３０Ｖ,Ｓｉ／ＳｉＯ２界面态密度小于３．５×１０１０ｃｍ－２．该工艺现已成功地应用于薄膜全耗尽ＣＭＯＳ／ＳＯＩ工艺中．同时还开展了采用低温Ｈ２－Ｏ２薄栅氧化工艺制备的全耗尽ＣＭＯＳ／ＳＯＩ器件的抗总剂量辐照特性研究,采用低温Ｈ２－Ｏ２合成氧化方法制备的ＳＯＩ器件的抗辐照特性明显优于采用常规干氧氧化方法制备的器件,Ｈ２－Ｏ２低温氧化工艺是制备抗核加固ＣＭＯＳ     

自对准外延CoSi_2源漏接触CMOS器件技术

ＣＯ／Ｔｉ／Ｓｉ或ＴｉＮ／Ｃｏ／Ｔｉ／Ｓｉ多层薄膜结构通过多步退火技术在Ｓｉ单晶衬底上外延生长ＣｏＳｉ２薄膜，ＡＥＳ、ＲＢＳ测试显示ＣｏＳｉ２薄膜具有良好均匀性和单晶性．这种硅化物新技术已用于ＣＭＯＳ器件工艺．采用等离子体增强化学汽相淀积（ＰＥＣＶＤ）技术淀积氮氧化硅薄膜，并用反应离子刻蚀（ＲＩＥ）技术形成多晶硅栅边墙．固相外延ＣｏＳｉ２薄膜技术和边墙工艺相结合，经过选择腐蚀，可以分别在源漏区和栅区形成单晶ＣｏＳｉ２和多晶ＣｏＳｉ２薄膜，构成新型自对准硅化物（ＳＡＬＩＣＩＤＥ）器件结构．在Ｎ阱ＣＭＯＳ工艺     

NORA: a racefree dynamic CMOS technique for pipelined logic structures

Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.     

Silicon-gate n-well CMOS process by full ion-implantation technology

A silicon-gate n-well CMOS process for an application of digital circuits operated by TTL compatible supply voltage was developed. Full ion-implantation technology, a new photolithography technique, n⁺-doped polysilicon gate which contain no boron impurities, and thin gate oxide of 65 nm can realize CMOS circuits of 2-µm gate length. Average impurity concentrations measured from substrate bias effect of MOSFET's and junction depth are in good agreement with those expected from impurity profiles calculated by a simple diffusion theory. So, the process design for CMOS circuits operated by any supply voltage is possible, by adjusting threshold voltages. The process can easily be extended to n-MOS/CMOS process (E/D MOS and CMOS on the same chip), if a photomask to fabricate depletion-type n-MOSFET's is provided.     

Low-Voltage High-Frequency Continuous-Time Filters Based on Simple Transconductors and Miller Integrators

An approach to implement low-voltage continuous-time filters using simple transconductance elements and gain-stage Miller integrators is presented. The technique allows direct translation of an RC active structure or a system block diagram into a CMOS circuit that uses differential pairs as transconductors and gain stages as Miller Integrators. A novel and efficient compensation technique to cancell excess phase in Miller integrators is discussed. A new high-frequency compensated CMOS universal filter structure that has no summing nodes in the main feedback loop is discussed and experimentally verified.     

Self-biasing of folded cascode CMOS op-amps

In cascode CMOS op-amps a large number transistors are biased using independent standard bias circuits. This results in numerous drawbacks, namely, an area and power overhead, and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no bias voltages other than the two supply rails. The resulting self-biased op-amps are free from the above mentioned drawbacks and exhibit the same performance as existing folded cascode op-amps. This is achieved by following transistor sizing constraints derived through detailed circuit analysis. The technique is applied to an existing high performance op-amp. Simulation results show that the high performance is maintained while nine bias voltages are eliminated.     

A new self-aligned well-isolation technique for CMOS devices

This paper presents the development of a new well-isolation technique for advanced CMOS LSI's. The technique comprises narrow deep trench fabrication utilizing undercut, in addition to silicon-oxide cap formation, which leaves a cavity. The predominant feature of this technique is that well isolation self-aligned to the well region is realized utilizing the trench fabrication technique. Additionally, no crystal defects are observed around the well isolation even after 1000°C annealing following silicon-oxide cap formation. Since the well isolation produced also prevents the latchup phenomenon from occurring due to its depth, this technique enables the CMOS device dimensions to be considerably reduced.     

Scarce-state-transition error-trellis decoding of block codes withBPSK signals

A novel decoding technique for linear block codes with coherent BPSK signals is proposed. The new system has the same error performance as and similar complexity to the conventional trellis decoding of block codes. Like the scarce-state-transition Viterbi decoding of convolutional codes, the proposed system is also well suited for CMOS VLSI implementation and has a lower power consumption     

用含表面活性剂和螯合剂的清洗液清洗硅片的研究

目前半导体工业生产中普遍采用的清洗技术是 RCA清洗技术 .文中介绍了一种含表面活性剂和螯合剂的新型半导体清洗剂和清洗技术 .并利用 X射线光电子谱和原子力显微镜等测试方法 ,分别比较了用两种清洗技术清洗过的硅片表面 .测试结果表明 ,它们的去污效果基本相当 .但对硅片表面的粗糙化影响方面 ,新型半导体清洗技术优于标准 RCA清洗技术 .     

Scarce-state-transition syndrome-former error-trellis decoding of(n,n-1) convolutional codes

A novel scarce-state-transition (SST) type trellis decoding system for (n,n-1) convolutional codes with coherent BPSK signals is proposed. The new system retains the same number of binary comparisons as the syndrome-former trellis decoding technique. Like the original SST-type encoder trellis technique, the proposed system is also suitable for CMOS VLSI implementation. A combination of the two techniques results in a less complex and low power consumption decoding system     

清洗后硅片表面的电子结构

介绍了一种含表面活性剂和螯合剂的新型半导体清洗剂和清洗工艺。利用红外吸收谱、X射线光电子谱和原子力显微镜等 ,把它和标准 RCA清洗工艺的清洗效果做了比较。测试结果表明 ,经清洗过的硅片表面主要是由硅、氧和碳三种元素组成 ,它们分别以 Si-O键、C-O键和 Si-C键的形式存在。两种清洗技术都在硅片表面产生氧化硅层 ,在硅片表面都存在有机碳污染 ,但新型半导体清洗工艺产生的有机碳污染少于标准 RCA清洗。在对硅片表面的粗糙化影响方面 ,新型半导体清洗技术清洗明显优于标准 RCA清洗技术