MEMS低量程微加速度计的设计

在传统双边四梁微加速度计结构的基础上,设计了一种新型MEMS低量程微加速度计,量程为±10 g。用ANSYS有限元软件对加速度计的结构建立仿真模型,进行应力、模态及抗冲击能力分析。加速度计供电电压为5 V时,灵敏度理论值达到1.029 mV/g,与传统结构相比,极大地提高了低量程微加速度计的灵敏度。     

悬臂梁式硅微加速度计的研制

介绍一种悬臂梁式硅微加速度计的结构与工作原理,并利用ANSYS软件进行了仿真模拟。采用体硅“无掩膜”腐蚀技术,对设计出的敏感芯片进行了工艺试制。通过合理的设计,使挠性梁腐蚀区域侧面上产生(311)面,通过控制所产生的(311)面对(111)面的侵削作用,获得了所需结构。为提高灵敏度和线性,该加速度计采用静电力反馈闭环控制方式,检测与处理电路采用高精度双极线性电路工艺进行了工艺流片。利用多芯片组装工艺进行了敏感芯片与一次集成的检测和处理电路的混合封装。经测试硅微加速度计性能为量程±50g,分辨率3×10–3g,非线性<5×10–4,质量为9.6g。     

左右分布式高灵敏硅微谐振加速度计结构设计

提出了一种基于微杠杆原理的左右分布式低交叉耦合、高灵敏度的硅微谐振加速度计结构.该结构采用了一级微杠杆放大机构,左右双音叉谐振器和单质量块布局,实现了力放大和差动频率输出,具有结构简单、易于加工的特点,且两音叉谐振器间相互干扰小.首先,优化了设计参数,并进行了模态分析与谐响应分析.结果表明,左右谐振工作谐振频率分别为149.49 kHz和150.8 kHz,在该工作频率下X方向的最大位移远大于y和Z方向(两个数量级以上),表明工作模态具有优良的抗干扰能力.其次,在1 000g加速度载荷作用下进行了极限过载仿真.仿真结果表明,其最大应力为612.69 MPa,表明具有一定的抗冲击能力.最后,在±50g的设计量程内对结构的灵敏度进行了仿真分析.仿真结果表明,其灵敏度为160.51 Hz/g,验证了该设计的正确性.     

引信用高g加速度计研究

高g加速度计具有高过载、高响应速度、高环境压力以及体积小和价格低等特点。我们开发的新型电容式加速度计,具有10万g的量程,能够实现高g环境下的加速度测量,满足了用户的要求。基于有限元模拟和经验数值结合的办法,在大量程和灵敏度之间综合考虑,确定了高g的设计思路,并采用硅溶片工艺制备了满足设计要求的MEMS加速度计。     

一种振动测量用电容式硅基MEMS加速度计

为了解决目前微电子机械系统(MEMS)加速度计在振动测量领域量程小和振动测量精度低等问题,基于绝缘体上硅(SOI)加工工艺,设计并制作了一款梳齿电容式MEMS加速度计。通过提高工作模态频率和干扰模态频差,提升了加速度计振动环境适应性;加速度计量程达到±50g,非线性度0.2%,横向灵敏度0.17%,分辨率优于0.5mg,体积9 mm×9 mm×2.7 mm,功率损耗30 mW。针对随机振动环境对加速度计的输出精度进行了实验验证,结果表明,MEMS加速度计与标准传感器的输出误差为2.69%,能够满足大部分工程应用需求。     

高分辨力闭环微加速度计接口电路

本文报道一种电容式闭环微加速度计的低噪声、开关电容CMOS接口电路。采用相同电极分时复用的方法,从而避免电容敏感与静电力反馈的馈通现象。并设计PID电路保证真空封装的高Q值加速度计的闭环稳定性及动态响应特性。整体电路结构只需单端放大器,传输门和电容。测试结果显示,接口电路工作在±5V条件下,整体微加速度计具有±3g满量程,非线性0.05%,800Hz带宽,刻度因子为1.2V/g,噪声密度为0.8μg/ 。芯片采用2um 双金属双多晶N阱CMOS工艺加工,芯片面积15.2 mm2。测试结果证明,本文电路达到高精度微加速度计系统设计要求,可以应用到地震监测、石油勘探等领域中。     

单片集成的高性能压阻式三轴高g加速度计的设计、制造和测试

设计、制造并测试了一种单片集成的压阻式高性能三轴高g加速度计,量程可达105g.x和y轴单元均采用一种带微梁的三梁-质量块结构,z轴单元采用三梁-双岛结构.与传统的单悬臂梁结构或者悬臂梁-质量块结构相比,这两种结构均同时具有高灵敏度和高谐振频率的优点.采用ANSYS软件进行了结构分析和优化设计.中间结构层主要制作工艺包括压阻集成工艺和双面Deep ICP刻蚀,并与玻璃衬底阳极键合和上层盖板BCB键合形成可以塑封的三层结构,从而提高加速度计的可靠性.封装以后的加速度计采用落杆方法进行测试,三轴灵敏度分别为2.28,2.36和2.52 μV/g,谐振频率分别为309,302和156 kHz.利用东菱冲击试验台,采用比较校准法测得y轴和z轴加速度计的非线性度分别为1.4%和1.8%.     

单片集成的高性能压阻式三轴高g加速度计的设计、制造和测试

设计、制造并测试了一种单片集成的压阻式高性能三轴高g加速度计,量程可达105g.x和y轴单元均采用一种带微梁的三梁-质量块结构,z轴单元采用三梁-双岛结构.与传统的单悬臂梁结构或者悬臂梁-质量块结构相比,这两种结构均同时具有高灵敏度和高谐振频率的优点.采用ANSYS软件进行了结构分析和优化设计.中间结构层主要制作工艺包括压阻集成工艺和双面Deep ICP刻蚀,并与玻璃衬底阳极键合和上层盖板BCB键合形成可以塑封的三层结构,从而提高加速度计的可靠性.封装以后的加速度计采用落杆方法进行测试,三轴灵敏度分别为2.28,2.36和2.52 μV/g,谐振频率分别为309,302和156 kHz.利用东菱冲击试验台,采用比较校准法测得y轴和z轴加速度计的非线性度分别为1.4%和1.8%.     

一种结构新颖的地震动加速度计

对比典型的差动电容结构,设计了一种新的折叠梁电容式MEMS低g(g=9.8m/s~2,当地重力加速度)值加速度计,指标为量程0～±2g,横向灵敏度<3%。利用有限元分析软件对模型进行了静态应力分析和模态分析,并给出了接口电路和自检测功能原理。最后设计了一套可行的加工工艺。     

一种硅梁谐振加速度计结构设计与模拟分析

为了提高谐振加速度计的灵敏度以及稳定性,提出一种基于微杠杆力学放大机构的硅梁谐振式加速度计结构,并对其进行了有限元模拟分析。该加速度计由两个静电激励电容检测的硅谐振梁组成差分输出,采用硅深刻蚀以及硅玻璃阳极键合等体硅工艺制作。模拟结果表明新结构提高了加速度计灵敏度,有效改善了交叉灵敏度、线性度、温度稳定性等。     

无掩膜腐蚀与伺服型电容式微加速度计

为了解决“三明治”这类微器件制作的深窄槽结构成型问题,运用无掩膜湿法腐蚀技术,成型悬臂梁雏形后再成型质量块,较好地实现了悬臂梁与质量块同时准确成型,研制出±70g和±5g两种不同量程的微加速度计。样品测试表明,利用这项技术所制作的微加速度计相对精度皆优于1×10^-4。其中,±70g量程的残差可控制在7mg以内,非线性可达0．02％;±5g量程的残差在0．4mg左右。     

一种数字CMOS工艺制造的10位100MS/s流水线ADC

介绍了采用0.18μm数字工艺制造、工作在3.3V下、10位100MS/s转换速率的流水线模数转换器。提出了一种适用于1.5位MDAC的新的金属电容结构,并且使用了高带宽低功耗运算放大器、对称自举开关和体切换的PMOS开关来提高电路性能。芯片已经通过流片验证,版图面积为1.35mm×0.99mm,功耗为175mW。14.7MS/s转换速率下测得的DNL和INL分别为0.2LSB和0.45LSB,100MS/s转换速率下测得的DNL和INL分别为1LSB和2.7LSB,SINAD为49.4dB,SFDR为66.8dB。     

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.     

A low-voltage tunneling-based silicon microaccelerometer

This paper describes the design, fabrication, and testing of a low-voltage tunneling-based silicon microaccelerometer. The device has been successfully batch-fabricated by the boron etch-stop dissolved wafer process. A 4 h, 1100°C oxygen, post-diffusion annealing process has been developed to eliminate the stress gradient in and warpage of thin (≈3 μm) heavily-boron-doped silicon microstructures. Using a simple discrete readout circuit, the device with an active area of 400×400 μm² provides a measured sensitivity of 1.66×10⁴ ppm/g (133 mV/g), bandwidth of 2 kHz in air, and a full scale range of 30 g with a nonlinearity of 0.6%. The measured noise spectrum exhibits a typical 1/f behavior and drops from 1.75 mg/√Hz (at 50 Hz) to 0.25 mg/√Hz (at 2 kHz), corresponding to a minimum detectable acceleration of 22.8 mg. The variations of the offset output voltage and device sensitivity are ±40 mV (≈0.5%) and ±0.65 mV/g (≈0.49%) in continuous operation over thirty days. The temperature coefficient of offset (TCO) and temperature coefficient of sensitivity (TCS) are -600 ppm/°C and 1200 ppm/°C, respectively     

A novel multi-input floating-gate MOS four-quadrant analogmultiplier

A novel four-quadrant analog multiplier using multi-input floating-gate MOS (MFMOS) transistors has been designed and fabricated using a 2-μm double-poly double-metal P-well CMOS process. It is essentially based on the quarter-square technique which relies on the square-law characteristic of the MOS transistor in the saturation region. The multiplier is realized with only four MFMOS transistors and a current source. The input range is 100% of the supply voltage and accepts either differential, single-ended, or floating input signals. Measured nonlinearity and total harmonic distortion are 0.2% and 0.5%, respectively, under full scale input conditions. Input noise is 170 μV (rms), giving a 95 dB input dynamic range. The power dissipation is 1.1 mW and bandwidth is 12 MHz. Second-order effects on the multiplier performance have also been analyzed     

滤波带宽对冲击响应谱的影响研究

目前利用冲击响应谱作为参考的冲击实验在国防事业、国家经济生活中得到广泛的应用,冲击响应谱也成为国防事业和经济生活中重要的参考标准,分析对冲击响应谱造成影响的因素,将有利于对冲击响应谱规范,为更好实现冲击实验提供精确的参数设置。实验过程中为了得出冲击信号滤波带宽对冲击响应谱的影响,利用霍普金森杆产生高g值,窄带宽的冲击信号,再结合信号分析软件对得到的数据进行处理,得出滤波带宽影响冲击响应谱的等冲区的结论。     

Single-loop ΔΣ modulator with extended dynamic range

A single-loop delta?sigma modulator with extended dynamic range is proposed. It employs an auxiliary quantiser to process the quantisation error of the main quantiser. This simple addition guarantees improved stability over a wider signal input range and also reduces the sensitivity to the front-end DAC nonlinearity. Simulation results are provided to verify the effectiveness of this structure.     

A Symmetric Complementary Structure for RF CMOS Analog Squarer and Four-Quadrant Analog Multiplier

A symmetric complementary structure for CMOS analog squarer and four-quadrant multiplier is proposed and analyzed. Analog squarer and a four-quadrant analog multiplier by utilizing the square-algebraic identity in the MOS triode region are presented. The squarer has a symmetric complementary configuration of the push-pull source follower and provides high performance in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The squarer, with –3 dB bandwidth of 1.3 GHz, had a nonlinearity error less than 1% over input signal range of ±1 V. The multiplier is basically constructed by voltage subtractors (for differential function of inputs) and sum-squaring as well as difference-squaring core circuits (for multiplication of two differential inputs signals). The multiplier has a nonlinearity error less than 1% over ±0.5 V input range. The circuit provides a –3 dB bandwidth higher than 1.3 GHz and exhibits a THD lower than 1% with a 1 V peak-to-peak input voltage, which dissipating 2.6 mW. The second-order effects including mismatch effects are discussed. The proposed circuits will be useful in various RF analog signal-processing applications.     

Analogue BiCMOS squarer and its applications

A BiCMOS squarer using active attenuators which has been fabricated in a 10 μm BiCMOS process is presented. Experimental results show that the nonlinearity of the squarer can be kept below 2%, across the entire input voltage range of ±0.3 V. Its -3 dB bandwidth is measured to be ~1 MHz. Moreover, based on the proposed squarer circuits, a four-quadrant multiplier and a vector summation circuit have also been realised. The proposed circuits are expected to be useful in analogue signal processing applications     

宽温区高温体硅CMOS倒相器的优化设计

在对体硅 CMOS倒相器直流特性、瞬态特性的高温模型和高温特性深入研究的基础上 ,提出了高温体硅 CMOS倒相器结构参数设计的考虑 ,给出了宽温区 (2 7～ 2 5 0℃ )体硅 CMOS倒相器优化设计的结果。模拟验证表明 ,所设计的体硅 CMOS倒相器在宽温区能满足下列电学参数设计指标 :输出高电平 Vo H>4 .95 V,输出低电平 Vo L<0 .0 5 V,转换电平 V*i (2 7℃ ) =2 .5 V,V*i(2 5 0℃ ) =2 .4 V,上升时间 tr(2 7℃ ) <110 ns,tr(2 5 0℃ ) <180 ns,下降时间 tf(2 7℃ ) <110 ns,tf(2 5 0℃ ) <16 0 ns。