15-nm base type-II InP/GaAsSb/InP DHBTs with F/sub T/=384 GHz and a 6-V BV/sub CEO/

Type-II InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a 15-nm base were fabricated by contact lithography: 0.73/spl times/11 /spl mu/m/sup 2/ emitter devices feature f/sub T/=384GHz (f/sub MAX/=262GHz) and BV/sub CEO/=6V. This is the highest f/sub T/ ever reported for InP/GaAsSb DHBTs, and an "all-technology" record f/sub T//spl times/BV/sub CEO/ product of 2304 GHz/spl middot/V. This result is credited to the favorable scaling of InP/GaAsSb/InP DHBT breakdown voltages (BV/sub CEO/) in thin collector structures.     

A 183 GHz f/sub T/ and 165 GHz f/sub max/ regrown-emitter DHBT with abrupt InP emitter

Small-area regrown emitter-base junction InP/In-GaAs/InP double heterojunction bipolar transistors (DHBT) using an abrupt InP emitter are presented for the first time. In a device with emitter-base junction area of 0.7 /spl times/ 8 /spl mu/m/sup 2/, a maximum 183 GHz f/sub T/ and 165 GHz f/sub max/ are exhibited. To our knowledge, this is the highest reported bandwidth for a III-V bipolar transistor utilizing emitter regrowth. The emitter current density is 6/spl times/10/sup 5/ A/cm/sup 2/ at V/sub CE,sat/ = 1.5 V. The small-signal current gain h/sub 21/ = 17, while collector breakdown voltage is near 6 V for the 1500-/spl Aring/-thick collector. The emitter structure, created by nonselective molecular beam epitaxy regrowth, combines a small-area emitter-base junction and a larger-area extrinsic emitter contact, and is similar in structure to that of a SiGe HBT. The higher f/sub T/ and f/sub max/ compared to previously reported devices are achieved by simplified regrowth using an InP emitter and by improvements to the regrowth surface preparation process.     

Effect of photodecomposed-PH/sub 3/ treatment on PN/InP metal-insulator-semiconductor diodes

The effect of photodecomposed phosphine (PD-PH/sub 3/) treatment on the interfacial properties of phosphorus nitride/indium phosphide (PN/InP) metal-insulator-semiconductor (MIS) structures has been investigated. It is demonstrated that PD-PH/sub 3/ treatment is effective in reducing the interface state density for PN/InP MIS diodes fabricated by photochemical vapour deposition (photo-CVD). An interface state density as low as 3.1*10/sup 11/ eV /sup -1/ cm/sup -2/ is achieved by an in situ photoprocess consisting of PD-PH/sub 3/ treatment and subsequent PN deposition.<>     

Graded base type-II InP/GaAsSb DHBT with f/sub T/=475 GHz

The first demonstration of a type-II InP/GaAsSb double heterojunction bipolar transistor (DHBT) with a compositionally graded InGaAsSb to GaAsSb base layer is presented. A device with a 0.4/spl times/6 /spl mu/m/sup 2/ emitter dimensions achieves peak f/sub T/ of 475 GHz (f/sub MAX/=265 GHz) with current density at peak f/sub T/ exceeding 12 mA//spl mu/m/sup 2/. The structure consists of a 25-nm InGaAsSb/GaAsSb graded base layer and 65-nm InP collector grown by MBE with breakdown voltage /spl sim/4 V which demonstrates the vertical scaling versus breakdown advantage over type-I DHBTs.     

Low-power InP/GaAsSb/InP DHBT cascode transimpedance amplifier with GBP/P/sub dc/ of 7.2 GHz/mW

A low-power high gain-bandwidth monolithic cascode transimpedance amplifier using novel InP/GaAsSb/InP DHBT technology was investigated. The amplifier exhibited state-of-the-art performance of 17.3 dB gain, 12 GHz bandwidth, 55 dB/spl Omega/ transimpedance, and a corresponding gain-bandwidth of 6.7 THz/spl Omega/ while consuming only 12.2 mW DC power. It also achieved good gain-bandwidth-product per DC power figure-of-merit (GBP/P/sub dc/) of 7.2 GHz/mW     

InGaAs/InP DHBTs with 120-nm collector having simultaneously high f/sub /spl tau//, f/sub max//spl ges/450 GHz

InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction.     

BV/sub CEO/--BV/sub CBO/ separation and sharpness of breakdown in high-speed bipolar transistors

The effect of secondary impact ionization by the noninitiating carrier on the near avalanche behavior of high-speed n-p-n bipolar transistors is studied. We show that secondary collector ionization by generated holes traveling back toward the base layer significantly reduces BV/sub CBO/ if the hole ionization coefficient is higher than that of electrons [/spl beta//sub p/(E)>/spl alpha//sub n/(E)]: positive feedback associated with a strong secondary ionization sharpens the breakdown characteristic by speeding up carrier multiplication and decreases separation between the open-base collector-emitter (BV/sub CEO/) and the open-emitter base-collector (BV/sub CBO/) breakdown voltages. The effect of secondary ionization on the BV/sub CEO/-BV/sub CBO/ separation has not previously been described. Multiplication coefficient comparisons for representative InP, GaAs, and Si collectors indicate all structures can sustain low-current above BV/sub CEO/ operation from a transport (nonthermal) point of view, although the different degrees of secondary ionization in various semiconductors lead to fundamental differences when InP is compared to GaAs and Si since for the latter materials /spl beta//sub p/(E)相似文献   

0.6-eV bandgap In/sub 0.69/Ga/sub 0.31/As thermophotovoltaic devices grown on InAs/sub y/P/sub 1-y/ step-graded buffers by molecular beam epitaxy

Single-junction, lattice-mismatched (LMM) In/sub 0.69/Ga/sub 0.31/As thermophotovoltaic (TPV) devices with bandgaps of 0.60 eV were grown on InP substrates by solid-source molecular beam epitaxy (MBE). Step-graded InAs/sub y/P/sub 1-y/ buffer layers with a total thickness of 1.6 /spl mu/m were used to mitigate the effects of 1.1% lattice mismatch between the device layer and the InP substrate. High-performance single-junction devices were achieved, with an open-circuit voltage of 0.357 V and a fill factor of 68.1% measured at a short-circuit current density of 1.18 A/cm/sup 2/ under high-intensity, low emissivity white light illumination. Device performance uniformity was outstanding, measuring to better than 1.0% across a 2-in diameter InP wafer indicating the promise of MBE growth for large area TPV device arrays.     

High-performance In/sub 0.53/Ga/sub 0.47/As thermophotovoltaic devices grown by solid source molecular beam epitaxy

In/sub 0.53/Ga/sub 0.47/As-based monolithic interconnected modules (MIMs) of thermophotovoltaic (TPV) devices lattice-matched to InP were grown by solid source molecular beam epitaxy. The MIM device consisted of ten individual In/sub 0.53/Ga/sub 0.47/As TPV cells connected in series on an InP substrate. An open-circuit voltage (V/sub oc/) of 4.82 V, short-circuit current density (J/sub sc/) of 1.03 A/cm/sup 2/ and fill factor of /spl sim/73% were achieved for a ten-junction MIM with a bandgap of 0.74 eV under high intensity white light illumination. Device performance uniformity was better than 1.5% across a full 2-in InP wafer. The V/sub oc/ and J/sub sc/ values are the highest yet reported for 0.74-eV band gap n-p-n MIM devices.     

High transconductance of 2.25 S/mm observed at 16 K for 195-nm-gate In/sub 0.75/Ga/sub 0.25/As/In/sub 0.52/Al/sub 0.48/As HEMT fabricated on [411]A-oriented InP substrate

We achieved a maximum transconductance (g/sub m/) of 2.25 S/mm at 16 K for a 195-nm-gate In/sub 0.75/Ga/sub 0.25/As/In/sub 0.52/Al/sub 0.48/As pseudomorphic high-electron mobility transistor (PHEMT) fabricated on a [411]A-oriented InP substrate, which is the highest value ever reported for HEMTs. This PHEMT also showed a much enhanced cutoff frequency (f/sub T/) of 310 GHz at 16 K, compared with its room temperature value (245 GHz). The significantly enhanced g/sub m/ and f/sub T/ at 16 K can be attributed to the higher saturation velocity in the region "under the gate," which is caused not only by suppressing the phonon scattering, but also by suppressing the interface roughness scattering due to the "(411)A super-flat InGaAs/InAlAs interfaces" (effectively atomically flat heterointerfaces over a wafer-size area).     

InGaAs-InP metamorphic DHBTs grown on GaAs with lattice-matched device performance and f/sub /spl tau//, f/sub max/>268 GHz

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBTs) were grown on a GaAs substrate using a metamorphic buffer layer and then fabricated. The metamorphic buffer layer is InP - employed because of its high thermal conductivity to minimize device heating. An f/sub /spl tau// and f/sub max/ of 268 and 339 GHz were measured, respectively - both records for metamorphic DHBTs. A 70-nm SiO/sub 2/ dielectric sidewall was deposited on the emitter contact to permit a longer InP emitter wet etch for increased device yield and reduced base leakage current. The dc current gain /spl beta/ is /spl ap/35 and V/sub BR,CEO/=5.7 V. The collector leakage current I/sub cbo/ is 90 pA at V/sub cb/=0.3 V. These values of f/sub /spl tau//, f/sub max/, I/sub cbo/, and /spl beta/ are consistent with InP based DHBTs of the same layer structure grown on a lattice-matched InP substrate.     

MESFET-like transferred-electron devices in In/sub 0.53/Ga/sub 0.47/As

In/sub 0.53/Ga/sub 0.47/As transferred-electron devices with Schottky-gate electrodes were fabricated. These devices can be used in optoelectronic circuits on InP or as millimetre wave oscillators. For the realisation of the gate electrode several enhancement layers were tested to increase the Schottky barrier height on In/sub 0.53/Ga/sub 0.47/As. The triggering of single dipole domains in the device was demonstrated.<>     

Reduction of 1/f noise in multiplexed linear In/sub 0.53/Ga/sub 0.47/As detector arrays via epitaxial doping

A significant (2-5*) reduction in 1/f noise was observed in In/sub 0.53/Ga/sub 0.47/As photodetector arrays read out by a PMOS multiplexer, when the epitaxial InP cap layer doping was changed from undoped to sulfur-doped n type of about 3*10/sup 16/ cm/sup -3/. A further decrease was observed when the InP buffer layer was also changed from undoped to sulfur-doped n type of about 5*10/sup 17/ cm/sup -3/. Data was presented for the variation of 1/f noise, within a temperature range of 18 degrees C to -40 degrees C. Surface states at the InP cap/SiN interface appears to be the primary source of 1/f noise, with the bulk states at the n/sup -/In/sub 0.53/Ga/sub 0.47/As buffer hetero-interface as a secondary source. Increased n-type doping in the high-bandgap InP cap and buffer layers may reduce electron trapping, and thus 1/f noise. The measured noise spectrum of InGaAs photodetectors varies as f/sup y/ with y being approximately -0.45 for device structures with doped and undoped InP can layers. For a doped InP buffer layer, this value of y is -0.3.<>     

Temperature dependence of breakdown and avalanche multiplication in In/sub 0.53/Ga/sub 0.47/As diodes and heterojunction bipolar transistors

The avalanche multiplication and impact ionization coefficients in In/sub 0.53/Ga/sub 0.47/As p-i-n and n-i-p diodes over a range of temperature from 20-400 K were measured and shown to have negative temperature dependence. This is contrary to the positive temperature dependence of the breakdown voltage measured on InP/In/sub 0.53/Ga/sub 0.47/As heterojunction bipolar transistors (HBTs) in this and previous works. It is shown that the collector-base dark current and current gain can be the overriding influence on the temperature dependence of breakdown in InP/In/sub 0.53/Ga/sub 0.47/As HBTs and could explain previous anomalous interpretations from the latter.     

Threshold voltage of submicron Ga/sub 0.47/In/sub 0.53/As HIGFETs

Presents threshold voltage data for Al/sub 0.48/In/sub 0.52/As/Ga/sub 0.47/In/sub 0.53/As/InP heterostructure insulated gate FETs (HIGFETs) with gate lengths from 1.2 mu m to 0.4 mu m. The refractory-gate, self-aligned fabrication process was applied to MBE-grown structures with 300 AA Ga/sub 0.47/In/sub 0.53/As channels and semi-insulating superlattice buffers to achieve sharp pinchoff with excellent threshold uniformity. HIGFETs with L/sub g/=1.2 mu m showed a threshold voltage of -0.076+or-0.019 V, making them well-suited to application in direct-coupled FET logic (DCFL) circuits.<>     

High bandwidth and low-leakage current InP-In/sub 0.53/Ga/sub 0.47/As-InP DBHTs on GaAs substrates

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBTs) were grown on GaAs substrates. A 284-GHz power-gain cutoff frequency f/sub max/ and a 216-GHz current-gain cutoff frequency f/sub /spl tau// were obtained, presently the highest reported values for metamorphic HBTs. The breakdown voltage BV/sub CEO/ was >5 V while the dc current gain /spl beta/ was 21. High thermal conductivity InP metamorphic buffer layers were employed in order to minimize the device thermal resistance.     

Collector-pedestal InGaAs/InP DHBTs fabricated in a single-growth, triple-implant process

This letter reports InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBTs) employing an N/sup +/ subcollector and N/sup +/ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C/sub cb/ associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N/sup +/ subcollector that lies underneath the base ohmic contact, as well as compensate the /spl sim/1-7/spl times/10/sup -7/ C/cm/sup 2/ surface charge at the interface between the indium phosphide (InP) substrate and the N/sup $/collector drift layer. By implanting the subcollector, C/sub cb/ associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C/sub cb/ by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f/sub /spl tau// and 403-GHz f/sub max/. The dc current gain /spl beta//spl ap/38, BV/sub ceo/=6.0 V, BV/sub cbo/=5.4 V, and I/sub cbo/<50 pA at V/sub cb/=0.3 V.     

InGaAs-InP mesa DHBTs with simultaneously high f/sub /spl tau// and f/sub max/ and low C/sub cb//I/sub c/ ratio

We report an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT), fabricated using a conventional triple mesa structure, exhibiting a 370-GHz f/sub /spl tau// and 459-GHz f/sub max/, which is to our knowledge the highest f/sub /spl tau// reported for a mesa InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The collector semiconductor was undercut to reduce the base-collector capacitance, producing a C/sub cb//I/sub c/ ratio of 0.28 ps/V at V/sub cb/=0.5 V. The V/sub BR,CEO/ is 5.6 V and the devices fail thermally only at >18 mW//spl mu/m/sup 2/, allowing dc bias from J/sub e/=4.8 mA//spl mu/m/sup 2/ at V/sub ce/=3.9 V to J/sub e/=12.5 mA//spl mu/m/sup 2/ at V/sub ce/=1.5 V. The device employs a 30 nm carbon-doped InGaAs base with graded base doping, and an InGaAs-InAlAs superlattice grade in the base-collector junction that contributes to a total depleted collector thickness of 150 nm.     

Barrier height enhancement of InP Schottky junctions by treatment with photo-decomposed PH/sub 3/

Au-InP Schottky junctions are formed on a surface treated by ArF excimer laser photolytic process of phosphine (PH/sub 3/) gas. The Schottky junction has a metal-insulator-semiconductor (MIS) structure because of the existence of a thin P layer deposited on the InP surface. The barrier height increases to 0.65 eV and the reverse current is reduced by more than two orders of magnitude compared with the case of Schottky junctions without photolytic treatment. The Richardson constant of the novel Schottky junction is evaluated as 0.126 A cm/sup -2/ K/sup -2/ from the temperature dependence of the saturation current.<>     

Low-temperature MBE-grown In/sub 0.52/Ga/sub 0.18/Al/sub 0.30/As/InP optical waveguides

The MBE growth of In/sub 0.52/Ga/sub 0.18/Al/sub 0.30/As ( lambda /sub g/=1.06 mu m) layers in the temperature range of 400-450 degrees C was demonstrated to give high-quality optical waveguides which not only exhibit low propagation losses as low as 0.5 dB/cm at lambda =1.55 mu m but concomitantly high resistivity of >10/sup 4/ Omega cm. The refractive index of In/sub 0.52/Ga/sub 0.18/Al/sub 0.30/As was estimated to be 3.207+or-0.03 at lambda =1.55 mu m.<>