A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.     

A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver

A low-IF polyphase channel filter for a dual-mode Bluetooth/Zigbee transceiver is described. Implemented in a standard 0.18-/spl mu/m CMOS process, the filter has a fifth-order 0.5-dB equiripple bandpass response and employs novel transconductor and preamplifier designs. It consumes /spl les/1 mW and achieves image band rejection /spl ges/44 dB, input referred noise of /spl les/52.2 /spl mu/Vrms and input referred third-order intermodulation intercept of /spl ges/20 dBVp, which gives a spurious-free dynamic range of /spl ges/68.4 dB. Chip area including its tuning circuit is 0.23 mm/sup 2/.     

A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator

A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 /spl mu/m CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.     

A low-power high-PSRR current-mode microphone preamplifier

Bionic implants for the deaf require wide-dynamic-range low-power microphone preamplifiers with good wide-band rejection of the supply noise. Widely used low-cost implementations of such preamplifiers typically use the buffered voltage output of an electret capacitor with a built-in JFET source follower. We describe a design in which the JFET microphone buffer's output current, rather than its output voltage, is transduced via a sense-amplifier topology allowing good in-band power-supply rejection. The design employs a low-frequency feedback loop to subtract the dc bias current of the microphone and prevent it from causing saturation. Wide-band power-supply rejection is achieved by integrating a novel filter on all current-source biasing. Our design exhibits 80 dB of dynamic range with less than 5 /spl mu/V/sub rms/ of input noise while operating from a 2.8 V supply. The power consumption is 96 /spl mu/W which includes 60 /spl mu/W for the microphone built-in buffer. The in-band power-supply rejection ratio varies from 50 to 90 dB while out-of-band supply attenuation is greater than 60 dB until 25 MHz. Fabrication was done in a 1.5-/spl mu/m CMOS process with gain programmability for both microphone and auxiliary channel inputs.     

Low-voltage wideband compact CMOS variable gain amplifier

A novel low-voltage wideband CMOS variable gain amplifier (VGA) is proposed. Using a 0.13 /spl mu/m CMOS technology, the VGA exhibits a linear-dB controllable gain range of 40 dB with a bandwidth in excess of 130 MHz, while drawing only 50 /spl mu/A from a single 1 V power supply voltage.     

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

CMOS exponential function generator

A new CMOS exponential function generator is presented. The proposed circuit is compact, with low power and wide dynamic range. The proposed circuit has been fabricated in a 0.50 /spl mu/m CMOS process. Experimental results show that the output range of the proposed exponential function generator can be more than 15 dB with the linear error less than /spl plusmn/ 0.5 dB. The supply voltage is /spl plusmn/ 1.5 V and the power dissipation is less than 0.4 mW. Experimental results are given to demonstrate the proposed circuit.     

A new CMOS pixel structure for low-dark-current and large-array-size still imager applications

A pixel structure for still CMOS imager application called the pseudoactive pixel sensor (PAPS) is proposed and analyzed in this paper. It has the advantages of a low dark current, high signal-to-noise ratio, and a high fill factor over the conventional passive pixel sensor imager or active pixel sensor imager. The readout circuit called the zero-bias column buffer-direct-injection structure is also proposed to suppress both the dark current of the photodiode and the leakage current of row switches by keeping both biases of photodiode and the parasitic p-n junction in the column bus at or near zero voltage. The improved double delta sampling circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352/spl times/288 (CIF) has been fabricated by using a 0.25-/spl mu/m single-poly-five-level-metal (1P5M) n-well CMOS process. The pixel size is 5.8 /spl mu/m/spl times/5.8 /spl mu/m. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/s. The proposed still CMOS imager has a fill factor of 58%, chip size of 3660 /spl mu/m/spl times/3500 /spl mu/m, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with a low dark current and high resolution.     

A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution

A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.     

Robust highly linear high-frequency CMOS OTA with IM3 below - 70 dB at 26 MHz

An enhanced configuration for a linearized MOS operational transconductance amplifier (OTA) is proposed. The proposed fully differential OTA circuit is based on resistive source degeneration and an improved adaptive biasing technique. It is robust to process variation, which has not been fully shown in previously reported linearization techniques. Detailed harmonic distortion analysis demonstrating the robustness of the proposed OTA is introduced. The transconductance gain is tunable from 160 to 340 /spl mu/S with a third-order intermodulation (IM3) below -70 dB at 26 MHz. As an application, a 26-MHz second-order low-pass filter fabricated in TSMC 0.35-/spl mu/m CMOS technology with a power supply of 3.3 V is presented. The measured IM3 with an input voltage of 1.4 Vpp is below - 65 dB for the entire filter pass-band, and the input referred noise density is 156nV//spl radic/Hz. The cutoff frequency of the filter is tunable in the range of 13-26 MHz. Theoretical and experimental results are in good agreement.     

A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications

A CMOS local oscillator using a programmable delayed-lock loop based frequency multiplier is present in this paper. The maximum measured output frequency is 1.2 GHz. The frequency of the output clock is 8/spl times/ to 10/spl times/ of an input reference clock between 100 to 150 MHz at simulation. No LC-tank is used in the proposed design such that the power dissipation as well as the active area is drastically reduced. The design is carried out by TSMC 1P5M 0.25 /spl mu/m CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the voltage-controlled delay tap line at the midway of the working range. Meanwhile, the power dissipation is 52.5 mW at 1.2 GHz output.     

High-performance active polyphase filter design for digital TV tuner

This paper presents the polyphase filter design for the tuner of DTV front-end system. The polyphase filter is designed with an active circuit to improve the chip performance. Most of passive capacitor and resistor components are replaced with MOS transistors. The proposed method not only can reduce the chip area but also gain the signal level. For the prototyping implementation, the current channel bands in Taiwan are referred, which the frequency range is from 530 to 602 MHz for DTV programs. In experiments, the polyphase filter can achieve 85 dB for the image rejection in the center frequency. The main signal can be gained about 2-5 dB without using extra amplifier. The chip size is about 0.09 mm², and the average power dissipation is about 15 mW, when the chip technology employed TSMC 0.35 μm CMOS process. The proposed chip outperforms with less area and higher gain.     

A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mV/sub pp/ at 30 MHz. The OTA, fabricated in 0.5-/spl mu/m CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter's group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a /spl plusmn/1.65-V power supply.     

Wideband high dynamic range CMOS variable gain amplifier for low voltage and low power wireless applications

A high frequency CMOS variable gain amplifier (VGA) employing a new gain stage cell is proposed. A design technique based on the proposed VGA enables enhancement of its operating frequency up to about 350 MHz with a gain control range of 84 dB. The power consumption of the VGA implemented using a 0.18 /spl mu/m CMOS standard process is about 3 mA at 1.8 V supply voltage.     

Compact power-efficient class-AB CMOS exponential voltage to voltage converter

A novel implementation of a rail-to-rail exponential voltage to voltage converter is presented. It is based on a pseudo-exponential approximation that is easily achieved by the nonlinear currents of a class-AB transconductor. Measurement results for a 0.5 /spl mu/m CMOS technology show a 52 dB output voltage range with linearity error less than /spl plusmn/2 dB using a dual supply voltage of /spl plusmn/750 mV. The power dissipation is less than 40 /spl mu/W.     

A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system

A full CMOS seventh-order linear phase filter based on g/sub m/-C biquads with a -3-dB frequency of 200 MHz is realized in 0.35-/spl mu/m CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both low-distortion figures and high-frequency operation. The common-mode feedback (CMFB) employed takes advantage of the filter architecture; incorporating the load capacitors into the CMFB loop improves further its phase margin. A very simple automatic tuning system corrects the filter deviations due to process parameter tolerances and temperature variations. The group delay ripple is less than 5% for frequencies up to 300 MHz, while the power consumption is 60 mW. The third-harmonic distortion is less than -44 dB for input signals up to 500 mV/sub pp/. The filter active area is only 900 /spl times/ 200 /spl mu/m/sup 2/. The supply voltages used are /spl plusmn/1.5 V.     

Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver

Subharmonically pumped frequency down- and upconversion circuits are implemented in 0.18-/spl mu/m mixed-mode CMOS technology for 2-GHz direct-conversion WCDMA transceiver applications. These circuits operate in quadrature double-balanced mode and a required octet-phases (0/spl deg/, 45/spl deg/, 90/spl deg/, 135/spl deg/, 180/spl deg/, 225/spl deg/, 270/spl deg/, and 315/spl deg/) local oscillator (LO) signal comes from an active multiphases LO generator composed of a polyphase filter and active 45/spl deg/ phase shifting circuits. For linearity improvement, predistortion compensation and negative feedback schemes are used in the frequency down- and upconversion circuits, respectively. The downconverter achieves a conversion voltage gain of 20 dB (to 1-M/spl Omega/ load), 4-dBm IIP3 (18-dBm OIP3 to 50-/spl Omega/ load), 41-dBm IIP2 and 8.5-dB DSB NF at 1-MHz IF frequency, consuming 13.4 mA from 1.8-V supply, in the WCDMA Rx band (2110-2170 MHz). The upconverter, operating as two switched gain modes in the WCDMA Tx band (1920-1980 MHz), consumes 19.4 mA from 1.8-V supply and shows 14.5-dB conversion power gain, 15 -dBm OIP3 (0.5-dBm IIP3) and -11 dBm P/sub 1dB/ at maximum gain mode. At minimum gain mode, it realizes -0.3-dB conversion loss, 10.7-dBm OIP3 (11-dBm IIP3) and 0-dBm P/sub 1dB/, respectively. 3GPP WCDMA modulation tests are performed for both up- and downconversion circuits and the results are discussed in this paper.     

OTA linearity enhancement technique for high frequency applications with IM3 below -65 dB

A technique to enhance the linearity of continuous-time operational transconductance amplifiers (OTA)-C filters working at high frequencies is proposed. Each OTA consumes 10.5 mW and the transconductance can be tuned from 70 to 160 /spl mu/A/V while the IM3 remains below -70 dB up to 50 MHz for a 1.3-V/sub pp/ differential input. For a 20-MHz low-pass second-order filter implementation, the measured IM3 with an input voltage of 1.3 V/sub pp/ is below - 65 dB. The supply voltage is 3.3 V. Experimental results of the circuit, fabricated in a standard CMOS 0.35-/spl mu/m technology, are presented.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.