一种低功耗可编程开关电容的分压电路

介绍了一种低功耗可编程分压电路,其静态功耗为零,输出电压不受工艺、温度影响,因此,在工程上具有广泛的应用前景。     

A Low-Power Field-Programmable Gate Array Routing Fabric

This paper describes a new programmable routing fabric for field-programmable gate arrays (FPGAs). Our results show that an FPGA using this fabric can achieve 1.57 times lower dynamic power consumption and 1.35 times lower average net delays with only 9% reduction in logic density over a baseline island-style FPGA implemented in the same 65-nm CMOS technology. These improvements in power and delay are achieved by 1) using only short interconnect segments to reduce routed net lengths, and 2) reducing interconnect segment loading due to programming overhead relative to the baseline FPGA without compromising routability. The new routing fabric is also well-suited to monolithically stacked 3-D-IC implementation. It is shown that a 3-D-FPGA using this fabric can achieve a 3.3 times improvement in logic density, a 2.51 times improvement in delay, and a 2.93 times improvement in dynamic power consumption over the same baseline 2-D-FPGA.     

一种低功耗高分辨率可编程增益放大器的设计

该文设计了一种用于零中频接收机的低功耗高分辨率可编程增益放大器。该放大器采用源级电阻负反馈结构,利用跨导增强技术提高了放大器的线性度,并加入补偿电容扩展了带宽,实现了低功耗设计。该可编程增益放大器采用0.25μmCMOS工艺,仿真结果表明,在0.5pF负载电容的情况下,放大器增益动态的范围是0～62dB,2.5V供电电压下最大功耗为2.2mW,增益分辨率达到0.25dB,带宽10MHz,0dB增益时输入三阶交调点为17.9dBm。     

低功耗电荷泵可编程增益放大器的设计与实现

提出了一种低功耗电荷泵可编程增益放大器(PGA)电路模型.通过简单数学建模和VerilogA仿真,得出了一般自动增益控制电路(AGC)优化稳定时间的条件和简化模型,通过ADC、电荷泵,进一步简化电路,降低功耗,并实现数字控制功能.根据这种设计,采用TSMC 0.18 μm CMOS 单层多晶硅6层金属工艺,实现了一个功耗电流为1 mA、线性增益范围为60 dB的电荷泵可编程增益放大器.     

A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock

A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-${rm mu}hbox{m}$ CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 $hbox{mm}^{2}$ and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.      

一种用于FPGA的新型混合布线算法

布尔可满足性是计算机科学中最基础的问题之一,已经出现了包括著名的基于查找的SAT算法在内的各种算法.对于传统的一次布通一条线网的方法,基于布尔可满足性的算法有着独特的优点,例如:同步线网嵌入及可布通性确定.然而基于SAT的布线法在可扩展性方面有很大缺陷.而另一方面,几何查找布线算法即使具有广泛的拆线重布线的能力,但当北一个问题具有严格的布线约束条件时,它在布线方案收敛方面存在很大困难.文章提出了将一种布尔可满足性算法与VPR430相结合的新型、有效的混合布线算法.试验结果表明与相应的纯几何布线算法相比,这种算法在运行时间上有了极大的改善(减少了29%),并且对布线整体方案无不良影响.     

A Low-Power Programmable Bandpass Filter Section for Higher Order Filter Applications

We present a programmable, continuous-time bandpass filter that is extremely compact, power efficient, and can cover a wide range of frequencies (10 Hz-10 MHz). This capacitively coupled current conveyor (C ⁴) has a second-order bandpass transfer function and is capable of being used as a basic bandpass-filter element to create high-order filters. The use of floating-gate transistors helps to ease the difficulties of effectively utilizing G _m-C filters by providing precise, programmable current sources that set the filter's time constants. Additionally, we provide an algorithmic design approach for constructing these bandpass filters to meet any given specifications. This bandpass filter is ideally suited to large filter-bank applications because of its small size and low-power demands.     

基于FPGA的可编程电阻的设计

现在市场上的各种电阻和电阻箱有不足之处,不能满足一些研发场所的要求,为了解决这一问题,本文介绍一种基于FPGA的可直接输入阻值提供不同电阻的设计方法。FPGA通过控制继电器的吸合,从而确定与其并联的电阻的接入与否,最后通过电阻的叠加得到不同阻值。介绍了该设计的工作原理及软件设计思想,并有部分仿真结果。这种设计使用8421编码原则和硬件描述语言,减少了一些元器件的使用。相比于市场上的产品,其稳定性更高,抗干扰性更强,体积也更小,同时,它的操作更简便,显示更直观。     

Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations

In order to meet superior performance metrics along with denser logic integration and device miniaturization, FPGAs have become more susceptible to transistor related aging, coupled with manufacturing defects owing to increased complexity in photolithographic techniques, thereby reducing the reliability and lifetime. In this paper, we propose certain built-in circuit techniques that are integrated with the original design, to localize the source of any hard or soft errors, if any, with tolerable penalty in performance, against acceptable time and/or hardware redundancy. Circuit realization on FPGA has been achieved through primitive instantiation and constrained placement, such that the exact location from which the fault has emanated can be traced, and bypassed for mapping any subsequent logic on the same FPGA. The adopted design paradigm which had earlier proved its potential for high performance FPGA based designs, has now been adopted to facilitate fault localization.     

A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems

A low-power, area-efficient four-way 32-bit multifunction arithmetic unit has been developed for programmable shaders for handheld 3D graphics systems. It adopts the logarithmic number system (LNS) at the arithmetic core for the single-cycle throughput and the small-size low-power unification of various complicated arithmetic operations such as power, logarithm, trigonometric functions, vector-SIMD multiplication, division, square root and vector dot product. 24-region and 16-region piecewise linear logarithmic and antilogarithmic converters are proposed with 0.8% and 0.02% maximum conversion error, respectively. All the supported operations are implemented with less than 6.3% operation error and unified into a single arithmetic platform with maximum four-cycle latency and single-cycle throughput. A 93 K gate test chip is fabricated using one-poly five-metal 0.18-mum CMOS technology. It operates at 210 MHz with maximum power consumption of 15.3 mW at 1.8 V.     

FPGA布线结构的蒙特卡罗评估

提出一种基于蒙特卡罗技术的FPGA结构研究新方法。该方法在布线资源中随机产生均匀分布的开路故障,并绕开障碍物布线互连,不依赖于CAD算法和基准电路。开关块拓扑分析实例表明该方法与CAD方法的结论一致,而评估时间从15小时缩短到15分钟。     

FPGA 布线开关的电路设计

在分析隔离岛式FPGA布线结构的基础上，设计了导通晶体管布线开关和三态缓冲布线开关。设计了级恢复电路，解决了导通晶体管开关引起的静态功耗问题。提出了基于扇人的三态缓冲开关bufm，避免了一般缓冲开关的扇出问题。最后，我们对各种布线开关的延时特性作了比较，提出了一些合理的建议。     

一种FPGA新型逻辑单元结构的设计

提出了一种FPGA可编程逻辑单元的新结构,该结构具有较多的输入端数和输出端数,并加入了专用的快速进位逻辑、专用级联链等功能,使得这种结构可用来实现任意4输入的逻辑函数和某些高达11个变量的输入函数;这种结构还可同时实现两个任意3输入的逻辑函数或最多5输入的某些函数,而且也能实现快速的进位计算和高扇入的逻辑运算.与目前一些商业FPGA的逻辑结构进行比较表明,本文提出的单元结构不仅具有较高的资源利用率,而且在性能和函数实现能力上都有较大的优势.     

可编程FIR滤波器的FPGA实现

介绍了FIR滤波器的基本的线性相位结构及FIR滤波器的抽头系数SD算法编码。给定滤波器的数字指标,用MATLB设计抽头系数,最后用Verilog HDL语言实现了一个16阶的FIR低通滤波器并在QuartusⅡ上仿真,并对仿真结果与理论值进行比较,波形仿真结果和理论值相吻和,最后将编程数据文件下载到FPGA芯片上。对于不同性能的FIR滤波器,抽头系数是变化的,因此只要对本设计的抽头系数重新在线配置,就可以实现不同的FIR滤波器。     

Design of Integrated Selection and Recirculation Circuitry for a High-Speed, Low-Power, Magnetic Thin-Film Memory

The circuit design for a high-speed, low-power, magnetic thin-film memory is described. The modest operating-current requirements of the memory element, 50 milliampere word currents and 40 milliampere bit currents, permit the use of integrated selection and recirculation circuits. The selection system uses one transistor per word line and has a matrix array of word drivers and word switches to select one word line. Word current rise time is 2 to 3 nanoseconds. The 1-millivolt readout signal, 6 nanoseconds in duration, is amplified by means of a high-gain (1400), wide-band (50 Mc/s) sense amplifier with a differential input stage. Information is written into the memory with a bit driver which generates 40 milliampere current pulses of either polarity. Design considerations such as the ac coupling in the sense arnplifier, the relation between amplifier internal noise and system mean free time between errors, and the minimization of noise are discussed. A variety of transistor geometries was used to optimize the devices to the individual circuit functions. These geometries are illustrated.     

适用于可编程IP核的布图方法

提出了一套适用于可编程IP核的布图系统PRPIC(Placement and Routing System for Programmable IP Core)。该系统对可编程IP核的结构进行抽象建模,并根据该模型生成用于布图的实际电路的有向资源图,从而可以灵活地支持规模和结构不同的可编程IP核。根据可编程IP核结构和应用等方面的特殊性,对布图算法进行了优化。     

Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications

This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of $2 ^{7} -1$, $2 ^{10} -1$, $2 ^{15} -1$, $2 ^{23} -1$, and $2 ^{31} -1~hbox{b}$ according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 ${hbox {ps}}_{rm rms}$, and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18-$mu{hbox {m}}$ CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators.      

基于FPGA的可编程电压源系统设计

介绍一种基于FPGA的可编程电压源系统的设计与实现.采用FPGA为控制芯片,应用Quartus Ⅱ软件和硬件描述语言为工具,通过数/模转换和运放把数字信号转换成模拟电压信号.实验表明,该系统操作灵活方便,稳定性强,调压精度高,电压可调范围大(0～26 V),具有很好的实用性和工程参考价值.     

一种改进的子集可满足性算法用于FPGA布线

介绍了用布尔可满足性(SAT)和子集可满足性(sub-SAT)算法解决FPGA的详细布线问题。在布线资源固定的FPGA布线环境中,布尔公式可以证明所给电路的不可布通性,这一点要优于典型的one-net-at-a-time方法。子集可满足性方法把一个有N个约束的"严格的"SAT问题转换成一个新的"松弛的"SAT问题,仅当在原始问题中变量的不可满足个数不超过阈值k(kN)时,这一问题是可满足的。它改进了布尔可满足性,但是却产生了很多额外的变量和子句。针对这一问题,提出了用伪布尔可满足性(PBS)来消除子集可满足性公式带来的缺点。初步的实验结果表明,把这个方法加入子集可满足性方法中可以减少变量和子句数量,并显著减少运行时间。     

A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay

This brief presents a new circuit architecture for linear-in-decibel, constant-bandwidth variable gain amplifier (VGA). To obtain high linearity under low-voltage operation, this VGA is a closed-loop structure. In loop amplifier design, two techniques are applied: first, the loop amplifier is given finite input impedance. This arrangement keeps the VGA bandwidth constant under different gain setting. Second, a current-buffered compensation is applied for loop stability. Compared to the Miller compensation, this method achieves wider bandwidth. The prototype chip using 0.18-mum CMOS technology demonstrates that -10- to 20-dB gain and 0.5- to 30-MHz bandwidth can be programmed independently. The group delay difference within 30-dB gain control range is smaller than 1%. The total circuit dissipates 1.35 mA from a 1.8-V supply