A numerical approach based on transient thermal analysis toestimate the safe operating frequencies of thyristors

The spatio-temporal distribution of temperatures in high-power SCRs used for switching high di/dt current pulses were simulated using the finite element method (FEM). Two types of SCRs, with amplifying gate (unshorted device), and without amplifying gate (shorted device) structures, were analyzed. The details of the numerical simulation, such as the meshing strategy, the heat source model and the boundary conditions are discussed. Based on the analysis, the failure temperature of the unshorted device was computed to be 1100°C. The peak temperature in the shorted device was, however, found to be 335°C. The instantaneous cooling cycles of the devices and their cooling time constants, as obtained from the simulations, are presented. Based on these parameters, the safe operating frequencies of these devices were estimated     

Two-dimensional computer design of dual-ring thyristors

The main 2-dimensional equations are presented for the basic computer model of dual-ring amplifying gate thyristors (d.r.t.). These criteria ensure the maintenance of the very high di/dt capability of these devices in any possible triggering conditions.     

Computer-aided experimental investigation of the correct turn-on in thyristors with amplifying gate

A 2-dimensional computer model has been developed for the analysis of the amplifying gate thyristors correct turn-on at the auxiliary emitter prior to the main one. The results of investigation were used in the design of devices having essentially the same di/dt high capability in any possible turn-on conditions.     

Behavior of thyristors under transient conditions

The capability of gate-triggered thyristors to withstand steep wavefront, high-current pulses (i.e., di/dt capability) is a function of both junction temperature and frequency of operation. Localized internal heating occurs during turn-on and may lead to thermal runaway. The conditions required for this to occur have been determined by destructively testing many devices. The initial conducting area of a thyristor largely determines di/dt capability, which is not necessarily related to the size of the device but is a function of the design of the gate region. Gate drive is very important for determining the di/dt capability of a thyristor having a conventional gate design. Two devices which have been designed to increase the initial conducting area are discussed. One of these devices, if improperly designed, can lose its effectiveness with high gate drive. This characteristic can be studied by observing the reverse recovery current immediately following short forward current pulses.     

金属氧化物半导体控制晶闸管的di/dt优化

金属氧化物半导体控制晶闸管(MCT)相比于绝缘栅双极型晶体管(IGBT)具有高电流密度、低导通压降和快速开启等优势,在高压脉冲功率领域具有广阔的应用前景.作为脉冲功率开关,MCT开启过程对输出脉冲信号质量有很大影响.采用理论分析并结合仿真优化重点研究了MCT开启瞬态特性.通过对MCT开启过程进行详细地理论分析推导,给出了MCT开启过程中阳极电流和上升时间的表达式.结合Sentaurus TCAD仿真优化,将MCT开启过程中电流上升速率(di/dt)由40 kA/s提升至80 kA/s,极大地改善了器件开启瞬态特性.最后,总结提出了提高器件开启瞬间di/dt的设计途径.     

Inverter light triggered thyristor with unique arm-structure amplifying gate

A 1200-V 200-A directly light triggered thyristor suitable for inverter application has been developed. A new amplifying gate design with a second amplifying stage was used in achieving a factor of 15 to 50 increase in gate sensitivity without any loss indV/dtcapability and only a small (less than a factor of two) reduction in devicedi/dtrating, despite a ten times smaller initial turn-on line length. In all, three versions were made with gate threshold currents down to 1 mA anddV/dtcapabilities to 1000 V/µs. All three types had 60-Hz di/dt capabilitLes of about 250 A/µs at 125 deg TJand turn-off times of approximately 25 µs. The new light sensitive amplifying gate stage design features a gate thyristor region with extending arms for high gate sensitivity, the inner portion of which is just large enough to accommodate initial on-region spreading duriag the short on-time of the gate stage. The arms increase gate sensitivity while contributing very little to the overalldV/dtcurrent. The turn-on speed can be accounted for by most of the inner region being turned on by the photogate pulse. Like regular electrically fired thyristors, a gate overdrive factor is important. With these devices an overdrive factor of about 3 to 5 is needed for highdi/dtturn-on whereas in an electrically triggered device this factor is closer to 10.     

High-power dual amplifying gate light triggered thyristors

The feasibility of directly light triggering a high power phase control thyristor is investigated. Work is described on an optically triggered gated 53-mm diameter 2600-V 1000-A thyristor which is similar to an electrically gated production version. Test results describing the response of this thyristor to various optical signals are presented. Our work has shown that this cell can be directly triggered by light at an equivalent gate current which is a factor of three below its present dynamic gate requirements and still largely retain all its blocking and dynamic characteristics. This improvement is obtained by the use of a second very sensitive amplifying gate stage which is responsive to light. All wafer processing of the light sensitive thyristor was carried out on standard production lines. Tests made on static dV/dt, di/dt, blocking voltage, and leakage current on light sensitive devices all closely match parameters of the standard electrically fired equivalent cell.     

The di/dt capability of thyristors

This paper describes an experimental investigation of the di/dt failure mechanism of thyristors. The location of the initial turn-on region and the spread of the "on" region were observed on a specially designed thyristor having many monitoring electrodes. The turn-on process was studied for triggering by gate, by breakover, and by dv/dt. In many cases it was found that turn-on occurred at almost the same region, whether it was triggered by breakover or by dv/dt. This area coincided with the final holding position in the turn-off process. The di/dt capability of the thyristor was measured. It was found that the capabilities were almost the same for the three triggering methods. The destruction temperature in the di/dt test was estimated from the area of the burn-out spots and the energy dissipation.     

Role of the amplifying gate in the turn-on process of involutestructure thyristors

The switching characteristics of involute thyristors with and without the amplifying gate structure are discussed. The effects of peak gate currents (10-100 A) on the anode current di/dt, switching delay, and energy loss in both types of devices are presented. The performance of the devices without the amplifying gate was far superior than that of the devices with the amplifying gate. A model is presented to explain this difference. Thyristors without the amplifying gate successfully switched anode currents on the order of 12.6 kA, at a di/dt of 100000 A/μs, from an anode voltage of 2 kV on a single-shot basis     

Silicon carbide PiN and merged PiN Schottky power diode models implemented in the Saber circuit simulator

Dynamic electrothermal circuit simulator models are developed for silicon carbide power diodes. The models accurately describe the temperature dependence of on-state characteristics and reverse-recovery switching waveforms. The models are verified for the temperature dependence of the on-state characteristics, and the di/dt, dv/dt, and temperature dependence of the reverse-recovery characteristics. The model results are presented for 1500 V SiC Merged PiN Schottky (MPS) diodes, 600 V Schottky diodes, and 5000 V SiC PiN diodes. The devices studied have current ratings from 0.25 A to 5 A and have different lifetimes resulting in different switching energy versus on-state voltage trade-offs. The devices are characterized using a previously reported test system specifically designed to emulate a wide range of application conditions by independently controlling the applied diode voltage, forward diode current, di/dt, and dv/dt at turn-off. A behavioral model of the test system is implemented to simulate and validate the models. The models are validated for a wide range of application conditions for which the diode could be used.     

牵引用3 300 V平面栅IGBT栅极台面结构研究

针对机车牵引用3 300 V/1 500 A IGBT功率模块,采用TCAD仿真工具研究了不同栅极结构对器件静态和动态参数的影响。当平面栅IGBT采用栅极台面结构且台面厚度逐渐降低时,器件的静态阻断电压提高,开关损耗降低,但是器件的开关时间增加;此外,关断时过快的dv/dt会引起栅极电压振荡,开启时过快的di/dt会引起很大的电流过冲,导致器件应用的可靠性降低。在机车牵引的应用环境下,IGBT的栅极结构参数需要从电学参数和可靠性两个方面进行折中设计。     

功率集成器件及其兼容技术的发展

功率集成器件在交流转直流(AC/DC)电源转换IC、高压栅驱动IC、LED驱动IC等领域均有着广泛的应用。介绍了典型的可集成功率高压器件,包括不同电压等级的横向双扩散金属氧化物半导体场效应晶体管(LDMOS)以及基于硅和SOI材料的横向绝缘栅双极型晶体管(LIGBT),此外还介绍了高低压器件集成的BCD工艺和其他的功率集成关键技术,包括隔离技术、高压互连技术、dV/dt技术、di/dt技术、抗闩锁技术等,最后讨论了功率集成器件及其兼容技术的发展趋势。     

小尺寸栅极HEMT器件结温测量

用现有的红外法测量的GaN基HEMT器件结温,比实际最高温度点的温度低.而用喇曼法测量结温对设备要求高且不易于操作.针对现有技术对GaN基HEMT器件结温的测量存在一定困难的问题,设计了一款HEMT器件匹配电路.利用红外热像仪测量HEMT器件的结温升高,并结合物理数值模拟仿真,提出一种小尺寸栅极结温升高测量方法.结果表明,建立正确的仿真模型,可以得到不同栅极长度范围内的温度.通过这种方法可以测量出更接近实际的结温,为之后研究加载功率与壳温对AlGaN/GaN HEMT器件热阻的影响奠定了理论基础,并且为实际工作中热特性研究提供了参考依据.     

Experimental and numerical study of the emitter turn-off thyristor(ETO)

The emitter turn-off thyristor (ETO) is a new family of high power semiconductor devices that is suitable for megawatt power electronics application. ETOs with voltage and current ratings of 4-6 kV and 1-4 kA, have been developed and demonstrated. And those power levels are the highest in silicon power devices and are comparable to those of the gate turn-off thyristor (GTO). Compared to the conventional GTO, the ETO has much shorter storage time, voltage controlled turn-off capability, and much larger reverse biased safe operation area (RBSOA). Furthermore, ETOs have a forward-biased safe operation area (FBSOA) that enables it to control the turn-on di/dt similar to an insulated gate bipolar transistor (IGBT). These combined advantages make the ETO based power system simpler in terms of dv/dt snubber, di/dt snubber, overcurrent protection, resulting in significant savings in the system cost. This paper presents experimental and numerical results that demonstrate the advantages of the ETO     

p-n-p-n charge dynamics

A simple unified charge model applicable to both unsaturated and saturated p-n-p-n dynamic behavior is analyzed. Expressions are obtained for three important dynamic conditions: di/dt prior to saturation, voltage drop during turn-on, and reverse current during recovery. Comparison with measurement shows that interdigitated gate p-n-p-n devices match one-dimensional turn-on theory and closely approximate the behavior of p-i-n rectifiers under similar pulsed conditiom. The major analytical simplifications of the one-dimensional theory are examined in the Appendixes. The limitations imposed by these simplifications can be avoided by use of numerical integration techniques.     

Active gate voltage control of turn-on di/dt and turn-off dv/dt in insulated gate transistors

As the characteristics of insulated gate transistors [like metal-oxide-semiconductor field-effect transistors and insulated gate bipolar transistors (IGBTs)] have been constantly improving, their utilization in power converters operating at higher and higher frequencies has become more common. However, this, in turn, leads to fast current and voltage transitions that generate large amounts of electromagnetic interferences over wide frequency ranges. In this paper, a new active gate voltage control (AGVC) method is presented. It allows us to control the values of di/dt at turn-on and dv/dt at turn-off for insulated gate power transistors, by acting directly on the input gate voltage shape. In an elementary switching cell, it enables us to strongly reduce over-current generated by the reverse recovery of the free-wheeling diode at turn-on, and oscillations of the output voltage across the transistor at turn-off. In the following sections, the AGVC in open and closed-loop for IGBT is presented, and its performance is compared with that of a more conventional method, i.e., increasing the gate resistance. Robustness of the AGVC is estimated under variations of dc-voltage supply and transistor switched current.     

Assessment of off-state negative gate voltage requirements forIGBTs

This paper addresses the need for off-state negative gate bias with insulated gate bipolar transistor (IGBT) devices that experience a dv/dt when in the off state. Factors considered include off-state gate bias voltage, gate impedance, reapplied dv/dt, and temperature. Theoretical calculation and experimental results for a high-voltage high-current IGBT supports the assessment of these factors     

Switching characteristics of 45-A double-interdigitated GTO thyristors

This work presents the turn-off, turn-on and high-frequency switching characteristics of 45-A 1500-V double-interdigitated GTO switches. The devices possess the highest value of the peak interruptable anode current ever reported in the open literature for 4 × 4 mm area thyristors packed into TO-220 cases. The dynamic evaluation of devices was performed under resistive-inductive load conditions, i.e., close to those encountered in practical circuits employing GTO thyristors. The performed investigations have shown that the novel type of GTOs exhibit the best overall switching characteristics ever presented for this class of GTO switches (identical area and case). The devices performed well under high current and voltage conditions. Even the worst recorded data at higher turn-on and turn-off gains show that the developed GTOs behave as fast commutation devices consuming low input (gate) energy. It was demonstrated that fast turn-off is by no means incompatible with excellent turn-on sensitivity. A remarkable feature of devices consists in a built-in self-protection capability against electrothermal failure during gated turn-off. This unique feature enables the GTOs both to switch large amounts of load current and to safely operate at high commutation frequencies (hundred of kHz) under heavy load conditions.     

The dV/dt capability of double-interdigitated (TIL) thyristors

This work presents an alternative solution, with respect to the conventional cathode-emitter shorts or MOS-controlled emitter shorts, for achieving virtual immunity to the parasitic action of displacement currents in power thyristors. The developed simple design/ technological procedure, based upon the novel double-interdigitated or two interdigitation level (TIL) gate-cathode configuration with a coarse geometry, offers a fair balance between technological simplicity/cost effectiveness and overall device performance. Based upon the developed design guidelines, two sets of gold-doped thyristors with different geometrical configurations and current-voltage handling capabilities were produced. The performed measurements have shown that both sets of TIL thyristors possess an extremely high value of the maximum permissible critical rate of rise of the off-state voltage (dV/ dt capability) even under open-gate conditions. When the gate is connected to the cathode, the TIL thyristors are practically immune to the action of displacement currents. Unlike thyristors using conventional emitter shorts, the TIL-type devices possess a good static and dynamic turn-on/latching sensitivity and have low on-state losses at high-current densities.     

A novel circuit for accurate characterization and modeling of thereverse recovery of high-power high-speed rectifiers

As circuit switching frequency continues to increase, there is a need to produce faster rectifiers with lower power losses. Efficient utilization of high-power ultrafast rectifiers requires precise knowledge of the key static and dynamic switching parameters, especially the reverse-recovery characteristics. Conventional reverse-recovery test circuits were developed to test rectifiers with reverse-recovery times (t_RR) greater than 100 ns, however, new measurement techniques are needed for accurate characterization and modeling of the high-power ultrafast rectifier reverse-recovery process. A test circuit topology is proposed which offers several advantages over existing test circuits. This circuit offers the ability to characterize high-power ultrafast rectifiers at very high di/dt and also provides independent control of bias current, reverse voltage and di/dt. This circuit is also studied using a two-dimensional (2-D) mixed device and circuit simulator in which the device under test is represented as a 2-D finite-element grid and the semiconductor equations are solved under boundary conditions imposed by the proposed test circuit. This simulation tool is used to understand the device physics of the reverse-recovery process and develop more accurate models to be implemented in behavioral circuit simulators. The simulation results are then compared to the measured data for a silicon P-i-N and 200-V GaAs Schottky rectifier under various measurement conditions. Simulation results are shown to be in excellent agreement with the measured data