An accurate semi-empirical saturation drain current model for LDDn-MOSFET

Based on a new empirical mobility model which is solely dependent on V_gs, V_t and T_ox, a corresponding semiempirical I_dsat model for n-MOSFET including velocity saturation, mobility degradation due to increased vertical effective field, and source/drain series resistance of LDD structures is reported in this paper. A good agreement among the model and the measurement data from several different technologies is shown. Prediction of I_dsat for the future generations of device scaling and low-power applications by using this new model is presented     

Runtime Leakage Minimization Through Probability-Aware Optimization

Runtime leakage current, defined as circuit leakage during normal operation (i.e., nonstandby mode), has become a major concern in very advanced technologies along with traditional standby mode leakage. In this paper, we propose a new leakage reduction method that specifically targets runtime leakage current. We first observe that the state probabilities of nodes in a circuit tend to be skewed, meaning that they have either high or low values. We then propose a method that exploits these skewed state probabilities by setting only those transistors to high-V_t (thick-oxide) that have a high likelihood of being off (on) and, hence, contributing significantly to the total runtime leakage. Accordingly, we also propose a library specifically tailored to the proposed approach, where V_t and T_ox assignment with favorable tradeoffs under skewed input probabilities is provided. For further leakage reduction, we also introduce circuit resynthesis using pin reordering, pin rewiring, mapping, and decomposition. The optimization algorithm shows substantial leakage improvement over probability unaware optimization using a traditional standard cell library     

On the SiO2-based gate-dielectric scaling limit forlow-standby power applications in the context of a 0.13 μm CMOS logictechnology

This paper describes a leading-edge 0.13 μm low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I _off) and gate delay (T_d) performance at operating voltages (V_cc) of 1.5 V and 1.2 V, devices with 0.11 μm nominal gate length (L_g-nom) and various gate-oxide thicknesses (T_ox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Å in order to keep acceptable off-state power consumption at V_cc=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T_ox=26 Å) is targeted for V_cc=1.5 V with worst case I_off <10 pA/μm and nominal gate delay 24 ps/gate. Another design, named LP1 (T_ox=22 Å) is targeted for V_cc =1.2 V with worst case I_off<20 pA/μm and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 μA/μm nominal drive currents at V_cc for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm² cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T _ox=22 Å) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125°C and V _cc=1.5 V     

Separation of hot-carrier-induced interface trap creation and oxidecharge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V_gs stress, HEIP is found to dominate the shift of threshold voltage V_t. When V_gs increases to a moderate value, the V_t shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V_gs is increased further to V_gs=V_ds. For the first time, the effects of interface trap creation and oxide charge trapping on the V_t shift are quantified by the proposed technique     

采用红外快速热退火的晶体管TED效应与沟道尺寸的关系研究

硼的瞬间增强扩散（transient enhanced diffusion, TED）导致MOS晶体管出现反短沟道效应,阈值电压异常升高,严重影响器件性能和良品率,不同的器件尺寸,阈值电压增量不同,为探究沟道内杂质离子分布情况和器件尺寸对TED效应的影响,在40 nm CMOS工艺平台下,对调阈值注入、低掺杂漏极（LDD）离子注入和碳离子协同注入工艺进行参数调整实验,测量不同工艺参数、不同尺寸的晶体管阈值电压,采用TCAD工具仿真沟道内硼离子和间隙原子的浓度分布。实验结果表明:沟道长度逐渐缩小,阈值电压先上升,在0.55 μm处达到最高后迅速下降,上升速率随着沟道宽度的减小而降低。当沟道长度不变时,阈值电压随沟道宽度一直下降,且下降得越来越快。间隙硅原子由LDD离子注入引入并向沟道扩散,而硼离子聚集在LDD-沟道边界位置,但是在LDD和沟道形成的角落会向浅沟槽隔离（STI）区域泄漏,聚集和泄漏作用共同控制沟道内硼离子的浓度分布。TED效应导致的阈值电压漂移是受器件尺寸调控的,另外,高能量的碳协同注入结合红外快速热退火技术可以有效地抑制TED效应。     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

Flexibly controllable threshold-voltage (V_th) asymmetric gate-oxide thickness (T_ox) four-terminal (4T) FinFETs with HfO₂ [equivalentoxidethickness(EOT)=1.4 nm] for the drive gate and HfO₂+thick SiO₂ (EOT=6.4-9.4 nm) for the V_th-control gate have been successfully fabricated by utilizing ion-bombardment-enhanced etching process. Owing to the slightly thick V_th-control gate oxide, the subthreshold slope (S) is significantly improved as compared to the symmetrically thin T_ox 4T-FinFETs. As a result, the asymmetric T_ox 4T-FinFETs gain higher I_on than that for the symmetrically thin T_ox 4T-FinFETs under the same I_off conditions     

Threshold voltage roll-up/roll-off characteristic control insub-0.2-μm single workfunction gate CMOS for high-performance DRAMapplications

Threshold voltage (V_t) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-μm single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N₂ implant prior to gate oxidation is important to reduce V_t roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V_t roll-off characteristics. Finally, the impact of halo implant on V_t variation in sub-0.2-μm buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V_t variation in sub-0.2-μm single workfunction gate pFET     

Cost-Effective Low Vt Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and Yb+P Coimplant (nMOS)

Low V_t Ni fully silicided (FUSI) devices are demonstrated making use of Al implantation for pMOS and Yb or Yb+P implantation for nMOS combined with Ni-silicide phase engineering. When Yb(+P) and Al implantation are followed by a high temperature anneal, significant segregation of Yb or Al toward the Ni-FUSI/SiON interface is observed and large Vt shifts of 450 mV (330 mV) and 200 mV are obtained for nMOS NiSi FUSI/SiON devices and pMOS Ni-rich FUSI/SiON devices, respectively, as compared to the undoped reference devices. The Vt shifts are preserved down to the shortest gate lengths. For both Al and Yb, the V_t shifts are explained by the dopants reacting with and modifying the dielectric. Thus, the low V_t dual implantation approach proposed achieves a low-cost "dual dielectric" implementation without the need of dual deposition of dielectrics or capping layers. In the case of Yb implantation followed by a high temperature anneal, a significant reduction in the inversion dielectric thickness is observed, indicating that the reaction between Yb and SiON results in the formation of a high-k dielectric. The Yb diffusion and reaction at the interface can be engineered using a P coimplant.     

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V_t) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V_t is high at V_gs=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V_dd=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS)     

A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V     

Enhancement of PMOS device performance with poly-SiGe gate

Poly-Si and poly-Si_0.75Ge_0.25-gated PMOS transistors with a very thin gate oxide of 29 Å were fabricated. In addition to reduced gate-depletion effect (GDE) and reduced boron penetration, more favorable I_d-V_d characteristics were observed for the poly-SiGe-gated transistors than poly-Si-gated transistors. This and the underlying superior hole mobility are explained with a universal mobility model based on V_g, T_ox, V_th and V_th. Both reduced GDE and superior hole mobility contribute to the enhanced performance     

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:Ni2Si, and Ni31Si12) on HfSiON

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni₃₁Si₁₂ FUSI gates on p-channel MOS (PMOS) with good V_t control to short gate lengths (L_G=50 nm, linear V_t of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni₂Si or Ni₃₁ Si₁₂ on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni₂Si or Ni₃₁Si₁₂ FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% I_on improvement at I_off=100 nA/mum) was obtained for Ni ₃₁Si₁₂ compared to Ni₂Si FUSI gates, as well as a V_t reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS     

Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

DC and high-frequency device characteristics of In_0.7Ga_0.3As and InSb quantum-well field-effect transistors (QWFETs) are measured and benchmarked against state-of- the-art strained silicon (Si) nMOSFET devices, all measured on the same test bench. Saturation current (I_on) gam of 20% is observed in the In_0.7Ga_0.3As QWFET over the strained Si nMOSFET at (V_g - V_t) = 0.3 V, V_ds = 0.5 V, and matched I_off, despite higher external resistance and large gate-to-channel thickness. To understand the gain in I_on, the effective carrier velocities (v_eff) near the source-end are extracted and it is observed that at constant (V_g - V_t) = 0.3 V and V_ds = 0.5 V, the v_eff of In_0.7Ga_0.3As and InSb QWFETs are 4-5times higher than that of strained silicon (Si) nMOSFETs due to the lower effective carrier mass in the QWFETs. The product of v_eff and charge density (n_s), which is a measure of "intrinsic" device characteristics, for the QWFETs is 50%-70% higher than strained Si at low-voltage operation despite lower ns in QWFETs. Calibrated simulations of In_0.7Ga_0.3As QWFETs with reduced gate-to-channel thickness and external resistance matched to the strained Si nMOSFET suggest that the higher v_eff will result in more than 80% I_on increase over strained Si nMOSFETs at V_ds = 0.5 V, (V_g - V_t) = 0.3 V, and matched I_off, thus showing promise for future high-speed and low-power logic applications.     

Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies

Dual-V_t design technique has proven to be extremely effective in reducing subthreshold leakage in both active and standby mode of operation of a circuit in submicrometer technologies. However, aggressive scaling of technology results in different leakage components (subthreshold, gate and junction tunneling) to become significant portion of total power dissipation in CMOS circuits. High-V_t devices are expected to have high junction tunneling current (due to stronger halo doping) compared to low-V_t devices, which in the worst case can increase the total leakage in dual-V_t design. Moreover, process parameter variations (and in turn V_t variations) are expected to be significantly high in sub-50-nm technology regime, which can severely affect the yield. In this paper, we propose a device aware simultaneous sizing and dual-V_t design methodology that considers each component of leakage and the impact of process variation (on both delay and leakage power) to minimize the total leakage while ensuring a target yield. Our results show that conventional dual-V_t design can overestimate leakage savings by 36% while incurring 17% average yield loss in 50-nm predictive technology. The proposed scheme results in 10%-20% extra leakage power savings compared to conventional dual-V_t design, while ensuring target yield. This paper also shows that nonscalability of the present way of realizing high-V_t devices results in negligible power savings beyond 25-nm technology. Hence, different dual-V_t process options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual-V_t designs in future technologies.     

Long-term bias temperature reliability of P+ polysilicongated FET devices

An instability was found to be associated with +BT stress for P ⁺ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N⁺ poly-gated devices (NNMOS and NPMOS). The instability with the P⁺ poly-gated devices, which is a decrease in threshold voltage (V_t) and an increase in interface state density (D_it), was significantly reduced following N₂ annealing at 400°C. It is shown that adequate reliability for P⁺ poly-gated devices can be achieved for VLSI technologies     

Duet: an accurate leakage estimation and optimization tool fordual-Vt circuits

Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, the method achieves speedups of three to four orders of magnitude over exhaustive SPICE simulations while maintaining very good accuracy. The leakage current calculation is then utilized in a new leakage and performance optimization algorithm for circuits using dual V_t processes. The approach is the first to consider the assignment of both the V_t and the width of a transistor, simultaneously. The optimization approach uses incremental calculation of leakage and performance sensitivities and can take into account a partially defined circuit state constraint for the standby mode of the device     

Recovery of the NBTI-Stressed Ultrathin Gate p-MOSFET: The Role of Deep-Level Hole Traps

Under a static negative-bias temperature stress, the negative threshold-voltage V_t shift (extracted from the dc current-voltage characteristic) of the direct-tunneling gate p-MOSFET is found to be substantially larger than that calculated based on the interface-state density measured using the charge-pumping method. Device-recovery characteristics from bipolar gate stress show that interface states alone cannot entirely account for the V_t shift, and indicate that a substantial number of positive oxide charges are also generated during stress. Stability of the increased V_t shift under a negative dc gate biasing and unipolar ac gate pulsing implies that these positive charges are deep-level hole traps with energy states above the Si conduction band edge. Because the defect states are outside the energy window of direct electron tunneling, their long relaxation time plays an important role in the slow recovery transient of the p-MOSFET     

Impact of electron and hole inversion-layer capacitance on lowvoltage operation of scaled n- and p-MOSFET's

The influence of inversion-layer capacitance (C_inv) on supply voltage (V_dd) of n- and p-MOSFET's is quantitatively examined. The physical origin of the effect of C_inv on V_dd consists in the band bending of a Si substrate in the inversion condition due to C_inv, which is not scaled with a reduction in gate oxide thickness. The amount and the impact of the band bending is accurately evaluated on a basis of one dimensional (1-D) self-consistent calculations including two-dimensional (2-D) subband structure of inversion-layer electrons and holes. It is demonstrated that additional band bending of a Si substrate due to C_inv becomes a dominant factor to limit the lowering of V_dd for CMOS with ultrathin gate oxides. The operation at V_dd lower than 0.6 V is quite difficult even with effective T_ox less than 1 nm     

High-Work-Function Ir/HfLaO ${rm p}$-MOSFETs Using Low-Temperature-Processed Shallow Junction

We report a high effective work function (Phi_m-eff) and a very low Vt Ir gate on HfLaO p-MOSFETs using novel self-aligned low-temperature shallow junctions. This gate-first process has shallow junctions of 9.6 or 20 nm that are formed by solid phase diffusion using SiO₂-covered Ga or Ni/Ga. At 1.2-nm effective oxide thickness, good Phi_m-eff of 5.3 eV, low V_t of +0.05 V, high mobility of 90 cm²/V-s at -0.3 MV/cm, and small 85degC negative bias-temperature instability (NBTI) of 20 mV (10 MV/cm for 1 h) are measured for Ir/HfLaO p-MOSFETs.