Instability dependent upon bias and temperature stress in amorphous‐indium gallium zinc oxide (a‐IGZO) thin‐film transistors

Abstract— The effects of gate‐bias stress, drain‐bias stress, and temperature on the electrical parameters of amorphous‐indium gallium zinc oxide (a‐IGZO) thin‐film transistors have been investigated. Results demonstrate that the devices suffer from threshold‐voltage instabilities that are recovered at room temperature without any treatments. It is suggested that these instabilities result from the bias field and temperature‐assisted charging and discharging phenomenon of preexisting traps at the near‐interface and the a‐IGZO channel region. The experimental results show that applying a drain‐bias stress obviously impacts the instability of a‐IGZO TFTs; however, the instability caused by drain bias is not caused by hot‐electron generation as in conventional MOSFETs. And the degradation trend is affected by thermally activated carriers at high temperature.     

Modeling of threshold‐voltage‐shift dependency on drain bias in amorphous‐silicon thin‐film transistors in active‐matrix organic light‐emitting‐diode displays

Abstract— A theoretical model to interpret appearances of the threshold voltage shift in hydrogenated amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) is developed to better understand the instability of a‐Si:H TFTs for the driving transistors in active‐matrix organic light‐emitting‐diode (AMOLED) displays. This model assumes that the defect creation at channel in a‐Si:H is proportional to the carrier concentration, leading to the defect density varying along the channel depending on the bias conditions. The model interprets a threshold‐voltage‐shift dependency on the drain‐stress bias. The model predicts the threshold voltage shift stressed under a given gate bias applying the drain saturation voltage is 66% of that with zero drain bias, and it even goes down to 50–60% of that when stressed by applying twice the drain saturation voltage.     

Letter: Mechanisms for on/off currents in dual‐gate a‐Si:H thin‐film transistors using indium‐tin‐oxide top‐gate electrodes

Abstract— Two types of dual‐gate a‐Si:H TFTs were made with transparent indium‐tin‐oxide (ITO) top‐gate electrodes of different lengths to investigate the static characteristics of these devices. By changing the length of the ITO top gate, we found that the variations in the on‐currents of these dual‐gate TFTs with dual‐gate driving are due to the high resistance of the parasitic intrinsic a‐Si:H regions between the back electron channel and the source/drain contact. In the off‐state of the dual‐gate‐driven TFTs, the Poole‐Frenkel effect is also enhanced due to back‐channel hole accumulation in the vicinity of the source/drain contact. Furthermore, we observed for the first time that under illumination the dual‐gate‐driven a‐Si:H TFTs exhibit extremely low photo‐leakage currents, much lower than that of single‐gate‐driven TFTs in a certain range (reverse subthreshold region) of negative gate voltages. The high on/off current ratio under backside illumination makes dual‐gate TFTs suitable devices for use as switching elements in liquid‐crystal displays (LCDs) or for other applications.     

Effects of post‐annealing on a‐Si:H TFT characteristics fabricated on stainless‐steel substrate

Abstract— A 14.1‐in.‐diagonal backplane employing hydrogenated amorphous‐silicon thin‐film transistors (a‐Si:H TFTs) was fabricated on a flexible stainless‐steel substrate. The TFTs exhibited a field‐effect mobility of 0.54 cm²/V‐sec, a threshold voltage of 1.0 V, and an off‐current of 10^?13 A. Most of the electrical characteristics were comparable to those of the TFTs fabricated on glass substrates. To increase the stability of a‐Si:H TFTs fabricated on stainless‐steel substrate, the specimens were thermally annealed at 230°C. The field‐effect mobility was reduced to 71% of the initial value because of the strain of the released hydrogen atoms and residual compressive stress in a‐Si:H TFT under thermal annealing at 230°C.     

a‐InGaZnO thin‐film transistors for AMOLEDs: Electrical stability and pixel‐circuit simulation

Abstract— Inverted‐staggered amorphous In‐Ga‐Zn‐O (a‐InGaZnO) thin‐film transistors (TFTs) were fabricated and characterized on glass substrates. The a‐InGaZnO TFTs exhibit adequate field‐effect mobilities, sharp subthreshold slopes, and very low off‐currents. The current temperature stress (CTS) on the a‐InGaZnO TFTs was performed, and the effect of stress temperature (TSTR), stress current (ISTR), and TFT biasing condition on their electrical stability was investigated. Finally, SPICE modelling for a‐InGaZnO TFTs was developed based on experimental data. Several active‐matrix organic light‐emitting‐display (AMOLED) pixel circuits were simulated, and the potential advantages of using a‐InGaZnO TFTs were discussed.     

Impact of source/drain contacts formation of self‐aligned amorphous‐IGZO TFTs on their negative‐bias‐illumination‐stress stabilities

In this study, we have compared the performance of self‐aligned a‐IGZO thin‐film transistors (TFTs) whereby the source/drain (S/D) region's conductivity enhanced in three different ways, that is, using SiN_x interlayer plasma (hydrogen diffusion), using calcium (Ca as reducing metal) and using argon plasma (changing the atomic ratio). All these TFTs show comparable characteristics such as field‐effect mobility (μ_FE) of over 10.0 cm²/(V.s), sub‐threshold slope (SS^‐1) of 0.5 V/decade, and current ratio (I_ON/I_OFF) over 10⁸. However, under negative‐bias‐illumination‐stress (NBIS), all these TFTs showed strong degradation. We attributed this NBIS stability issue to the exposed S/D regions and changes in the conductivity of S/D contact regions. The hydrogen plasma‐treated TFTs showed the worst NBIS characteristics. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel.     

Highly reliable oxide‐semiconductor TFT for AMOLED displays

Abstract— The stability and reliability of oxide‐semiconductor TFTs were investigated. The contact material to the oxide semiconductor affected the thermal stability of the TFT, and a molybdenum‐contact source/drain showed good stability. And the passivating film and TFT structure affected the stability against bias stress and humidity stress, and dc‐sputtered Al²O³ passivation and fully covered channel structure with an etching stopper or source/drain showed good reliability. Moreover, high photo‐stability was confirmed by the bias‐enhanced photo‐irradiation stress test. An 11.7‐in.‐diagonal qHD AMOLED display was demonstrated to provide an applicable solution for a large‐sized OLED and an ultra‐high‐definition LCD‐TV mass production.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

Novel back‐channel‐etch process flow based a‐IGZO TFTs for circuit and display applications on PEN foil

In this study, we report high‐quality amorphous indium–gallium–zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) fabricated on a polyethylene naphthalate foil using a new back‐channel‐etch (BCE) process flow. The BCE flow allows a better scalability of TFTs for high‐resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165 °C in order to ensure good overlay accuracy (<1 µm) on foil. The presented process flow differs from the previously reported flow as we define the Mo source and drain contacts by dry etch prior to a‐IGZO patterning. The TFTs show good electrical performance, including field‐effect mobilities in the range of 15.0 cm²/(V·s), subthreshold slopes of 0.3 V/decade, and off‐currents <1.0 pA on foil. The threshold voltage shifts of the TFTs measured were less than 1.0 V after a stressing time of 10⁴ s in both positive (+1.0 MV/cm) and negative (?1.0 MV/cm) bias directions. The applicability of this new BCE process flow is demonstrated in a 19‐stage ring oscillator, demonstrated to operate at a supply voltage of 10 V with a stage delay time of 1.35 µs, and in a TFT backplane driving a 32 × 32 active‐matrix organic light‐emitting diode display.     

Effect of source/drain overlap region on device performance in a‐IGZO thin‐film transistors

Abstract— In this paper, the effect of source/drain overlap length on the amorphous indium gallium zinc oxide (a‐IGZO) TFT performance has been investigated. Results of this paper show that as source/drain overlap length decreases to a negative value forming S/D offset, the threshold voltage and S parameters of a‐IGZO TFTs increased and the field‐effect mobility decreased. The V_T variation increases sharply as the channel length decreases because of the large resistance R_offset when it is formed at a‐IGZO source/drain. In the experiment, R_offset of each 1 μm, evaluated from the transfer length method (TLM), shows approximately 54–66 kΩ. This means thatthe source/drain overlap length is a very important control parameter for uniform device characteristics of a‐IGZO TFTs.     

Flexible AMOLEDs with low‐temperature‐processed TFT backplane technologies

Developments of backplane technologies, which are one of the challenging topics, toward the realization of flexible active matrix organic light‐emitting diodes (AMOLEDs) are discussed in this paper. Plastic substrates including polyimide are considered as a good candidate for substrates of flexible AMOLEDs. The fabrication process flows based on plastic substrates are explained. Limited by the temperature that plastic substrates can sustain, TFT technologies with maximum processing temperature below 400 °C must be developed. Considering the stringent requirements of AMOLEDs, both oxide thin‐film transistors (TFTs) and ultra‐low‐temperature poly‐silicon TFTs (U‐LTPS TFTs) are investigated. First, oxide TFTs with representative indium gallium zinc oxide channel layer are fabricated on polyimide substrates. The threshold voltage shifts under bias stress and under bending test are small. Thus, a 4.0‐in. flexible AMOLED is demonstrated with indium gallium zinc oxide TFTs, showing good panel performance and flexibility. Further, the oxide TFTs based on indium tin zinc oxide channel layer with high mobility and good stability are discussed. The mobility can be higher than 20 cm²/Vs, and threshold voltage shifts under both voltage stress and current stress are almost negligible, proving the potential of oxide TFT technology. On the other hand, the U‐LTPS TFTs are also developed. It is confirmed that dehydrogenation and dopant activation can be effectively performed at a temperature within 400 °C. The performance of U‐LTPS TFTs on polyimide is compatible to those of TFTs on glass. Also, the performance of devices on polyimide can be kept intact after devices de‐bonded from glass carrier. Finally, a 4.3‐in. flexible AMOLED is also demonstrated with U‐LTPS TFTs.     

Comparative study of a‐IGZO TFTs with direct current and radio frequency sputtered channel layers

In this work, a comparative study of electrical properties and gate‐bias stress stability between direct current (DC)‐sputtered and radio frequency (RF)‐sputtered amorphous indium–gallium–zinc oxide thin film transistors (a‐IGZO TFTs) is conducted. The RF‐sputtered a‐IGZO TFTs show higher field‐effect mobility and steeper sub‐threshold slope. The DC‐sputtered ones show a better uniformity of threshold voltage, enhanced stability under both positive bias stress and negative bias illumination stress. The X‐ray photoelectron spectroscopy characterization of the a‐IGZO films reveals that the concentration of oxygen vacancies and electron density in the RF‐sputtered a‐IGZO film is higher than that in the DC‐sputtered one, which probably accounts for the differences of electrical properties between the RF‐sputtered and DC‐sputtered a‐IGZO TFTs.     

Novel self‐aligned top‐gate oxide TFT for AMOLED displays

Abstract— A novel highly reliable self‐aligned top‐gate oxide‐semiconductor thin‐film transistor (TFT) formed by using the aluminum (Al) reaction method has been developed. This TFT structure has advantages such as small‐sized TFTs, lower mask count, and small parasitic capacitance. The TFT with a 4‐μm channel length exhibited a field‐effect mobility of 21.6 cm²/V‐sec, a threshold voltage of ?1.2 V, and a subthreshold swing of 0.12 V/decade. Highly reliable TFTs were obtained after 300°C annealing without increasing the sheet resistivity of the source/drain region. A 9.9‐in.‐diagonal qHD AMOLED display was demonstrated with self‐aligned top‐gate oxide‐semiconductor TFTs for a low‐cost and ultra‐high‐definition OLED display. Excellent brightness uniformity could be achieved due to small parasitic capacitance.     

Development of 8‐in. oxide‐TFT‐driven flexible AMOLED display using high‐performance red phosphorescent OLED

An 8‐in. flexible active‐matrix organic light‐emitting diode (AMOLED) display driven by oxide thin‐film transistors (TFTs) has been developed. In‐Ga‐Zn‐O (IGZO)‐TFTs used as driving devices were fabricated directly on a plastic film at a low temperature below 200 °C. To form a SiO_x layer for use as the gate insulator of the TFTs, direct current pulse sputtering was used for the deposition at a low temperature. The fabricated TFT shows a good transfer characteristic and enough carrier mobility to drive OLED displays with Video Graphic Array pixels. A solution‐processable photo‐sensitive polymer was also used as a passivation layer of the TFTs. Furthermore, a high‐performance phosphorescent OLED was developed as a red‐light‐emitting device. Both lower power consumption and longer lifetime were achieved in the OLED, which used an efficient energy transfer from the host material to the guest material in the emission layer. By assembling these technologies, a flexible AMOLED display was fabricated on the plastic film. We obtained a clear and uniform moving color image on the display.     

Interface and bulk effects for bias—light‐illumination instability in amorphous‐In—Ga—Zn—O thin‐film transistors

Abstract— Positive‐current‐bias (PB) instability and negative‐bias—light‐illumination (NBL) instability in amorphous‐In—Ga—Zn—O (a‐IGZO) thin‐film transistors (TFTs) have been examined. The channel‐ thickness dependence indicated that the Vth instability caused by the PB stress is primarily attributed to defects in the bulk a‐IGZO region for unannealed TFTs and to those in the channel—gate‐insulator interface for wet‐annealed TFTs. The interface and bulk defect densities (Dit and Nss, respectively) are Dit = 4.8 × 10¹¹ cm^?2/eV and Nss = 7.0×10¹⁶ cm^?3/eV for the unannealed TFT, which increased to 5.2×10¹¹ cm^?2/eV and 9.8×10¹⁶ cm^?3/eV, respectively, by the PB stress test. These are reduced significantly to Dit = 0.82×10¹¹ cm^?2/eV and Nss = 3.2×10¹⁶ cm^?3/eV for the wet‐annealed TFTs and are unchanged by the PB stress test. It was also found that the photo‐response of a‐IGZO TFTs begins at 2.3 eV of photon excitation, which corresponds to subgap states observed by photoemission spectroscopy. The origin of the NBL instability for the wet‐annealed TFTs is attributed to interface effects and considered to be a trap of holes at the channel‐gate—insulator interface where migration of the holes is enhanced by the electric field formed by the negative gate bias.     

Flexible amorphous‐silicon non‐volatile memory

Abstract— The development of a flexible, rewritable, non‐volatile memory (NVM) that is implemented on a standard, low‐temperature a‐Si:H process without additional mask steps is reported. This NVM is a part of a flexible‐display system. Each NVM cell is composed of differentially configured thin‐film‐transistors (TFTs). The cell reads out one of two stable states depending on the relative threshold voltages of the differentially configured TFTs. Information is stored in each cell by increasing the threshold voltage of one differential TFT or the other, utilizing the well‐known electrical‐stress degradation intrinsic to a‐Si:H TFTs. The stored information is retained indefinitely with no applied power. A test array of individually addressable NVM cells has been successfully fabricated and tested on flexible stainless‐steel substrates. Read and write operation, as well as preliminary reliability measurements, are described. The design is readily scalable to large memory arrays.     

Amorphous‐silicon gate‐driver circuits of shared‐node dual pull‐down structure with overlapped output signals

Abstract— A novel gate‐driver circuit using amorphous‐silicon (a‐Si) TFTs has been developed. The circuit has a shared‐node dual pull‐down AC (SDAC) structure with a common‐node controller for two neighboring stages, resulting in a reduced number of TFTs. The overlapped clock signals widen the temperature range for stable operation due to the extended charging time of the inner nodes of the circuit. The accelerated lifetime was found to be over 1000 hours at 60°C with good bias‐temperature‐stress (BTS) characteristics. Accordingly, the a‐Si gate‐driver circuit was successfully integrated into a 14.1‐in. XGA (1024 × RGB × 768) TFT‐LCD panel having a single bank form.     

Single‐source dual‐layer amorphous IGZO thin‐film transistors for display and circuit applications

In this study, the authors report on high‐quality amorphous indium–gallium–zinc oxide thin‐film transistors (TFTs) based on a single‐source dual‐layer concept processed at temperatures down to 150°C. The dual‐layer concept allows the precise control of local charge carrier densities by varying the O₂/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual‐layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual‐layer TFTs are more stable under bias conditions in comparison with single‐layer TFTs processed at low temperatures. Finally, the applicability of this dual‐layer concept in logic circuitry such as 19‐stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active‐matrix organic light‐emitting diode display demonstrator is proven.     

PECVD‐based nanocrystalline‐silicon TFT backplanes for large‐sized AMOLED displays

Abstract— A 14.1‐in. AMOLED display using nanocrystalline silicon (nc‐Si) TFTs has been developed. Nanocrystalline silicon was deposited using conventional 13.56‐MHz plasma‐enhanced chemical vapor deposition (PECVD). Detailed thin‐film characterization of nc‐Si films was followed by development of nc‐Si TFTs, which demonstrate a field‐effect mobility of about 0.6–1.0 cm²/V‐sec. The nc‐Si TFTs show no significant shift in threshold voltage when over 700 hours of constant current stress is applied, indicating a stable TFT backplane. The nc‐Si TFTs were successfully integrated into a 14.1‐in. AMOLED display. The display shows no significant current decrease in the driving TFT of the 2T‐1cap circuit because the TFTs are highly stable. In addition to the improved lifetime of AMOLED displays, the development of nc‐Si TFTs using a conventional 13.56‐MHz PECVD system offers considerable cost advantages over other laser and non‐laser polysilicon‐TFT technologies for large‐sized AMOLEDs.     

Temperature instability of low‐temperature deposited a‐Si:H TFTs fabricated on plastic substrate

Abstract— Low‐temperature deposited a‐Si:H TFTs have been successfully fabricated on colorless polyimide (CPI) substrate for flexible‐display applications. A serious degradation in threshold voltage was observed after applying external thermal stress. The threshold‐voltage shift saturates after applying several thermal stress cycles. In addition, the TFTs show instability under long periods of thermal stress with fixed temperature. This phenomenon was composed of thermally induced traps and substrate‐expansion‐induced mechanical stress. Finally, the a‐Si:H TFT backplane fabricated on a PI substrate at low temperature has been successfully demonstrated for flexible AMLCDs.