Harmonic oscillators realized using current amplifiers and grounded capacitors

New configurations of harmonic oscillators, realized using current amplifier blocks and only grounded capacitors, are introduced in this article. The proposed configurations are based on a grounded inductor simulator scheme and on a loop constructed from first‐order sections, respectively. Comparison with the already published topologies shows that the new configurations have attractive characteristics concerning their implementation in integrated form. Copyright © 2006 John Wiley & Sons, Ltd.     

Electronically controlled multiphase sinusoidal oscillators using current amplifiers

A novel current‐mode multiphase oscillator topology is introduced in this letter. This is realized by employing current amplifiers and only grounded capacitors. Attractive characteristics offered by the new topology are the electronic adjustment of the oscillation frequency, the absence of passive resistors, and the requirement of only grounded capacitors. Comparison with the corresponding already published current follower based structure shows that the proposed topology has better performance in terms of the number of required active elements, the employment of passive resistors, and the ability for electronic adjustment of the oscillation frequency. Copyright © 2008 John Wiley & Sons, Ltd.     

Analytical comparison of frequency compensation techniques in three‐stage amplifiers

In this paper, design equations of the most common Nested Miller topologies are derived. Moreover, a coherent and comprehensive analytical comparison among the different topologies is also presented. In particular, after deriving design equations, following the approach previously proposed by the authors that have the phase margin as the main design parameter, the different solutions are compared by evaluating a novel figure of merit that expresses a trade‐off between gain‐bandwidth product, load capacitance and total transconductance, for equal values of phase margin. It is shown that there is no unique optimal solution as this depends on the load condition and the relative magnitude of the transconductance of each stage. From this point of view, the proposed comparison also provides useful design guidelines for the optimization of small‐signal performance. Simulations confirming the effectiveness of the comparison are also given. Copyright © 2006 John Wiley & Sons, Ltd.     

Current‐mode wave field programmable analogue arrays

A new configurable analogue block (CAB), the key element in the design of field programmable analogue arrays (FPAAs), is introduced in this paper. This CAB is based on wave equivalents of the passive elements and it is easily reconfigurable resulting in very simple and versatile FPAA structures. The proposed topology employs a minimum number of switches in the signal path due to the absence of the interconnection network required in other FPAA structures, and thus an improved performance is achieved in comparison with the already introduced corresponding programmable configurations. Copyright © 2008 John Wiley & Sons, Ltd.     

Using MOS current dividers for linearization of programmable gain amplifiers

Two highly linear, digitally programmable gain amplifiers are presented and compared in terms of linearity, frequency, area and power consumption. High linearity and wide gain tuning range with moderate area consumption are the main benefits of both configurations. Furthermore, constant bandwidth is achieved by means of switched compensation capacitor arrays. Three‐bit prototypes were integrated in a 0.35 µm–3.3 V CMOS process with 2.5 V supply voltage. Experimental distortion levels are better than ?68 dB for 1 MHz and 1 V_p?p output signals in both configurations; hence, the suitability of the linearization technique based on MOS current dividers is shown. Copyright © 2007 John Wiley & Sons, Ltd.     

Three‐stage nested‐Miller‐compensated operational amplifiers: Analysis,design, and optimization based on settling time

In analog signal‐processing applications, settling performance of the employed operational amplifiers (opamps) is usually of great matter. Under low‐voltage environment of modern technologies where only a few transistors are allowed to be stacked, three‐stage amplifiers are gaining more interest. Unfortunately, design and optimization of three‐stage opamps based on settling time still suffer from lack of a comprehensive analysis of the settling behavior and closed‐form relations between settling time/error and other parameters. In this paper, a thorough analysis of the settling response of three‐stage nested‐Miller‐compensated opamps, including linear and non‐linear sections, is presented. This analysis leads to a design methodology which determines the circuit requirements for desired settling time/error. Based on settling time, it allows optimizations in power consumption and area. Copyright © 2010 John Wiley & Sons, Ltd.     

Modified CFOA,its transpose,and applications

It is shown that the recently‐proposed modified current feedback operational amplifier (MCFOA) is quite a versatile element in that given a realization for a system function using MCFOAs, we can obtain three alternate realizations using the same MCFOA but by appropriately connecting the y, x, w, and z terminals of the MCFOA to the remaining part of the original realization. Using the results concerning the transpose of a multi‐terminal element, it is further shown that the transpose of an MCFOA is another MCFOA. Thus, using the results of transposition, given a voltage‐mode circuit using MCFOAs, we can directly obtain four current‐mode circuits using the same MCFOAs or vice versa. Copyright © 2015 John Wiley & Sons, Ltd.     

Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers

We present an adaptive frequency compensation technique providing maximum bandwidth closed‐loop amplifiers. The approach exploits an auxiliary variable gain amplifier to implement an electrically tunable compensation capacitor proportional to the feedback factor. In this manner, the closed‐loop bandwidth is kept ideally constant irrespective of the closed‐loop gain. The proposed method can be applied to any amplifier adopting dominant‐pole compensation. As an example, we designed a CMOS amplifier providing 66‐dB direct current gain and 310‐MHz gain‐bandwidth product. For closed‐loop gains ranging from 1 to 10, the closed‐loop bandwidth was found never lower than 401 MHz (noinverting configuration) and 229 MHz (inverting configuration). A similar amplifier with equal gain‐bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed‐loop bandwidth reduced to 33 MHz (noninverting) and 30 MHz (inverting) when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, whereas the other main operational amplifier performance parameters remain almost unchanged compared with the standard solution. Copyright © 2011 John Wiley & Sons, Ltd.     

A practical near constant bandwidth amplifier

This paper presents a simple near constant bandwidth amplifier constructed from two operational amplifiers. The near constant bandwidth is obtained by reducing the normally high input impedance of the opamp via local and overall feedback. Experimental results obtained using identical opamps and different opamps verify the expected theoretical results. Copyright © 2009 John Wiley & Sons, Ltd.     

An algorithm for multiple fault diagnosis in analogue circuits

The paper deals with multiple fault diagnosis of analogue AC or DC circuits with limited accessible terminals for excitation and measurement and brings an algorithm for identificating faulty elements and evaluating their parameters. The main achievement is a method enabling us to efficiently identify faulty elements. For this purpose some testing equations are derived playing a key role in identification of possibly faulty elements which are next verified using a test of acceptance. The proposed approach is described in detail for double fault diagnosis. Also extension to triple fault diagnosis is given. Although the method pertains to linear circuits, some aspects of multiple fault diagnosis of non‐linear circuits can be also performed using the small signal approach. Two numerical examples illustrate the proposed method and show its efficiency. Copyright © 2006 John Wiley & Sons, Ltd.     

Class AB amplifier with enhanced slew rate and GBW

The design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power-efficient adaptive biasing circuit and a class AB current follower using the quasi-floating gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5-μm CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small-signal performance.     

Current‐mode filters based on current mirror arrays

A technique is proposed for obtaining current‐mode filters based on current mirror arrays that operate as unity gain current amplifiers. These amplifiers by properly driving capacitors realize active lossless integrators which are the basic active elements for the derivation of filters according to the leapfrog method. Due to the fact that both the structure of the amplifiers and the adapted method for filter design are simple, the proposed technique is attractive for filter design and implementation. A design and the implementation of two third‐order low‐pass filters are presented. The array of the amplifiers has been implemented in a 0.8 µm CMOS technology. Copyright © 2007 John Wiley & Sons, Ltd.     

Design of current‐mode MOSFET‐C filters using OTRAs

In this paper, third‐order current‐mode MOSFET‐C filters that use operational transresistance amplifiers (OTRAs) with little parasitic capacitance effects are presented. On the basis of the proposed systematic method and design procedure, we can efficiently synthesize third‐order active filters with OTRAs along with simplified MOSFET resistor circuits, and all virtually grounded capacitors. Third‐order current‐mode Chebychev low‐pass and high‐pass filters are realized to verify the validity of the theoretical analysis. Experimental results employing commercially available current feedback amplifiers are also given. Copyright © 2008 John Wiley & Sons, Ltd.     

A novel circuit element and its application in signal amplification

A novel IC‐based current amplifier configuration for signal‐processing applications that can be configured using commercially available integrated circuit elements is presented. The circuit is accurate, has a wide bandwidth and can drive grounded loads. It utilizes a CCII+ type current conveyor with its input circuit in the feedback loop of a current feedback amplifier (CFA). In the current amplifying mode, the circuit has a low input impedance over a broad frequency range which never rises above the low input impedance of the inverting input of the associated CFA. Experimental results obtained using AD844s confirm the results derived. Copyright © 2007 John Wiley & Sons, Ltd.     

A new efficient SC integrator scheme for high‐speed low‐power applications

A new solution to implement efficient switched‐capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35?µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.     

A method for fast simulation of multiple catastrophic faults in analogue circuits

The paper offers an efficient method for simulation of multiple catastrophic faults in linear AC circuits. The faulty elements are either open circuits or short circuits. The method exploits the well‐known Householder formula in matrix theory to find the node voltages deviations due to the perturbations of some circuit elements. The main achievement of the paper is a systematic method for performing the simulation of all combinations of the multiple catastrophic faults. The method includes two new procedures enabling us to find very efficiently the node impedance matrix of the nominal circuit and inverses of some matrices corresponding to different fault combinations. The procedures are the crucial point of this approach and make it very efficient. Consequently, the amount of the computing power needed to carry out all the simulations is significantly reduced. Numerical examples illustrating the proposed approach are provided. Copyright © 2008 John Wiley & Sons, Ltd.     

Design approach for high‐bandwidth low‐power three‐stage operational amplifiers

A new design approach to optimize the frequency compensation network of three‐stage operational amplifiers (op‐amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well‐established three‐stage op‐amps using Nested‐Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35‐µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op‐amps. It is also demonstrated that NMCFNR op‐amps, designed according to the proposed method, even guarantee larger values of the gain‐bandwidth product than three‐stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping‐factor control frequency compensation. Copyright © 2010 John Wiley & Sons, Ltd.     

Design criterion for high‐speed low‐power SC circuits

The settling behavior of switched‐capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two‐stage Miller‐compensated operational amplifiers (op‐amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op‐amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35‐ µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd.     

A generalized fault diagnosis method in dynamic analogue circuits

Fault diagnosis of analogue circuits is essential for analogue and mixed‐signal systems testing and maintenance. A new method is proposed in this paper for multiple fault diagnosis of linear analogue circuits in frequency domain. The Woodbury formula is applied to the modified nodal equation to construct the fault diagnosis equation, which relates the limited measured circuit responses with the multiple faults inside the circuit in a linear way. A recently developed ambiguity group locating technique is modified here to identify the faulty parameters directly. Computation cost is reduced compared to combinatorial search in traditional fault verification methods. Only one node is needed for voltage measurement, but multiple excitations on accessible nodes are required for fault identification. Parameter evaluation can provide the exact solution to the deviated values of faulty parameters. The faulty parameter deviations can have any finite values. Example circuits are provided to illustrate the proposed method. Two other methods for multiple analogue fault diagnosis sharing the same mechanism as the method proposed in this paper are also briefly described. The proposed method is extremely effective for the circuit with very limited accessible nodes and is also computationally efficient. Copyright © 2002 John Wiley & Sons, Ltd.