High output impedance CMQOs using DVCCs and grounded components

In this paper a new circuit topology for realizing second‐order current‐mode quadrature oscillator is proposed. Three additional circuits are further derived from it, thus resulting in four distinct circuits. Each circuit employs three differential voltage current conveyors and all grounded passive components, ideal for IC implementation. All the circuits possess high output impedance. The circuits exhibit non‐interactive frequency control and low THD. The effects of non‐idealities are also analyzed. PSPICE simulations using 0.5 µCMOS parameters confirm the validity and practical utility of the proposed circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

A new parallel ZVS converter with less power switches and low current stress components

A new direct current (DC)/DC converter with parallel circuits is presented for medium voltage and power applications. There are five pulse‐width modulation circuits in the proposed converter to reduce current stress at low voltage side for high output current applications. These five circuits share the same power switches in order to reduce switch counts. To reduce the converter size, conduction loss, and voltage stress of power semiconductors, the series connections of power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with high switching frequency instead of insulated gate bipolar transistor (IGBT) with low switching frequency are adopted. Thus, the voltage stress of MOSFETs is clamped at half of input voltage. The switched capacitor circuit is adopted to balance input split capacitor voltages. Asymmetric pulse‐width modulation scheme is adopted to generate the necessary switching signals of MOSFETs and regulate output voltage. Based on the resonant behavior at the transition interval of power switches, all MOSFETs are turned on under zero voltage switching from 50% load to 100% load. The circuit configuration, operation principle, converter performance, and design example are discussed in detail. Finally, experimental verifications with a 1.92 kW prototype are provided to verify the performance of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.     

A wavelet‐based piecewise approach for steady‐state analysis of power electronics circuits

Simulation of steady‐state waveforms is important to the design of power electronics circuits, as it reveals the maximum voltage and current stresses being imposed upon specific devices and components. This paper proposes an improved approach to finding steady‐state waveforms of power electronics circuits based on wavelet approximation. The proposed method exploits the time‐domain piecewise property of power electronics circuits in order to improve the accuracy and computational efficiency. Instead of applying one wavelet approximation to the whole period, several wavelet approximations are applied in a piecewise manner to fit the entire waveform. This wavelet‐based piecewise approximation approach can provide very accurate and efficient solution, with much less number of wavelet terms, for approximating steady‐state waveforms of power electronics circuits. Copyright © 2006 John Wiley & Sons, Ltd.     

A systematic class AB state space synthesis method based on MOSFET square law and translinear square‐root cells

A new state space Class AB synthesis method for the design of square‐root domain filter based on the MOSFET square law is proposed in this study. Those circuits designed by the proposed Class AB systematic synthesis method have the advantages of Class AB circuit structure and translinear circuits. Two alternative design procedures were suggested for designing new circuits. Proposed synthesis technique is applied for designing of a first order all‐pass filter and a third order low‐pass filter. Circuits are simulated in PSpice using 0.35 µm CMOS technology parameters. Time domain and frequency domain analysis of the proposed filters are performed, and simulation results of those are also presented. The simulation results show that the proposed synthesis technique is appropriate for the design of different types of filters and has the advantages of Class AB circuit structure. Copyright © 2015 John Wiley & Sons, Ltd.     

A fully electronically controllable Schmitt trigger and duty cycle‐modulated waveform generator

The paper introduces a new Schmitt trigger consisting of only one multiple‐output current inverting differential input transconductance amplifier with no passive element. The proposed circuit is simple and usable up to 100 MHz with the advantage of electronically controlled threshold levels and amplitude of the output. The circuit is also little sensitive to temperature and benefits from low power dissipation (0.5 mW). The amplitude of the output current is tunable electronically from 5 nA to 500 μA, which is a wide tunable range. The effects of transistors mismatch on proposed Schmitt trigger have also been explored. The utility of the proposed circuit is further justified through its application as a triangular/square wave generator, with a maximum frequency of 75 MHz. Duty cycle modulation through electronic means is also shown for the generator circuit, where duty cycle results for 80, 20, and 95% have been included, by varying external control current. The cadence VIRTUOSO simulation results by using generic process design kit 90‐nm technology are shown to confirm the proposed theory. The proposed circuits are also verified through experimental results by using commercial integrated circuits: AD844 and LM13700. All the simulated and experimental results promise potential applications of the proposed circuits in instrumentation and communication systems. Copyright © 2017 John Wiley & Sons, Ltd.     

Design of current‐mode MOSFET‐C filters using OTRAs

In this paper, third‐order current‐mode MOSFET‐C filters that use operational transresistance amplifiers (OTRAs) with little parasitic capacitance effects are presented. On the basis of the proposed systematic method and design procedure, we can efficiently synthesize third‐order active filters with OTRAs along with simplified MOSFET resistor circuits, and all virtually grounded capacitors. Third‐order current‐mode Chebychev low‐pass and high‐pass filters are realized to verify the validity of the theoretical analysis. Experimental results employing commercially available current feedback amplifiers are also given. Copyright © 2008 John Wiley & Sons, Ltd.     

Implementation and design of high‐power fast charger for lithium‐ion battery pack

The high‐power fast charger (HPFC) incorporating a power stage with a controlling loop is presented in this paper. A power stage is composed of an inter‐leaved boost power factor correction and a DC‐DC full‐bridge phase‐shifted (FBPS) converter, and that the HPFC can supply a constant‐voltage (CV) or a constant‐current (CC) power to charge a secondary lithium‐ion battery pack. In addition, the ripple current can be reduced due to the DC‐DC FBPS converter combines with the current‐doubler rectifier at HPFC's output side. Also, the controlling loop is equipped with a voltage compensator and a current compensator, and this design is for the sake of HPFC, which can either operate in CV or CC output mode. Moreover, the shut‐down situation will be prevented by proposed bi‐phase charging controller, when the charging current is adjusted from the fist CC level to the second CC level. Analysis and design considerations of the proposed circuits are presented in details. Experimental results agree well with the theoretical predictions and confirm the validity of the proposed approach. Copyright © 2013 John Wiley & Sons, Ltd.     

A simple control scheme for a single stage flyback LED driver

This study proposes a simple control scheme for using single‐stage flyback (SSF) converters in lighting source applications for LEDs. Among the advantages of the average current mode is an I/O current ripple that is only one‐half of the critical conduction mode (CRM). This condition helps extend the output capacitor lifetime while lowering the input EMI capacitance input EMI capacitance. The SSF converter proposed in this study operates in continuous conduction mode (CCM). In addition, two sample‐and‐hold (S/H) circuits are placed at the output voltage loop and feed‐forward path, respectively. Since these S/H circuits access the average output current and average feed‐forward voltage, the LED driver is unaffected by the 120‐Hz ripple noise, the total harmonic distortion (THD) is reduced, and the transient response of the output current is improved. Finally, the operation principles and design considerations of the studied LED driver are analyzed and discussed. A laboratory prototype is also designed and tested to verify the feasibility. Copyright © 2014 John Wiley & Sons, Ltd.     

Realization of a multiport gyrator using current mirror circuits

A current‐mode signal processing circuit is quite attractive for low supply voltage operation and high‐frequency application. A current‐mode continuous‐time filter consists of simple bipolar current mirrors and capacitors, and are quite suitable for monolithic integration. In this paper, we propose a design for a multiport gyrator using current mirror circuits. Using the multiport gyrator and capacitors, we can simulate passive LC filters. The tuning of the filter frequency can be achieved by adjusting the current of a single dc current course. As examples, third‐ and fifth‐order low‐pass filters are designed for frequencies of 20 to 80 MHz, and SPICE simulation results are shown to demonstrate the effectiveness of the proposed method. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 139(4): 41–47, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.1167     

A design of MOSFET‐C impedance simulation circuits based on a GIC

This paper proposes a systematic design method of MOSFET‐C impedance simulation circuits based on a generalized immittance converter (GIC). The design method can realize inductance simulation circuits, capacitance multipliers and frequency‐dependent negative resistances (FDNRs) only by MOSFETs, capacitors and two operational amplifiers. Although MOSFETs are used instead of passive resistors, the realized impedance simulation circuits have good linearity since the nonlinearity caused by MOSFETs are cancelled out. The proposed design method derives three inductance simulation circuits, five capacitance multipliers and two FDNRs systematically from a GIC. All of them are summarized in this paper. As an example, inductance simulation circuits are designed by using the proposed design method. The inductance simulation circuits are applied to a filter realization and validity of the design method is confirmed by HSPICE simulations. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

All‐pass filters using DDCC‐ and MOSFET‐based electronic resistor

The main motivation in this paper is to draw attention to the tunability and input‐signal amplitude limitations when a nonlinear device is used as a resistor. For this purpose, two first‐order all‐pass filters are proposed using differential difference current conveyor (DDCC), a capacitor and a resistor without element‐matching restriction. These all‐pass filter circuits can be made electronically tunable with electronic resistors. Tunability and input‐signal amplitude limitations of the proposed circuits due to the operational restrictions of the electronic resistors are examined. PSPICE simulations confirm the validity and the practical utility of the proposed circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

Linear circuits: a measurement‐based approach

This paper proposes a new measurement‐based approach that can solve synthesis problems in unknown linear circuits. The method makes use of a small number of measurements to determine the functional dependency of any circuit signal or variable on any set of design variables. Once the functional dependency is obtained, the design requirements can be applied to find the design parameter values. The results are described for linear direct current and alternating current circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

High input impedance voltage‐mode first‐order all‐pass sections

This paper proposes six new first‐order voltage‐mode all‐pass sections (VM‐APSs) based on three general topologies. Each circuit uses two differential voltage current conveyors and three grounded passive components. All the circuits possess high input impedance and easy control of pole frequency either by a simple matching of resistors (two equal‐valued resistors) for the three canonical circuits or by a single resistor for three non‐canonical circuits. PSPICE simulation results using real device 0.5µ CMOS parameters are given to validate the proposed circuits. Copyright © 2007 John Wiley & Sons, Ltd.     

Time‐mode circuits for analog computation

We introduce time‐mode circuits, a set of basic circuit building blocks for analog computation using a temporal step function representation for the inputs and outputs. These novel time‐mode circuits are low power, provide good noise performance and offer improved dynamic range. The design, IC implementation and detailed theoretical signal‐to‐noise ratio (SNR) analysis of a prototype time‐mode circuit—a weighted average computation circuit—are discussed. This new way of computation is studied with respect to existing conventional voltage‐mode and current‐mode circuits. Two possible applications of these time‐mode circuits are presented: an edge detection circuit for 16 pixels and a 3‐tap FIR filter that provides an SNR of 64 dB. Copyright © 2008 John Wiley & Sons, Ltd.     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Optimal sizing and design of CMOS analogue amplifier circuits using craziness‐based particle swarm optimization

This paper presents the optimal designs of two analogue complementary metal–oxide–semiconductor (CMOS) amplifier circuits, namely differential amplifier with current mirror load and two‐stage operational amplifier. A modified Particle Swarm Optimization (PSO), called Craziness‐based Particle Swarm Optimization (CRPSO) technique is applied to minimize the total MOS area of the designed circuits. CRPSO is a highly modified version of conventional PSO, which adopts a number of random variables and has a better and faster exploration and exploitation capability in the multidimensional search space. Integration of craziness factor in the fundamental velocity term of PSO not only brings diversity in particles but also pledges convergence close to global best solution. The proposed CRPSO‐based circuit optimization technique is reassured to be free from the intrinsic disadvantages of premature convergence and stagnation, unlike Differential Evolution (DE), Harmony Search (HS), Artificial Bee Colony (ABC) and Particle Swarm Optimization (PSO). The simulation results achieved for the two analogue CMOS amplifier circuits establish the efficacy of the proposed CRPSO‐based approach over those of DE, HS, ABC and PSO in terms of convergence haste, design conditions and design goals. The optimally designed analogue CMOS amplifier circuits occupy the least MOS area and show the best performance parameters like gain and power dissipation, in compared with the other reported literature. Copyright © 2016 John Wiley & Sons, Ltd.     

A class of versatile circuits,made up of standard electrical components,are memristors

In this paper, we propose a whole class of memristor circuits. Each element from the class consists of the cascade connection between a static nonlinear two‐port and a dynamic one‐port. The class may be divided into two subclasses depending on the input variable (voltage or current). Within each of these subclasses, two further sets of memristor circuits may be distinguished according to which output voltage and current of the two‐port represents one of the system states. The simplest memristor circuits make only use of purely passive elementary components from circuit theory, an absolute novelty in this field of research. Thus they are suitable circuit primers for the introduction of the topic of memristors to undergraduate students. A sample circuit is built using discrete devices and its memristive nature is validated experimentally. In case the one‐port is purely passive, the proposed circuits feature volatile memristive behavior. Allowing active devices into the dynamic one‐port, non‐volatile dynamics may also emerge, as proved through concepts from the theory of nonlinear dynamics. Given the generality of the proposed class, the topology of the emulators may be adjusted so as to induce a large variety of dynamical behaviors, which may be exploited to accomplish new signal processing tasks, which conventional circuits are unable to perform. Copyright © 2015 John Wiley & Sons, Ltd.     

Analysis and design of voltage‐controlled current sources for a grounded load

The paper presents the structure and the principle of operation of the ‘improved’ Howland current pumps (or voltage‐controlled current sources (VCCSs) for a grounded load). In particular, under review is the VCCS employing power operational amplifier (op amp) and the VCCS using low power op amp and an additional power transistor, extending working dynamic range. On the basis of analysis of the operational principle, the equations for transfer functions of both circuits and formulas for the related dynamic electrical parameters are obtained. Moreover, using these formulas, a design procedure is developed, and recommendations for simulation modelling are given. The efficiency of the proposed procedure is verified by simulation modelling and experimental testing of sample electronic circuits of VCCSs. Copyright © 2013 John Wiley & Sons, Ltd.     

Innovative design methodologies in quantum‐dot cellular automata

Current transistor‐based IC fabrication technology faces many trivial issues such as those of excess power dissipation, expensive fabrication and short channel effects at very low device size [1]. Quantum‐dot cellular automata (QCA)‐based digital electronics on the other hand provide scope for further development in the future by shrinking the device size. Current QCA logic circuits are based on logic synthesis using Inverters and (three or five input) Majority Gates. In this paper, a new design methodology has been described that can be used to create circuits with even greater device substrate densities than what are currently achieved in existing QCA designs. Based on the proposed methodology, a new QCA inverter is proposed. It is further tested through simulations on QCA Designer. Through the simulations, it is subsequently proved to be much more reliable and robust than the presently used common QCA inverter(s). In the second section of this paper, simple QCA circuits such as ring oscillators using odd number of inverters in daisy chains are described and designed using the proposed inverter design. Copyright © 2013 John Wiley & Sons, Ltd.     

All‐pass sections with rich cascadability and IC realization suitability

In this paper, two new circuit configurations for realizing voltage‐mode (VM) all‐pass sections (APSs) are presented. The proposed circuits employ only two differential voltage current conveyors (DVCCs) and are cascadable with other VM circuits due to their high‐input and low‐output impedances. The first configuration uses a grounded resistor and a grounded capacitor without requiring matching constraints, whereas the second employs two grounded resistors and a grounded capacitor with a single matching condition. While the first configuration can realize only one all‐pass response, the second can provide inverting and non‐inverting all‐pass responses with selection of appropriate input port. Adding two grounded resistors to the proposed filters, variable gain APSs can also be obtained. As applications, two quadrature oscillators, each of which using one of the proposed all‐pass circuits, one grounded resistor and one grounded capacitor are presented. SPICE simulation results are included to verify the theory. Copyright © 2010 John Wiley & Sons, Ltd.