High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

Novel polycrystalline silicon thin film transistors prepared by deposition from Si2H6 and subsequent annealing by NH3 plasma

This work investigated the channel layer of polycrystalline silicon (poly-Si) thin film transistors (TFTs) prepared by amorphous silicon (a-Si) films deposited using Si₂H₆ gas. The recrystallization of channel layers, source/drain, gate electrodes and post implant anneal were performed at the same time. Due to the larger grain size, the device has higher field effect mobility than SiH₄ deposited devices. These devices were also subsequently passivated by NH₃ plasma. The NH₃ plasma significantly improves the n-channel devices; however, the improvement of p-channel devices is limited. Especially, the threshold voltage of n-channel devices is significantly shifted toward the negative gate voltage than the shift magnitude of p-channel devices. To investigate the band gap width and Fermi level by determining the leakage activation energy, it is found that the channel film is changed slightly from p-type to n-type. These results may be attributed to the donor effect by NH₃ plasma passivation.     

Polycrystalline silicon thin-film transistors on a novel 800°C glass substrate

A new polycrystalline silicon thin-film transistor (TFT) technology using a potentially low-cost glass substrate is reported. Transistors are made using modified conventional n-channel MOS processes at temperatures of 800°C or less, with a final hydrogen implantation step. These transistors show leakage currents of 2 × 10^-11A/µm of channel width, ON-to-OFF current ratios of 1 × 10⁴at Vds= 9.0 V, and good dc stability. This combination of polycrystalline silicon transistors on potentially low-cost glass substrates offers a new option in the choice of active device technology for large-area flat-panel liquid crystal displays (LCD's).     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

High-performance thin-film silicon-on-insulator CMOS transistors inporous anodized silicon

Ultrathin-film silicon-on-insulator (SOI) CMOS transistors, produced in silicon islands 100 nm thick, formed by oxidation of porous anodized silicon, are described. Both n-channel and p-channel mobilities are similar to equivalent bulk values. Subthreshold slopes are less than 80 mV/decade and junction leakages are approximately 0.1 pA/μm. No kink is seen in the output characteristics of the n-channel transistors as the silicon film is fully depleted. A ring-oscillator gate delay of 161 ps has been achieved, at a power dissipation of 270 μW/stage, for 1.5-μm gate length     

An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I²L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (leq 2 microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n⁺buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

Realization of n-channel and p-channel high-mobility (Al,GA)As/GaAs heterostructure insulating gate FET's on a planar wafer surface

Self-aligned gate by ion implantation n-channel and p-channel high-mobility (Al,Ga)As/GaAs heterostructure insulated-gate field-effect transistors (HIGFET's) have been fabricated on the same planar wafer surface for the first time. Enhancement-mode n-channel (Al,Ga)As/GaAs HIGFET's have demonstrated extrinsic transconductances of 218 mS/mm at room temperature and 385 mS/mm at 77 K. Enhancement-mode p-channel (Al,Ga)As/GaAs HIGFET's have demonstrated extrinsic transconductances of 28 mS/mm at room temperature and 59 mS/mm at 77 K. There are the highest transconductance values ever reported on a p-channel FET device.     

Subquarter-micrometer gate-length p-channel and n-channel MOSFETswith extremely shallow source-drain junctions

The fabrication of p-channel and n-channel MOSFETs with sub-quarter-micrometer n⁺ polysilicon gates, have been fabricated using extremely shallow source-drain (S-D) junctions, is reported p⁺-n junctions as shallow as 80 nm have been fabricated using preamorphization low-energy BF₂ ion implantation and rapid thermal annealing, and 80-nm n⁺-p junctions have been fabricated using low-energy arsenic ion implantation and rapid thermal annealing. n-channel MOSFETs with 80-mm S-D junctions and 0.16-μm gate lengths have been fabricated, and a maximum transconductance of 400 mS/mm has been obtained. 51-stage n-channel enhancement-mode/enhancement-mode (E/E) ring oscillators and p-channel E/E ring oscillators with extremely shallow S-D junctions have also been obtained     

A 30-V row/column driver for flat-panel liquid crystal displays

An 80-output row/column driver has been developed for flat-panel liquid crystal displays (LCDs) using multiplex rates of up to 1:300. A p-well polysilicon-gate CMOS process was enhanced to provide 30-V p-channel and 15-V n-channel transistors using double-diffused drains. By means of a cascode circuit structure, voltage capability on the n-channel side was boosted to 30 V. Parasitic surface channels were avoided by a systematic approach to high-voltage layout. Important circuit features include low power consumption, display border control, and overtemperature protection. Chip size is 25.65 mm². Packaging in an 18.6 mm×15.2 mm, three-sided, 120-lead, tape-automated-bonding module is optimized for wiring on single-sided assembly substrates     

Low-power and high-stability SRAM technology using alaser-recrystallized p-channel SOI MOSFET

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 10⁴, and the source-drain leakage current is decreased by a factor of 10-10² compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs     

Polycrystalline silicon thin-film transistors fabricated by rapid Joule heating method

We report n- and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated with a rapid joule heating method. Crystallization of 50-nm-thick silicon films and activation of phosphorus and boron atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO/sub 2/ intermediate layers from joule heating induced by electrical current flowing in chromium strips. The effective carrier mobility and the threshold voltage were 570 cm/sup 2//Vs and 1.8 V for n-channel TFTs, and 270 cm/sup 2//Vs and -2.8 V for p-channel TFTs, respectively.     

Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors

We present a reproducible approach to the fabrication of super-self-aligned back-gate/double-gate n-channel and p-channel transistors with thin silicon channels and thick source/drain polysilicon regions. The device structure provides capability for scalable control of channel electrostatics, threshold variability without sacrificing source/drain series resistance, and capability of introducing strain to improve carrier transport. The separate device, circuit, and functional level back-gate access that is available through bottom interconnection also provides capability for adaptive power control and novel circuit design. Both n-channel and p-channel devices are demonstrated with the threshold tuning capability     

Fabrication of Si MOSFET's using neutron-irradiated Silicon as semi-insulating substrate

The feasibility of a novel silicon-on-semi-insulating substrate structure has been demonstrated. MOS field-effect transistors (MOSFET's) are fabricated on neutron-irradiated silicon wafers which are used as semi-insulating substrates. In order to keep the substrate semi-insulating, laser annealing is used to make the semiconducting layer, and to activate the impurities implanted in the semiconducting layer, and plasma anodization is employed to grow the gate oxide. The mobility of carrier in the channel is about 100 cm²/V . s for p-channel MOSFET's and 300 cm²/V . s for n-channel devices. This structure has inherent advantages such as crystallographically single crystalline.     

On the origin of leakage currents in silicon-on-sapphire MOS transistors

n-channel n-p-n metal-oxide-semiconductor transistors (MOST's), fabricated in thin films of silicon-on-sapphire, exhibit values of source-to-drain leakage currents (IL)which vary from wafer to wafer, typicaily from 10^-11to 10^-7A/mil of channel width. Conversely, p-channel (p-n-p) devices exhibit low leakage current values in the range of 10^-11∼ 10^-10A/mil of channel width, consistent from wafer to Wafer. A model of a high concentration of donorlike states in the silicon in the vicinity of the Al2O3-Si interface creating a back-surface Conductive channel is proposed to account for both the inconsistently high n-channel and consistently low p-channel leakage current values. Experimental measurements of IL, which support the general conclusions of the model, are presented. ILis shown to be a strong function of a) the annealing temperature of the sapphire substrate prior to film growth, b) the silicon-film growth rate, c) the impurity concentration profile in the channel region, and d) the device geometry. These measurements show that the dominant factor controlling the overall magnitude of ILis the state of the Al2O3-Si interface immediately prior to silicon-film growth. A set of silicon-film growth conditions and device processing steps is outlined which achieve consistent n- and p-channel leakage current values of less than 10^-9A/mil of gate width.     

Complementary DMOS process for LSI

This paper describes a new complementary metal-oxide semiconductor (CMOS) integrated circuit technology that utilizes a symmetrical double-diffused n-channel transistor. The features of the technology are the use of five masks, a self-aligned p-well diffusion and short channel n-MOS transistors. This results in a fifty percent reduction in p-well area as compared to conventional CMOS devices and lowers processing costs. Integrated circuits, fabricated using boron implantation for the p-well dose and p/SUP +/ diffusion, and arsenic implantation for the n/SUP +/ diffusion, exhibit a p-channel threshold of -1.8 V and an n-channel threshold of 1.2 V. The n-channel threshold is controlled by an initial boron implant of 3/spl times/10/SUP 14/ cm/SUP -2/ and subsequent double-diffusion steps. An invertor chain of seven cells bas been operated with a supply of 3-11 V. In operation, the delay per stage was 13 ns at 5 V and 5 ns at 10 V.     

Improved subthreshold characteristics of n-channel SOI transistors

It has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can havelog (I_{d}): V_{gs}, characteristics with very steep slopes in the subthreshold region. In contradiction to normal models for short-channel transistors on bulk silicon, the slope becomes steeper for shorter gate lengths or higher drain voltages. This effect is shown to be related to the kink in the output characteristics of transistors with floating islands.     

Role of nitridation/reoxidation of NH3-nitrided gatedielectrics on the hot-carrier resistance of CMOS transistors

The effect of nitriding and reoxidizing conditions are examined on the hot-carrier (HC) properties of p-channel and n-channel transistors with reoxidized nitrided oxide gate dielectrics. Nitrogen was introduced into the gate dielectric by performing cyclical nitridation and reoxidation steps (one cycle versus four cycles of nit./reox.), keeping the same overall oxidation and nitridation times constant, It was found that there were considerable differences in hot-carrier hardness, of up to three orders of magnitude for p-channel transistors, but much less for n-channel devices. Nitrogen-content variations (a factor of 2) for these very similar conditions explain the n-channel hot-carrier results. In the case of the p-MOS transistors, it is suggested that changes in hydrogen concentration might be responsible for the hot-carrier behavior     

Fabrication and properties of ESFI-SOS-MOST's suitable for both low-voltage and low-power circuits

The fabrication and the properties of ESFI-SOS p-channel deep-depletion and n-channel inversion transistors are discussed. These devices are aimed to be used in integrated circuits with both low supply voltage and low power consumption. It turns out that certain device parameters such as reverse current, leakage current, threshold voltage, and channel mobility are strongly correlated and that a proper set of process parameters (e.g., optimum process temperature, ion implantation dose, and implantation energy) exists permitting device fabrication most suitable to meet the goal mentioned above. Furthermore, the subthreshold behavior is investigated experimentally and theoretically and the density of fast interface states at the SiO2-Si interface is determined.     

Double-implanted GaAs complementary JFET's

The fabrication and performance characteristics of double-implanted GaAs complementary junction field-effect transistors (JFET's) suitable for low-power digital integrated circuit applications are described. Effective mobilities for the n-channel enhancement-mode JFET are 3500 cm²/V.s and for the p-channel 300 cm²/V.s. Experimental results of an ultra-low-power static RAM are presented.     

Amorphous-silicon silicon-nitride field-effect transistors

n-channel and p-channel amorphous-silicon field-effect transistors have been fabricated on a glassy substrate using undoped and impurity-doped a-Si films as the semiconductor and silicon nitride deposited from an SiH4-N2 mixture as the gate insulator. A change in the source-drain conductance of greater than four orders of magnitude is realised by changing the gate potential from 0 to 5 V.