面向寄存器的流水线处理器建模及验证方法

提出了一种新的流水线处理器功能的验证方法,这种方法的主要思想是通过验证流水线处理器中所有寄存器的功能来验证处理器的功能.流水线处理器绝大部分是由同步电路组成的,同步电路的状态则完全由寄存器的状态决定,因此如果能够保证每个寄存器功能正确就可以保证整个同步电路功能正确.对于流水线处理器来说,寄存器状态的变迁是由处理器的原始输入和寄存器本身状态决定的.原始输入包括控制信号(如复位信号)和数据输入(如指令输入).如果把对每个寄存器的赋值操作转换成对控制信号和数据输入的操作,就可以生成一个验证序列,这个序列包括每个时钟周期控制信号和数据输入的值.有了这个序列就可以把目标设计和参考模型进行结果比较,从而验证目标设计功能是否正确.同时这种方法也便于调试.     

数字有线电视技术系列讲座 第四讲 信源编码(下)

４　循环码汉明码是利用线性代数或在信息码和监督码之间形成确定的关系来检错和纠错。我们也可以用其他数学关系来完成这一任务，例如有一个具有某种运算功能的移位寄存器，如图２所示。如果原始状态为０１０，且输入在每个时钟都是零，那么移位寄存器随后每个时钟的内容为：０１０，１００，０１１，１１０，１０１，００１，０１０。经过７个周期又回到了原始状态。实际上以上结果也可以由某种运算得到。例如可以用多项式ｘ３＋ｘ＋１来表示该电路。多项式中两个“＋”号代表了原电路中的两个模２加，ｘ３代表了距离输入最远的移位寄存器…     

移位寄存器的Multisim仿真

介绍用Multisim仿真软件分析移位寄存器逻辑功能的方法,验证了4-D触发器构成的移位寄存器的逻辑功能。用Multisim仿真软件中的字组产生器产生的信号作为移位寄存器的时钟脉冲和输入数据,字组内容反映移位寄存器的输入信号和控制信号,用Multisim中的逻辑分析仪多踪同步显示各输入信号、控制信号和输出信号波形,直观地描述移位寄存器的工作过程。所述方法创新地解决了移位寄存器工作过程无法用实验仪器验证的问题。     

数字信号处理器分布式寄存器的写回设计

针对分布式寄存器文件应用于高性能超长指令字（VLIW）数字信号处理器而造成的分支流水线与写回控制信号的同步问题,提出了一种面向分布式本地寄存器文件的写回策略。其中包括指令执行周期的产生,写回信号缓存以及写回控制单元。采用了面积功耗性能评估方法,结果证明了该策略能充分发挥分布式寄存器文件在功耗方面的优势,相对于运用集中式寄存器文件可以减少50％的功耗,同时对于传统流水线写回控制方法可以节省60％的面积开销。     

RISC-DSP处理器中指令数据相关性的提前判断方法

RISC-DSP处理器中执行周期数动态可变的指令对数据相关检测造成了困难。该文通过分布式相关检测模型将检测操作转换为依赖关系集合的计算,推测不同流水线状态下后一周期中的依赖关系集合,并根据当前指令相关性和功能单元发出的信号确定当前流水线状态,从而提前判断出下一周期中的指令相关性。按照其集合操作的特点进行逻辑优化,并以所研制的RISC-DSP处理器MediaDSP64原型机为例进行电路实现。综合结果表明,在对整体电路资源和功耗影响较小的前提下,从原先流水线关键路径中隐藏了相关检测电路,其延时下降了约30%。     

简易数字信号传输性能分析仪的设计

本设计由STC89C52单片机控制模块、数字信号发生模块、液晶显示模块、伪随机信号发生模块、低通滤波模块、数字信号分析电路组成。通过D触发器与异或门电路以线性移位寄存器构成m序列生成器,并由数字信号分析电路产生锯齿波扫描电压,通过示波器显示眼图,滤波器采用四阶有源模拟滤波器设计实现。STC89C52单片机定时器控制产生信号发生器的时钟信号,并可以通过矩阵键盘控制m序列数据率的调整,其数据率和档位在单片机的控制下调整并由液晶显示。伪随机信号发生器时钟信号由10MHz的有源晶振提供,经两个74LS273级联,在异或门的控制下产生伪随机信号。三个低通滤波器采用宽带四阶巴特沃斯滤波器,带内增益调整范围为0.2-4.5;信号分析电路主要产生数据同步信号,并经锁相倍频及DAC转换器输出锯齿波扫描电压,以显示信号分析眼图。经实验测试及分析,本设计完成了m序列信号与噪声的生成叠加,滤波器设计与信号分析及同步扫描信号生成,形成眼图观测功能。     

基于PT6311+MCU的键扫描与VFD显示的编程实现

作为VFD显示控制及驱动器芯片,PT6311的核心功能仍然是实现VFD显示控制与驱动.芯片的硬件结构主要由扫描信号发生器、串行通信接口、控制模块、显示存储器、按键扫描值寄存器、通用输入寄存器、LED驱动器、VFD段/位驱动器等构成.PT6311内部电路原理框图如图1所示.     

同步网中SSM应用实例

同步状态信息 (ＳＳＭ ,ＳｙｎｃｈｒｏｎｉｚａｔｉｏｎＳｔａｔｕｓＭｅｓ ｓａｇｅ)也称为同步质量信息 ,用于在同步定时传递链路中直接反映同步定时信号的质量等级。具有ＳＳＭ功能则意味着同步定时传递链路中的每一个节点时钟都能够在接收到从上游节点传来的同步定时信号的同时 ,也接收到ＳＳＭ ,根据这些信息来判断所收到的同步定时信号的质量等级 ,以控制本节点时钟的工作状态 (如继续跟踪该信号 ,或倒换输入基准信号或转入保持状态 )。如果数字同步网中每个节点时钟都能收到上游节点送来的ＳＳＭ ,从而控制本身的时钟处于正确的工作…     

基于无冲突地址生成的高性能FFT处理器设计

提出一种基于存储器交织架构的FFT处理器设计方法,并且针对基-8FFT提出一种无冲突地址生成算法,数据按帧进行操作。每个存储器均划分为8个独立的存储体,通过对循环移位寄存器译码,蝶式运算单元并行无冲突读写操作数,8通道输入数据进行并行的复数乘法运算。每级运算引入完全流水,减少了运算的时钟周期开销,同时推导出局部流水线设计必须满足的不等式条件。输入、输出存储器采用乒乓操作,按帧轮换,FFT运算连续输入、输出,采样频率与系统工作频率一致,具有很好的实时性,运算精度通过块浮点得到保证。该设计方法可以扩展至基-16FFT处理器设计。     

一种实现单片机工作在低功耗模式下的事件寄存器电路设计

基于微处理器的单片机广泛应用于各行各业,其低功耗模式一般采用间歇工作方式,通过外部事件产生中断信号,使处于休眠或掉电状态的处理器进入运行状态,为节省处理器的中断资源,简化单片机软硬件开发,设计一种由D型触发器组成的事件（中断信号）寄存器电路,将事件（中断信号）储存后供处理器读取。文中给出了事件寄存器电路设计,电路的PROTEUS仿真结果表明其与设计目标一致,该电路在基于PC104等处理器的低功耗系统中已得到应用。     

SDH芯片功能验证平台的设计与实现

集成电路芯片的规模不断增大，功能越来越复杂，设计验证工作量也越来越大，成为整个设计周期的“瓶颈”。文章针对同步数字体量（SDH）宽带交换芯片设计中的功能验证，设计了初步的SDH验证平台，提出了具有一定通用性的SDH芯片的功能验证方案和实现方法，包括分层的描述和验证方法，一系列标准测试数据和自动观测模拟结果的若干加速C程序。该平台已用于40Gbit／s交换芯片的功能验证，加速了验证过程，取得了满意的效果。     

A surface-charge shift register with digital refresh

A digital shift register using the surface-charge transistor structure in which adjacent rows propagate in opposite directions and which has refresh turn-around circuits at the ends of each row is described. Two process compatible refresh circuits requiring only four times the basic bit storage area have been designed, and a test circuit composed of two 16-bit shift registers that propagate in opposite directions and are connected by these circuits has been built and tested. The regeneration characteristics of these refresh circuits have been measured as a function of transfer time in both the complete and partial transfer modes (`fat zero'). Operation of one of these 32-stage shift registers and its refresh at 10 MHz is presented.     

电路板TPS验证评估系统设计

针对对电路板测试程序集(TPS)难以进行客观全面地验证评估的难题,对电路板验证评估系统进行了设计。首先分析了电路板TPS的组成以及常用的评估技术;其次,针对不同的部分分别提出了相应的评估策略;最后,通过将TPS各部分评估结果进行加权求和对整个电路板TPS进行验证评估。设计的电路板TPS验证评估系统综合考虑了电路板TPS的各个组成部分,能够对电路板TPS进行客观有效的评估。     

Seamless Pipelining of DSP Circuits

Pipelining is a popularly used technique to achieve higher frequency of operation of digital signal processing (DSP) applications, by reducing the critical path of circuits. But conventionally critical path is estimated by the discrete component timing model in terms of the times required for the computation of additions and multiplications, where arithmetic circuits are considered as discrete components. Pipeline registers are inserted in between arithmetic circuits to reduce the estimated critical path. In this paper, we show that very often the architecture-level pipelining, based on the discrete component timing model, does not result in significant reduction in critical path, but on the other hand increases the latency and register complexity. In order to derive greater advantage of pipelining, propagation delays of different combinational sections could be evaluated precisely at gate level or at least at the level of one-bit adders, and based on that, the critical path could be reduced by placing the pipeline registers seamlessly across the combinational datapath without restricting them to be placed only in between arithmetic circuits. In this paper, we present adequately precise evaluation of propagation delays across combinational path as a network of arithmetic circuits based on seamless view of signal propagation. Using the precise information of propagation delay of combinational sections, we identify the best possible locations of pipeline registers in order to reduce the critical path up to the desired limit. The proposed seamless pipelining approach is found to achieve the desired acceleration of DSP applications without significant pipeline overhead in terms of latency and register complexity.     

基于周期粒度的级间寄存器备份机制

单粒子翻转是空间环境下微处理器发生异常的重要诱因之一,随着集成电路特征尺寸的缩小,单粒子翻转不仅会引发单位错误,还会引发大量的多位错误,如何有效解决处理器所面临的多位故障是容错处理器设计面临的新挑战.本文提出了一种基于周期粒度的级间寄存器备份机制的容错方法,采用双流水线冗余结构,通过比较器对比两条流水线的级间寄存器以检测单粒子故障;以周期粒度对级间寄存器的内容进行备份,当检测到单粒子故障时,使用2个周期对流水线进行恢复;为避免脏数据流出流水线,在数据缓存和寄存器堆的入口设置写缓冲,通过延迟写入保证信息可靠性.本文基于实际的SPARC V8结构处理器,对提出的方法进行了具体实现,在实验平台上进行了仿真,仿真结果显示,本文提出的容错方法能够以一定的面积开销实现对SEU、SET、和MBU故障容错,加固处理器的主频最高可以提升70%.     

时序电路的冗余状态变换确认研究

本文以状态跳变图为基础,深入分析冗余变换与非法变换的特征,提出结构冗余和功能冗余的概念,并讨论了可测、不可测故障与冗余之间的联系。最后结合验证和测试生成,提出状态冗余的隐含遍历确认策略。     

Causal reasoning mining approach to analog circuit verification

Functional errors in analog portion of mixed signal circuits become more severe and improvements in verification methods are increasingly important. Current verification methods fall into two categories, simulation-based verification and formal verification (Barke et al. [1]), focusing on verifying analog circuit function/performance. This paper proposes a novel approach verifying analog circuit design using causal reasoning. Causal reasoning is the inductive reasoning process to create a new design. The flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justifications (Jiao et al., 2015 [2]). Then, topological features corresponding to the starting ideas and design step sequence are verified individually by replacing the related devices with ideal behavior model. Performance is evaluated through Cadence Spectre simulation. Comparison with new circuit performance reveals incorrect functional issues and/or performance potentials for improvement. They are negative causes of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.     

IPOA组包功能的验证系统

介绍一种对IPOA应用中的组包功能进行RTL功能验证的系统。该验证系统可根据用户输入数据自动产生ATM信元作为激励 ,并对被测系统的输出进行自动验证。通过该验证系统大大提高了验证效率 ,缩短了仿真时间。同时 ,该系统产生的激励可对被测系统进行彻底的功能验证 ,提高了验证过程中代码覆盖率     

一类非线性扩频序列的构造及其性能分析

基于本原三项式线性函数,构造了一类非线性序列.首先根据非线性序列生成规律,借助逻辑代数理论,推导并提取了非线性序列特征函数,利用特征函数筛分作用,合成了非线性反馈函数,据此实现了非线性序列生成.最后,对该类非线性序列特性进行了分析和计算,并将其应用于直接序列码分多址通信系统(DS-CDMA)仿真实验中,结果表明该类非线性序列不仅具有理想的伪随机特性、良好的线性复杂度,还具有优于m序列、gold序列的误码率.     

Fast co-verification of HDL models

This paper presents a method for functional verification of HDL models of digital circuits. The method is based on a co-operation between a simulator and an emulator and utilizes the advantages of both simulation-based and emulation-based verification to form a fast co-verification approach. This is done by verifying the intensive time-consuming part of the circuit in the emulator and the non-synthesizable part as well as the part of the circuit that needs intensive redesign process during the early steps of the design phase in the simulator. To demonstrate the co-verification approach, a tool was developed, which supports Verilog, VHDL, and mixed Verilog-VHDL models. Three benchmarks including a simple 32-bit processor (DP32), a 16-bit arithmetic RISC processor, and a 256-point FFT unit were used in the experiments. The experimental results show that the co-verification approach gives up to 15,000 times speedup for gate-level and up to 100 times speedup for RTL abstractions as compared with the simulation-based verification. Finally, an analytical study on the speedups of the co-verification approach is also presented, which supports the experimental speedups results.