2.5-THz GaAs monolithic membrane-diode mixer

A novel GaAs monolithic membrane-diode (MOMED) structure has been developed and implemented as a 2.5-THz Schottky diode mixer. The mixer blends conventional machined metallic waveguide with micromachined monolithic GaAs circuitry to form, for the first time, a robust, easily fabricated, and assembled room-temperature planar diode receiver at frequencies above 2 THz. Measurements of receiver performance, in air, yield at T_receiver of 16500-K double sideband (DSB) at 8.4-GHz intermediate frequency (IF) using a 150-K commercial Miteq amplifier. The receiver conversion loss (diplexer through IF amplifier input) measures 16.9 dB in air, yielding a derived “front-end” noise temperature below 9000-K DSB at 2514 GHz. Using a CO₂-pumped methanol far-infrared laser as a local oscillator at 2522 GHz, injected via a Martin-Puplett diplexer, the required power is ≈5 mW for optimum pumping and can be reduced to less than 3 mW with a 15% increase in receiver noise. Although demonstrated as a simple submillimeter-wave mixer, the all-GaAs membrane structure that has been developed is suited to a wide variety of low-loss high-frequency radio-frequency circuits     

A Very Low-Noise Integrated 3MM-Wave Schottky Diode Mixer and PHEMT IF Amplifier

An integrated 3mm-wave Schottky diode mixer and pseudomorphic high-electron-mobility transistor (PHEMT) IF amplifier with record noise performance at room temperature is described. The design has shown the room-temperature double-sideband (DSB) receiver noise temperature T _R ^DSB of 190 K at 100 GHz due to a very low conversion loss in the full-height waveguide mixer and an ultra-low noise of the PHEMT IF amplifier. The receiver noise temperature has been reduced by a factor of 1.5 in comparison with the best previously reported 3mm-wave Schottky diode mixer receiver.     

Low-noise Quasioptical 2,0-mm and 1,5-mm Schottky mixer receivers

Quasioptical 2-mm and 1,5 mixer receivers for room temperature operation are described. Receivers incorporates polarization-rotationing dual-beam interferometers, used as antenna-heterodyn diplexer, waveguide Schottky diode mixers, carcinotron (BWO) and carcinitron with the frequency doubler, used as local oscillators (LO), and GaAs IF amplifiers. The best receiver noise temperatures are 600K (DSB) at 2,0-mm and 800K (DSB) at 1,5-mm wavelengths bands. The performance of these receivers is also discussed.     

AN UNCOOLED VERY LOW NOISE SCHOTTKY DIODE RECEIVER FRONT-END FOR MIDDLE ATMOSPHERIC OZONE AND CARBON MONOXIDE MEASUREMENTS

The paper describes an uncooled front-end of the Schottky diode receiver system, which may be applied for observations of middle atmospheric ozone and carbon monoxide thermal emission lines at frequencies 110.8 GHz and 115.3 GHz, respectively. The mixer of the front-end has utilized high-quality Schottky diodes that allowed us to reduce the mixer conversion loss. The combination of the mixer and an ultra-low-noise IF amplifier in the one integrated unit has resulted in double-sideband (DSB) receiver noise temperature of 260 K at a local oscillator (LO) frequency of 113.05 GHz in the instantaneous IF band from 1.7 to 2.7 GHz. This is the lowest noise temperature ever reported for an uncooled ozone receiver system with Schottky diode mixers.     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

Cryogenic cooling of mixers for millimeter and centimeter wavelengths

It is shown theoretically that cryogenically cooling a Schottky-barrier mixer only slightly increases the conversion loss while giving a considerable reduction in mixer noise. The d.c. bias and local oscillator drive must be appropriately scaled. Experimental results indicate that in conjunction with a cooled paramp IF amplifier, single-sideband (SSB) receiver noise temperatures of ~350 K at 85 GHz, and ~260 K at 33 GHz are presently obtainable-an improvement by a factor of 6 at 85 GHz and 4 at 33 GHz over current room-temperature mixer receivers. An unexplained source of noise within the diodes has been observed and if this can be eliminated a further factor of 2 improvement in noise temperature will be obtained.     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

45 GHz active HEMT mixer

A low-noise 45 GHz mixer has been realised using a high electron mobility transistor (HEMT). This is the first reported active mixer above 30 GHz and the first reported HEMT mixer. The mixer exhibits 1.5 dB maximum gain at 4 dBm local oscillator (LO) power and 8.1 dB noise figure, including a 2.6 dB NF IF amplifier, at 2 dBm LO power.     

基于GaAs肖特基二极管的330GHz接收前端技术研究

基于GaAs肖特基二极管,设计实现了310~330 GHz的接收机前端.接收机采用330 GHz分谐波混频器作为第一级电路,为降低混频器变频损耗,提高接收机灵敏度,分析讨论了反向并联混频二极管空气桥寄生电感和互感,采用去嵌入阻抗计算方法,提取了二极管的射频、本振和中频端口阻抗,实现了混频器的优化设计,提高了变频损耗仿真精度.接收机的165 GHz本振源由×6×2倍频链实现,其中六倍频采用商用有源器件,二倍频则采用GaAs肖特基二极管实现,其被反向串联安装于悬置线上,实现了偶次平衡式倍频,所设计的倍频链在165 GHz处输出约10 dBm的功率,用以驱动330 GHz接收前端混频器.接收机第二级电路采用中频低噪声放大器,以降低系统总的噪声系数.在310~330 GHz范围内,测得接收机噪声系数小于10.5 dB,在325 GHz处测得最小噪声系数为8.5 dB,系统增益为(31±1)dB.     

High Doping Density Schottky Diodes in the 3MM Wavelength Cryogenic Heterodyne Receiver

The paper describes a 3mm cryogenic mixer receiver using high doping density (“room-temperature”) Schottky diodes. The measured equivalent noise temperature T_eq of the diodes is 109 K at 20 K, which is much higher than the T_eq of the low doping density (“cryogenic”) diodes. In spite of this, the double-sideband (DSB) noise temperature of the cryogenic receiver developed is 55 K at 110 GHz, owing to the low conversion loss of the mixer and ultra-low noise of the PHEMT IF amplifier. This is the lowest noise temperature ever reported for a Schottky diode mixer receiver. The results obtained are useful for the development of submm receivers in which high doping density Schottky diodes are used.     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

Noise in RF-CMOS mixers: a simple physical model

Flicker noise in the mixer of a zero- or low-intermediate frequency (IF) wireless receiver can compromise overall receiver sensitivity. A qualitative physical model has been developed to explain the mechanisms responsible for flicker noise in mixers. The model simply explains how frequency translations take place within a mixer. Although developed to explain flicker noise, the model predicts white noise as well. Simple equations are derived to estimate the flicker and white noise at the output of a switching active mixer. Measurements and simulations validate the accuracy of the predictions, and the dependence of mixer noise on local oscillator (LO) amplitude and other circuit parameters     

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixer's IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.     

Cryogenic Millimeter-Wave Receiver Using Molecular Beam Epitaxy Diodes

A millimeter-wave cryogenic receiver has been built for the 60-90-GHz frequency band using GaAs mixer diodes prepared by molecuIar beam epitaxy (MBE). The diodes are mounted in a reduced-height image rejecting waveguide mixer which is followed by a cooled parametric amplifier at 4.5-5.0 GHz. At a temperature of 18 K the receiver has a total single-sideband (SSB) system temperature of 312 K at a frequency of 81 GHz. This is the lowest system temperature ever reported for a resistive mixer receiver. The low-noise operation of the mixer is seen to be a result of 1) the short-circuiting of the noise entering the image port and 2) an MBE mixer diode with a noise temperature which is consistent with the theoretical shot noise from the junction and the thermal noise from the series resistance.     

IIP2 Calibration by Injecting DC Offset at the Mixer in a Wireless Receiver

A major contributor to degraded input-referred second-order intercept point (IIP2) in integrated RF systems-on-chips is local oscillator (LO) leakage to the input of RF circuits. In this brief, we present a digital calibration technique for improving IIP2 by injecting controlled dc offset at the mixer output through a three-port network of switched-capacitor filters. The dc offset at mixer output gets up-converted to LO frequency at the input of RF circuits due to poor reverse isolation of the receiver front-end. By controlling the amplitude of the injected dc, IIP2 degradation due to LO leakage at the input of RF amplifiers can be compensated. Mathematical analysis is presented and supported by measurement data from a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process. Calibrated IIP2 of 50 dBm is reported for the receiver at low-noise amplifier input.     

A W-band image-rejection downconverter

The design, fabrication, and evaluation of a W-band image-rejection downconverter based on pseudomorphic InGaAs-GaAs HEMT technology are presented. The image-rejection downconverter consists of a monolithic three-stage low-noise amplifier, a monolithic image-rejection mixer, and a hybrid IF 90° coupler with an IF amplifier. The three-stage amplifier has a measured noise figure of 3.5 dB, with an associated small signal gain of 21 dB at 94 GHz while the image-rejection mixer has a measured conversion loss of 11 dB with +10 dBm LO drive at 94.15 GHz. Measured results of the complete image-rejection downconverter including the hybrid IF 90° coupler and a 10 dB gain amplifier show a conversion gain of more than 18 dB and a noise figure of 4.6 dB at 94.45 GHz     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

Design of a full-band CMOS UWB receiver and fast-hopping carrier generator for 3.1–10.6 GHz

This paper presents an interference rejection full-band UWB receiver and fast hopping carrier generator for 3.1–10.6 GHz. This receiver enables 11 bands of operation by embedding a tunable notch filter to eliminate interferers in a 5 GHz wireless local area network. The carrier generator can cover 3.1–10.6 GHz within less than 9.5 ns. The receiver, based on the proposed multi-band OFDM standard, consists of a zero-IF receive chain and required system noise figure, the receiver linearity specifications of which are discussed in this paper. It consists of a single-ended low-noise amplifier (LNA), a down-conversion mixer, a low-pass filter (LPF), and a programmable gain amplifier with an IO buffer. The LNA employs a common-gate topology of the 1st stage with dual-resonant loads, a cascade amplifier of the 2nd stage for mid-band resonance, and a tunable notch filter. The down-conversion mixer adopts a single-balanced architecture with LO cancellation. The LPF is implemented based on an active RC topology, and implements a four-stage programmable gain amplifier. The receiver dissipates 49.3 mA from a 1.8 V power supply. The average voltage conversion gain of the receiver IC is 73.5 dB, and the system noise figure is 8.4 dB. Input P1dB increases from ?36.8 dBm at 4 GHz to ?30.5 dBm at 10.3 GHz. The attenuation is 8.5 dB, which is achieved in the interference rejection band at 5.2 GHz. It occupies an area of 0.98 × 3.3 mm² including the bond pads.     

A Very Low-Noise Single-Sideband Receiver for 200-260 GHz

A cryogenic Schottky diode mixer receiver has been built for the 230-GHz region with true single-sideband operation and a receiver noise temperature as low as 330 K. Local oscillator power is provided by a frequency tripler, with LO injection and sideband filtering accomplished through quasi-optical interferometers. The image sideband is terminated in a cryogenic load with an effective temperature of 33 K. The IF bandwidth is 600 MHz with nearly flat noise, and the RF band is nearly flat over 50 GHz using backshort tuning of the mixer.