900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA RF receiver ICs with a new mixer linearization method and optimization of integrated inductor for single balance mixer LO buffer

900 MHz CDMA, 1.8 GHz PCS, and 450 MHz CDMA RF receivers are implemented and measured. In order to reduce NRE cost and meet the demand of fast time-to-market, a metal-mask configurable method is applied for those receivers using only upper metals, contact and via layers. Also to reduce power consumption, a new mixer linearization method is proposed, along with an optimization methodology of an integrated inductor for a single balance mixer LO buffer, with respect to power consumption and silicon area. In order to apply the proposed inductor optimization methodology into metal-mask configurable circuits, inductor design considerations for metal-mask variant circuits are presented. With the proposed linearization technique and inductor optimization method, low power 900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA mixers are obtained. The proposed receivers are fabricated in a 0.35 μm SiGe BiCMOS process. In the 900 MHz CDMA case, measurement results of the proposed mixer show 12 dBm IIP3 and 10.2 dB conversion gain, and 7.5 dB SSB NF with 10.5 mA current consumption at 2.7 V supply voltage.     

An SOI LDMOS/CMOS/BJT technology for integrated power amplifiersused in wireless transceiver applications

This paper describes a SOI LDMOS/CMOS/BJT technology that can be used in portable wireless communication applications. This technology allows the complete integration of the front-end circuits with the baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 μm channel length, 3.8 μm drift length, 4.5 GHz f_T and 21 V breakdown voltage), CMOS transistors (1.5 μm channel length, 0.8/-1.2 V threshold voltage), lateral NPN transistor (18 V BV_CBO and h _FE of 20), and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated     

Micropower circuits for bidirectional wireless telemetry in neural recording applications

State-of-the art neural recording systems require electronics allowing for transcutaneous, bidirectional data transfer. As these circuits will be implanted near the brain, they must be small and low power. We have developed micropower integrated circuits for recovering clock and data signals over a transcutaneous power link. The data recovery circuit produces a digital data signal from an ac power waveform that has been amplitude modulated. We have also developed an FM transmitter with the lowest power dissipation reported for biosignal telemetry. The FM transmitter consists of a low-noise biopotential amplifier and a voltage controlled oscillator used to transmit amplified neural signals at a frequency near 433 MHz. All circuits were fabricated in a standard 0.5-microm CMOS VLSI process. The resulting chip is powered through a wireless inductive link. The power consumption of the clock and data recovery circuits is measured to be 129 microW; the power consumption of the transmitter is measured to be 465 microW when using an external surface mount inductor. Using a parasitic antenna less than 2 mm long, a received power level was measured to be -59.73 dBm at a distance of one meter.     

140Mb/s混合集成光接收机

本文报导了140Mb/s混合集成光接收机的研制结果。接收机全部由厚膜电路集成模块组成。其主放带宽为200MHz(3dB),输出电压V_(pp)值为0.8V,接收灵敏度在10~(-9)误码率下为-39dBm。     

Monolithic integration of GaAs/AlGaAs LED and Si driver circuit

A GaAs/AlGaAs LED has been monolithically integrated with a Si driver circuit composed of ten MOSFETs. The LED replaces the output pad of a 2- μm design rule, standard Si output buffer circuit, so that the overall area remains the same. By applying a stream of voltage pulses to the input of the driver circuit, the LED output has been modulated at rates exceeding 100 MHz     

Pulse-modulated analog neuron circuits

Analog neuron circuits based on both frequency modulation and pulse modulation are investigated. The circuits are compared in terms of size, power, performance, and reliability; frequency modulation shows advantages in each area. Test circuits were designed and fabricated in 2μm CMOS technology. The frequency modulated neuron has an operational frequency of 3.125 MHz and a dynamic range of 17 bits. Our results indicate that this circuit technique may provide substantial advantages in high-performance, low-power neural systems.     

A 6-GHz integrated phase-locked loop using AlGaAs/GaAsheterojunction bipolar transistors

A fully integrated 6-GHz phase-locked-loop (PLL) fabricated using AlGaAs/GaAs heterojunction bipolar transistors (HBTs) is described. The PLL is intended for use in multigigabit-per-second clock recovery circuits for fiber-optic communication systems. The PLL circuit consists of a frequency quadrupling ring voltage-controlled oscillator (VCO), a balanced phase detector, and a lag-lead loop filter. The closed-loop bandwidth is approximately 150 MHz. The tracking range was measured to be greater than 750 MHz at zero steady-state phase error. The nonaided acquisition range is approximately 300 MHz. This circuit is the first monolithic HBT PLL and is the fastest yet reported using a digital output VCO. The minimum emitter area was 3 μm×10 μm with f_t=22 GHz and f_max=30 GHz for a bias current of 2 mA. The speed of the PLL can be doubled by using 1-μm×10-μm emitters in next-generation circuits. The chip occupies a die area of 2-mm×3-mm and dissipates 800 mW with a supply voltage of -8 V     

A high performance monolithic In0.53Ga0.47Asvoltage-tunable transimpedance amplifier

The fabrication and performance of the first monolithically integrated In_0.53Ga_0.47As JFET voltage-tunable transimpedance amplifier for use in InP-based optoelectronic integrated circuits are reported. A narrow-gate transistor is used as an active feedback resistor. The two-stage voltage amplifier has a voltage gain of 10.7 and a bandwidth of 350 MHz. The closed-loop transimpedance of the amplifier is tunable from 10 to 24 kΩ by controlling the gate bias of the feedback transistor     

Pulse-modulated analog neuron circuits

Analog neuron circuits based on both frequency modulation and pulse modulation are investigated. The circuits are compared in terms of size, power, performance, and reliability; frequency modulation shows advantages in each area. Test circuits were designed and fabricated in 2µm CMOS technology. The frequency modulated neuron has an operational frequency of 3.125 MHz and a dynamic range of 17 bits. Our results indicate that this circuit technique may provide substantial advantages in high-performance, low-power neural systems.     

An integrated optic RE spectrum analyzer in a ZnO-GaAs-AlGaAswaveguides

A report is presented on the realization of an integrated optic RF spectrum analyzer (IOSA) that combines a wideband acoustooptic Bragg cell and a pair of waveguide lenses in ZnO/GaAs/Al_0.15Ga_0.85As composite waveguide 7×23 mm² in size. A total of 10 and 40 channels at the center frequencies of 167 MHz and 500 MHz, respectively, and a frequency resolution of 5.5 MHz were realized. The diffraction efficiencies of 11.5%/W and 4.0%/W of RF drive power at the center frequencies of 167 MHz and 500 MHz, respectively, and a dynamic range larger than 16 dB were measured. Further integration of this IOSA (integrated optic spectrum analyzer) with a laser source, a photodetector array, and electronic driving circuits could produce a monolithically integrated optic RF spectrum analyzer     

High-Temperature Operation of AlGaN/GaN HEMTs Direct-Coupled FET Logic (DCFL) Integrated Circuits

This letter presents the high-temperature performance of AlGaN/GaN HEMT direct-coupled FET logic (DCFL) integrated circuits. At 375 degC, enhancement-mode (E-mode) AlGaN/GaN HEMTs which are used as drivers in DCFL circuits exhibit proper E-mode operation with a threshold voltage (V_TH) of 0.24 V and a peak current density of 56 mA/mm. The monolithically integrated E/D-mode AlGaN/GaN HEMTs DCFL circuits deliver stable operations at 375 degC: An E/D-HEMT inverter with a drive/load ratio of 10 exhibits 0.1 V for logic-low noise margin (NM_L) and 0.3 V for logic-high-noise margin (NM_H) at a supply voltage (V_DD) of 3.0 V; a 17-stage ring oscillator exhibits a maximum oscillation frequency of 66 MHz, corresponding to a minimum propagation delay ( tau_pd) of 446 ps/stage at V_DD of 3.0 V     

Base diffusion isolated transistors for low power integrated circuits

Base diffusion isolated transistors (BDI) designed for low power, nonsaturating, integrated circuits have been fabricated. Buried collectors are unnecessary in these low power devices, resulting in structures equivalent to discrete transistors in complexity of fabrication. A low-current power supply is required for isolation purposes. Transistor characteristics differ negligibly from those of standard transistors at collector currents <0.05 mA, and are satisfactory for application in linear circuits at currents up to at least 0.1 mA. Transistor fTis 80 MHz at 0.1 mA emitter current, 2 V collector voltage.     

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.     

Digital DPCM Codec for TV Signals Based onDeltaM/DPCMDigital Conversions

A digital differential pulse-code modulation (DPCM) codec based on ΔM/DPCM and DPCM/ΔM digital conversions is presented as an equivalent replacement of a conventional DPCM codec for TV signals by using digital processing technology. A generalized model and equivalent circuit are shown for the digital DPCM codec, and transfer characteristics and quantizing noises are analyzed. The digital DPCM codec is designed for 1-MHz TV signals and the performance is verified by experiments. By the use of double integration ΔM and digital filter technology, it is shown that at the ΔM sampling rate of 16 MHz the overall SNR performance is sufficiently good for use as a conventional DPCM codec, and the digital code converters can be realized with commercially available transistor-transistor-logic (TTL) medium-scale-integrated (MSI) circuits and low-power emitter-coupled-logic (ECL) integrated circuits (IC's).     

L, C and X band integrated synthetic aperture radar (SAR) receiver

An integrated receiver consisting of RF front ends, analog baseband (BB) chain with an analog to digital converter (ADC) for a synthetic aperture radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm². The RF front end consists of three parallel signal channel intended for L, C and X-band of the SAR receiver. The BB is selectable between 50 and 160 MHz bandwidths through switches. The ADC has selectable modes of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 and 37 dB and noise figure of 11 and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz BB and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz BB and 8 bit mode ADC.     

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits

A full-HD (1080p30) 500 MHz mobile application processor with an H.264 HP/MPEG-2/MPEG-4 video codec is integrated on a 6.4 × 6.5 mm² die in 65 nm low-power CMOS. With two parallel pipelines for macroblock processing and tile-based address translation circuits, the processor consumes 342 mW in real-time playback of a full-HD H.264 stream from a 64 b width low-power DDR-SDRAM at an operating frequency of 166 MHz at 1.2 V.     

2.24-Gbit/s 151-km optical transmission system using high-speedintegrated silicon circuits

Optical transmission experiments performed at 2.24 Gb/s using standard single-mode fiber with dispersion zero at 1.3 μm are discussed. In the optical transmitter, a 1.5-μm-wavelength distributed feedback laser is directly modulated by means of a special electrical drive pulse shaping technique. A link length of up to 151 km is bridged. This is the longest repeater distance at 2 Gb/s using direct detection without optical amplifiers reported so far. Moreover, the transmission system includes multiplexing and demultiplexing equipment using specially developed high-speed silicon integrated circuits. The whole system is assembled in a version suitable for field trial applications     

A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $Sigma Delta$ Modulator

Although SigmaDelta modulators have largely been implemented as discrete-time (DT) circuits, a continuous-time (CT) approach offers significant advantages for realizing high-accuracy A/D converters at signal bandwidths where technology considerations may impose significant constraints. A CT design allows for relaxed amplifier unity-gain frequency and power requirements, which can enable the realization of high-resolution modulators with bandwidths of several MHz or more at low power. It also provides the advantage of inherent anti-aliasing filtering. This paper introduces a hybrid CT/DT SigmaDelta modulator for A/D conversion that combines the benefits of CT and DT circuits, while mitigating the challenges associated with CT design. The second-order first stage of a two-stage cascade is implemented in CT, while the first-order second stage is a DT circuit. An experimental prototype of the proposed modulator, integrated in 0.18-mum CMOS technology, operates from a 1.2-V analog supply to allow for easier migration to a 0.13-mum or 90-nm CMOS technology. The prototype achieves a dynamic range of 77 dB, a peak SNR of 71 dB, a peak SNDR of 67 dB, and worst-case anti-aliasing filtering of 48 dB for a signal bandwidth of 7.5 MHz and a sampling rate of 240 MHz. The total power dissipation is 89 mW, including 63.6 mW of analog power.     

Wide-band guided-wave acoustooptic Bragg cells in GaAs-GaAlAs waveguide

One of the key components in future GaAs-based monolithic integrated acoustooptic modules or circuits is an efficient and wide-band acoustooptic Bragg cell. In this paper, design, fabrication, and performance characteristics of compact miniaturized GaAs-GaAlAs waveguide acoustooptic Bragg cells that operate at the acoustic frequency from 190 to 625 MHz are reported. A 201 MHz bandwidth has been obtained with the Bragg cell that employs a single tilted-finger chirp transducer centering at 360 MHz. The acoustic propagation losses in the GaAs-GaAlAs waveguides that were measured using acoustooptic Bragg diffraction as a probe are also presented.     

A 900-MHz fully integrated SOI power amplifier for single-chipwireless transceiver applications

This paper presents a silicon-on-insulator (SOI) fully integrated RF power amplifier for single-chip wireless transceiver applications. The integrated power amplifier (IPA) operates at 900 MHz, and is designed and fabricated using a 1.5-μm SOI LDMOS/CMOS/BJT technology. This technology is suitable for the complete integration of the front-end circuits with the baseband circuits for low-cost low-power high-volume production of single-chip transceivers. The IPA is a two-stage Class E power amplifier. It is fabricated along with the on-chip input and output matching networks. Thus, no external components are needed. At 900 MHz and with a 5-V supply, the power amplifier delivers 23-dBm output power to a 50-Ω load with 16-dB gain and 49% power-added efficiency