一种clock mesh与H-tree混合时钟树设计方法

本文提出了一种clock mesh与H-tree相结合的混合时钟树设计方法,同时通过对设计中的寄存器按照一定规则进行分组并分别布局在相同大小的网格中从而具备一定的对称性和规则性,可更好的优化H-tree结构,提高H-tree的性能从而提高了整个混合时钟树的性能。实验表明,该混合时钟树结构可显著减少时钟树长度和时钟分支间的skew,降低OCV影响。     

用Encounter实现Mesh-Local-Tree结构的时钟设计流程

提出了一种实用的设计流程,即在Cadencd公司的Encounter环境中去实现对网格 本地树(MLT)时钟结构的综合与分析方法.对一个实际工业设计试验的数据表明:运用Clockmesh CRS的综合方式,MLT的时钟架构相对于单一的树结构能够实现更小的时钟偏差(114ps、 171ps).同时,将这种设计流程运用于其他设计中,以比较MLT和CTS不同的设计流程.结果显示,MLT的时钟架构可以实现更小的时钟偏差,同时还可以降低缓冲器的数量,这样也弥补了单一网格结构的功耗问题.     

ASIC后端设计中的时钟偏移以及时钟树综合

目前的ASIC设计中,时钟偏移成为限制系统时钟频率的主要因素,时钟树综合技术通过在时钟网络中插入缓冲器来减小时钟偏移.但是,有时这样做并不能达到系统要求的时钟偏移.以一款SMIC 0.18μm工艺的DVBT数字电视解调芯片为例,分析了时钟偏移的产生原因.介殚绍了使用Synopsys公司Astro工具进行时钟树综合的方法,重点分析了在时钟树综合之前如何设置约束手动优化电路从而改善设计的时序,最后的流片结果证明该方法是有效的.     

ASIC设计中时钟偏移分析

目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战、文章分析了时钟偏移的产生机理,然后提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,最后还分析了如何利用有用的时钟偏移来改善电路的时序。     

基于Astro的时钟树综合

时钟树综合是芯片后端设计至关重要的一环,时钟偏差成为限制系统时钟频率的主要因素。本文以一款TSMC0．25μm工艺的RISC微处理器芯片为例．介绍了使用Synopsys公司的P8LR工具Astro进行时钟树综合和优化的方法,并与Silicon Ensemble在综合后的时钟偏差上作了对比,结果显示使用前者比后者时钟偏差减小百分之十四以上。     

微处理器时钟分布技术分析

当今高性能系统需要低偏斜的时钟分布网络.在同步数字系统中,时钟分布网络的设计是一个巨大的挑战,对时钟严格的控制是系统正确工作的关键.和系统中其它信号相比,时钟信号的负载电容大,布线长度长,扇出点多而且具有快速的开关频率,导致了时钟分布网络的设计困难.随着微处理器频率的不断提升及工艺的不断发展,对于时钟设计的要求更加严格,时钟网络设计是影响系统总体性能的一个重要因素.本文介绍了影响时钟分布网络相关的一些基本概念,并就微处理器中的各种时钟分布方法进行了简要分析.     

基于门控时钟技术的IC低功耗设计

随着数字集成电路(IC)设计的规模不断增加,降低功耗变得愈加重要。通过对门控时钟技术实现方法的分析,介绍了门控时钟技术降低功耗的有效性。通过应用实例,对逻辑设计门控和存储器门控的具体实现方法进行了详细分析,证明了门控时钟技术能够在不增加物理设计复杂度的前提下,有效降低功耗。同时门控时钟技术还可以改善时序和芯片面积,对现有设计流程不会造成任何影响。     

ASIC设计中时钟偏移分析

目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战.分析了时钟偏移的产生机理,提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,以及如何利用有用的时钟偏移来改善电路的时序.     

基于不同映射的光传送网的时钟性能仿真

文章对光传送网(OTN)新的体系架构进行了建模,运用一种新的映射方式将客户信号适配到OTN模型中进行传送.通过对接收端时钟和理想时钟的对比,分析了新旧映射方式对OTN时钟性能产生的影响,证明了新映射方法具有对时钟性能影响更小的优点.此模型和所得结论可帮助光网络系统设计人员在系统设计前衡量和分析网络时钟的性能,以及预估各种映射方式对时钟性能的影响.     

时钟树综合中的有效时钟偏移

为了解决用传统时钟树综合策略来设计芯片只能尽量减小时钟偏移,而不能满足时序收敛的问题,文中引入了有效时钟偏移的概念,并通过在TSMC0.13μm工艺下流片成功的芯片BES7000作为设计实例,分析了有效时钟偏移引入之后对改进时序建立时间的效果。     

低偏斜、高变化容忍的层次化无缓冲谐振时钟分布网络

无缓冲谐振时钟分布网络能够最小化同步系统的时钟功耗。但由于没有缓冲器,时钟网络的偏斜受到多方面因素的影响,例如时钟互连线寄生参数的差异,非平衡时钟负载以及工艺、电压温度变化。本文提出了一种层次化的两相无缓冲谐振时钟互连网络结构,将网格型和树型结构的各自优点相结合。在TSMC 65nm标准CMOS工艺下,通过一个流水线乘法器电路分析了该结构时钟网络的偏斜及变化容忍特性。版图后仿真结果表明,层次化时钟网络的偏斜分别比纯网格和纯H树结构时钟网络降低超过75%和65%,而且在非平衡时钟负载或工艺、电压温度变化的情况下,时钟网络偏斜最高小于7ps,不超过整个时钟周期（约760ps）的1%。     

Simultaneous switching noise reduction by resonant clock distribution networks

Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.     

一种10ps以下时钟偏差的纯数字电路分频器设计

本文对一款常用任意整数分频器进行改进,提出了一种纯数字、低时钟偏差、可获得任意整数分频结果的时钟分频器设计方案.该分频器由计数器与输出锁存器构成,通过调节逻辑结构与线延迟,完全平衡各时钟传播路径,大幅降低时钟偏差.仿真结果表明,在TSMC 0.13μm CMOS工艺下,当输入时钟频率在600MHz时,时钟偏差可控制在10ps以内.该分频器还包含自测电路,可判断时钟偏差是否满足要求.     

Hierarchical distribution network for low skew and high variation-tolerant bufferless resonant clocking

We propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes the advantages of mesh and tree architectures.The problems of skew reduction and variation-tolerance in the mixed interconnection network are studied through a pipelined multiplier under a TSMC 65 nm standard CMOS process.The post-simulation results show that the hierarchical architecture reduces more than 75% and 65%of clock skew compared with pure mesh and pure H-tree networks,respectively.The maximum skew in the proposed clock distribution is less than 7 ps under imbalanced loading and PVT variations,which is no more than 1%of the clock cycle of about 760 ps.     

Discharge-path-based antenna effect detection and fixing for X-architecture clock tree

Antenna effect is a phenomenon in the plasma-based nanometer process and directly influences the manufacturing yield of VLSI circuits. Because antenna-critical metal wires have sufficient charges to damage the thin gate oxides of the clock input ports connected by a clock tree, the standard cells or IPs cannot be driven by the clock source synchronously. For a given X-architecture clock tree that connects n clock sinks, we consider the antenna effect in the clock tree and propose a discharge-path-based antenna effect detection method. To fix the antenna violations, we use the jumper insertion technique recommended by foundries. Furthermore, we integrate the layer assignment technique to reduce the inserted jumper and via counts. Differing from the existing works, the delay of vias is considered in delay calculation, and a wire sizing technique is applied for clock skew compensation after fixing the antenna violations. Experimental results on benchmarks show that our algorithm runs in O(n²) to averagely insert 48.21% less jumpers and reduce 20.35% in vias compared with other previous algorithms. Moreover, the SPICE simulation further verifies the correctness of the resulting clock tree.     

Design methodology for synthesizing clock distribution networksexploiting nonzero localized clock skew

An integrated top-down design methodology is presented in this brief for synthesizing high performance clock distribution networks based on application dependent localized clock skew. The methodology is divided into four phases: (1) determining an optimal clock skew schedule composed of a set of nonzero clock skew values and the related minimum clock path delays; (2) designing the topology of the clock distribution network with delays assigned to each branch based on the circuit hierarchy, the aforementioned clock skew schedule, and minimizing process and environmental delay variations; (3) designing circuit structures to emulate the delay values assigned to the individual branches of the clock tree; and (4) designing the physical layout of the clock distribution network. The clock distribution network synthesis methodology is based on CMOS technology. The clock lines are transformed from distributed resistive capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. Variations in process parameters are considered during the circuit design of the clock distribution network to guarantee a race-free circuit. Nominal errors of less than 2.5% for the delay of the clock paths and 7% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demonstrated     

Fast clock scheduling and an application to clock tree synthesis

Clock networks are required to be constructed with adequate safety margins in the skew constraints to operate correctly even under the influence of variations. In this work, a scalable clock scheduler is developed to drive a synthesis framework that constructs useful skew clock trees with large safety margins that are tailored to the tree topology. Sequential elements are clustered early in the topology, if it is impossible provide adequate robustness to variations using only safety margins. Compared to earlier studies, the proposed framework performs the clock scheduling one to two orders of magnitude faster and improves yield and capacitive cost on several synthesized circuits.     

Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis

A 3D stacked IC is made of multiple dies possibly with heterogeneous process technologies. Therefore, the die-to-die variation between the stacked dies creates on-package variation in a 3D chip. In this paper, we analyze the effect of on-package variation on the 3D clock trees and address the problem of on-package variation aware layer embedding in 3D clock tree synthesis. The layer embedding problem is divided into two sub-problems: clock node embedding and clock edge embedding. While the clock node embedded problem has been intensively investigated by the previous 3D clock tree synthesis flows because the solution directly determines the TSV allocation, the clock edge embedding problem has not been fully addressed yet. We show in this work that a careful clock edge embedding can greatly reduce the impact of on-package variation on the 3D clock skew, thereby enhancing chip yield, and propose a two-step solution to the problem of on-package variation aware layer embedding of clock edges. Specifically, we formulate the edge embedding problem into a problem of maximizing the sharing of layers among the clock paths to minimize the impact of on-package variation globally and solve it efficiently, followed by applying a fine-grained refinement technique to balance the clock latency locally among the clock paths. From the experiments with Benchmark circuits, we confirm that compared to the results produced by the conventional on-package variation unaware layer embedding of clock edges, the proposed algorithm is able to improve the chip yield by 6.2–25.8% and 5.3–44.4% for 2-layered and 4-layered 3D designs, respectively.     

多时钟源分割方法在时钟树综合中的应用

本文以sha256算法模块的数字后端物理设计为例,提出了将多时钟源分割技术应用在传统时钟树综合中的方法。应用该方法后,利用有效时钟偏移,仅通过少量时钟缓冲器的插入就解决了该模块设计中的建立时间违例问题,大大降低了后续时序收敛工作的复杂度,将时序修复耗时缩短为采用传统方法的20%。     

基才labview闹钟的设计

通过虚拟仪器技术labview,来设计闹钟。设计出来的闹钟通过实践验证．实现了预定的功能。运用labview设计闹钟有自身独特的优点：编程方法简单,增加功能方便。